coreboot-gerrit December 2022

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[S] Change in coreboot[master]: 3rdparty/fsp: Update submodule pointer to latest master
by Felix Held (Code Review) 02 Dec '22

02 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70153 ) Change subject: 3rdparty/fsp: Update submodule pointer to latest master ...................................................................... 3rdparty/fsp: Update submodule pointer to latest master Here are the FSP updates with latest master: - IoT EHL MR5 - IoT ADL-P MR2 - IoT ADL-S MR3 - IoT ADL-PS PV - IoT TGL MR7 Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: If4a76fe25c7b7a2c34e5bb284418c01c77b22abb Reviewed-on: https://review.coreboot.org/c/coreboot/+/70153 Reviewed-by: Marvin Drees <marvin.drees(a)9elements.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M 3rdparty/fsp 1 file changed, 22 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Marvin Drees: Looks good to me, but someone else must approve diff --git a/3rdparty/fsp b/3rdparty/fsp index 12160fe..2047412 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 12160fe64bc1caaba3c2d6be44da0cd8787a2561 +Subproject commit 204741228d90f74e9926343083b8059cd16740b7 -- To view, visit https://review.coreboot.org/c/coreboot/+/70153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4a76fe25c7b7a2c34e5bb284418c01c77b22abb Gerrit-Change-Number: 70153 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/meteorlake: Refactor `pmc_lockdown_cfg` function
by Felix Held (Code Review) 02 Dec '22

02 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70132 ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/meteorlake: Refactor `pmc_lockdown_cfg` function ...................................................................... soc/intel/meteorlake: Refactor `pmc_lockdown_cfg` function This patch refactors the `pmc_lockdown_cfg()` to remove the helper functions and uses the `setbits32` function to enforce bit locking as applicable. This patch also locks PMC features like: 1. Debug mode configuration and host read access to PMC XRAM. 2. PMC soft strap message interface. 3. PMC static function. and then calls into the PMC IPC function that informs about PCI enumeration. Port of - 1. commit 2eec87a553ec ("soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function") 2. commit bae4a0b5a1e4 ("soc/intel/alderlake: Implement PMC feature lock") 3. commit c2570dc99800 ("soc/intel/alderlake: Implement PMC soft strap interface lock") 4. commit f021952c4067 ("soc/intel/alderlake: Implement PMC static function lock") 5. commit 457891415380 ("soc/intel/alderlake: Call into PMC IPC to inform PCI enumeration done") BUG=none TEST=Boot to OS on google/rex. Register values in OS - # busybox devmem 0xfe0018d4 32 #bit31 0x80000000 # busybox devmem 0xfe001024 32 #bit21,18,17,4 0x00362610 # busybox devmem 0xfe001818 32 #bit27,22 0x2B4F0004 # busybox devmem 0xfe00104c 32 #bit0 0x00000001 Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I3622748d8fecef69c60bb3fe9bfe68fc126764b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70132 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/meteorlake/include/soc/pmc.h M src/soc/intel/meteorlake/lockdown.c 2 files changed, 73 insertions(+), 40 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/include/soc/pmc.h b/src/soc/intel/meteorlake/include/soc/pmc.h index a56c290..813930b 100644 --- a/src/soc/intel/meteorlake/include/soc/pmc.h +++ b/src/soc/intel/meteorlake/include/soc/pmc.h @@ -51,6 +51,7 @@ #define SLEEP_AFTER_POWER_FAIL (1 << 0) #define GEN_PMCON_B 0x1024 +#define ST_FDIS_LOCK (1 << 21) #define SLP_STR_POL_LOCK (1 << 18) #define ACPI_BASE_LOCK (1 << 17) #define PM_DATA_BAR_DIS (1 << 16) @@ -76,6 +77,10 @@ #define PRSTS 0x1810 +#define PM_CFG 0x1818 +#define PM_CFG_DBG_MODE_LOCK (1 << 27) +#define PM_CFG_XRAM_READ_DISABLE (1 << 22) + #define S3_PWRGATE_POL 0x1828 #define S3DC_GATE_SUS (1 << 1) #define S3AC_GATE_SUS (1 << 0) @@ -96,7 +101,7 @@ #define DSX_EN_LAN_WAKE_PIN (1 << 0) #define DSX_CFG_MASK (0x1f << 0) -#define PMSYNC_TPR_CFG 0x18C4 +#define PMSYNC_TPR_CFG 0x18d4 #define PCH2CPU_TPR_CFG_LOCK (1 << 31) #define PCH2CPU_TT_EN (1 << 26) diff --git a/src/soc/intel/meteorlake/lockdown.c b/src/soc/intel/meteorlake/lockdown.c index 51fbdaf..b4ccbab 100644 --- a/src/soc/intel/meteorlake/lockdown.c +++ b/src/soc/intel/meteorlake/lockdown.c @@ -3,6 +3,7 @@ #include <device/mmio.h> #include <intelblocks/cfg.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelpch/lockdown.h> #include <soc/pcr_ids.h> #include <soc/pm.h> @@ -12,51 +13,27 @@ #define PCR_PSTH_CTRLREG 0x1d00 #define PSTH_CTRLREG_IOSFPTCGE (1 << 2) -static void pmc_lock_pmsync(void) -{ - uint8_t *pmcbase; - uint32_t pmsyncreg; - - pmcbase = pmc_mmio_regs(); - - pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); - pmsyncreg |= PCH2CPU_TPR_CFG_LOCK; - write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); -} - -static void pmc_lock_abase(void) -{ - uint8_t *pmcbase; - uint32_t reg32; - - pmcbase = pmc_mmio_regs(); - - reg32 = read32(pmcbase + GEN_PMCON_B); - reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK); - write32(pmcbase + GEN_PMCON_B, reg32); -} - -static void pmc_lock_smi(void) -{ - uint8_t *pmcbase; - uint8_t reg8; - - pmcbase = pmc_mmio_regs(); - - reg8 = read8(pmcbase + GEN_PMCON_B); - reg8 |= SMI_LOCK; - write8(pmcbase + GEN_PMCON_B, reg8); -} - static void pmc_lockdown_cfg(int chipset_lockdown) { + uint8_t *pmcbase = pmc_mmio_regs(); + /* PMSYNC */ - pmc_lock_pmsync(); + setbits32(pmcbase + PMSYNC_TPR_CFG, PCH2CPU_TPR_CFG_LOCK); /* Lock down ABASE and sleep stretching policy */ - pmc_lock_abase(); + setbits32(pmcbase + GEN_PMCON_B, SLP_STR_POL_LOCK | ACPI_BASE_LOCK); if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) - pmc_lock_smi(); + setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK); + + if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) { + setbits32(pmcbase + GEN_PMCON_B, ST_FDIS_LOCK); + setbits32(pmcbase + SSML, SSML_SSL_EN); + setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK | + PM_CFG_XRAM_READ_DISABLE); + } + + /* Send PMC IPC to inform about PCI enumeration done */ + pmc_send_pci_enum_done(); } static void soc_die_lockdown_cfg(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/70132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3622748d8fecef69c60bb3fe9bfe68fc126764b7 Gerrit-Change-Number: 70132 Gerrit-PatchSet: 7 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: nb/intel/i945: Use boolean for gpu_lvds_use_spread_spectrum_clock
by Felix Held (Code Review) 02 Dec '22

02 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70149 ) Change subject: nb/intel/i945: Use boolean for gpu_lvds_use_spread_spectrum_clock ...................................................................... nb/intel/i945: Use boolean for gpu_lvds_use_spread_spectrum_clock Change-Id: I5f11bde99dfcde81c9dc62c1102330c0a6c16e04 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70149 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/x60/devicetree.cb M src/northbridge/intel/i945/chip.h 4 files changed, 18 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 833d658..a7832ef 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -5,7 +5,7 @@ register "gfx" = "GMA_STATIC_DISPLAYS(0)" register "gpu_hotplug" = "0x00000220" - register "gpu_lvds_use_spread_spectrum_clock" = "1" + register "gpu_lvds_use_spread_spectrum_clock" = "true" register "pwm_freq" = "180" register "gpu_panel_power_up_delay" = "250" register "gpu_panel_power_backlight_on_delay" = "2380" diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index c77af6b..7a9e9ae 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -5,7 +5,7 @@ register "gfx" = "GMA_STATIC_DISPLAYS(0)" register "gpu_hotplug" = "0x00000220" - register "gpu_lvds_use_spread_spectrum_clock" = "1" + register "gpu_lvds_use_spread_spectrum_clock" = "true" register "pwm_freq" = "275" register "gpu_panel_power_up_delay" = "250" register "gpu_panel_power_backlight_on_delay" = "2380" diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index d56ec51..a41749a 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -5,7 +5,7 @@ register "gfx" = "GMA_STATIC_DISPLAYS(0)" register "gpu_hotplug" = "0x00000220" - register "gpu_lvds_use_spread_spectrum_clock" = "1" + register "gpu_lvds_use_spread_spectrum_clock" = "true" register "pwm_freq" = "180" register "gpu_panel_power_up_delay" = "250" register "gpu_panel_power_backlight_on_delay" = "2380" diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 0de0e58..8153462 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -4,6 +4,7 @@ #define NORTHBRIDGE_INTEL_I945_CHIP_H #include <drivers/intel/gma/i915.h> +#include <types.h> struct northbridge_intel_i945_config { /* In units of 100us timer */ @@ -17,7 +18,7 @@ u32 gpu_hotplug; u32 pwm_freq; - int gpu_lvds_use_spread_spectrum_clock; + bool gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; int pci_mmio_size; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/70149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f11bde99dfcde81c9dc62c1102330c0a6c16e04 Gerrit-Change-Number: 70149 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: nb/intel/i945: Use boolean for gpu_lvds_use_spread_spectrum_clock
by Felix Held (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Elyes Haouas. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70149 ) Change subject: nb/intel/i945: Use boolean for gpu_lvds_use_spread_spectrum_clock ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f11bde99dfcde81c9dc62c1102330c0a6c16e04 Gerrit-Change-Number: 70149 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 02 Dec 2022 14:44:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/pineview: Remove unused 'gpu_lvds_use_spread_spectrum_clock'
by Felix Held (Code Review) 02 Dec '22

02 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70147 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: nb/intel/pineview: Remove unused 'gpu_lvds_use_spread_spectrum_clock' ...................................................................... nb/intel/pineview: Remove unused 'gpu_lvds_use_spread_spectrum_clock' 'gpu_lvds_use_spread_spectrum_clock'is only used on i945. Change-Id: I0f63f18d3f57ef8774f22ca9eb8c20dd39c56cdc Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70147 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/pineview/chip.h 1 file changed, 15 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/northbridge/intel/pineview/chip.h b/src/northbridge/intel/pineview/chip.h index 6d67969..ce873b9 100644 --- a/src/northbridge/intel/pineview/chip.h +++ b/src/northbridge/intel/pineview/chip.h @@ -9,7 +9,6 @@ /* GMA */ bool use_crt; bool use_lvds; - int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/70147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f63f18d3f57ef8774f22ca9eb8c20dd39c56cdc Gerrit-Change-Number: 70147 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add timestamp for cse_fw_sync
by Subrata Banik (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Tarun Tuli, Dinesh Gehlot, Paul Menzel. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70172 ) Change subject: soc/intel/meteorlake: Add timestamp for cse_fw_sync ...................................................................... Patch Set 10: -Code-Review (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/70172/comment/e9173a98_fe0e5ddd PS1, Line 7: soc/intel/meteorlake: Add timestamp for cse_fw_sync The patch add timestamp around cse_fw_sync(). BUG=none TEST=Verified on Brya, cbmem -t: 948:starting CSE firmware sync 1,340,551 (50,657) 949:finished CSE firmware sync 1,379,348 (38,797) Port of commit 7c6dd796f26f (“soc/intel/alderlake: Add timestamp for cse_fw_sync”) \ please fix the commit msg -- To view, visit https://review.coreboot.org/c/coreboot/+/70172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9 Gerrit-Change-Number: 70172 Gerrit-PatchSet: 10 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 02 Dec 2022 14:40:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}
by Felix Held (Code Review) 02 Dec '22

02 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70114 ) Change subject: sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary} ...................................................................... sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary} Change-Id: Ia71692ecf74fd8921eeafabac9a4cb862da90e81 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70114 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/asus/p5qpl-am/devicetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/getac/p470/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/ibase/mb899/devicetree.cb M src/mainboard/intel/d945gclf/devicetree.cb M src/mainboard/intel/dg41wv/devicetree.cb M src/mainboard/kontron/986lcd-m/devicetree.cb M src/mainboard/lenovo/t60/mainboard.c M src/mainboard/lenovo/thinkcentre_a58/devicetree.cb M src/mainboard/lenovo/x60/mainboard.c M src/mainboard/roda/rk886ex/devicetree.cb M src/southbridge/intel/i82801gx/chip.h 21 files changed, 46 insertions(+), 32 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 358fcf4..833d658 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -55,8 +55,8 @@ register "gpe0_en" = "0x11000006" register "alt_gp_smi_en" = "0x1000" - register "ide_enable_primary" = "1" - register "ide_enable_secondary" = "1" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "true" register "c4onc3_enable" = "1" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index 5d10628..846a02b 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -38,7 +38,7 @@ # 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "2" - register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb index d0759e2..8115430 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb @@ -33,7 +33,7 @@ register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b" - register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "gpe0_en" = "0x440" register "gen1_dec" = "0x000c0291" # Superio HWM diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index 818ceaa..ef019d1 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -33,7 +33,7 @@ register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b" - register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 9f4142b..4237041 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -31,7 +31,7 @@ register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b" - register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index e0df76b..23268f2b 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -33,7 +33,7 @@ register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b" - register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "gpe0_en" = "0x440" register "gen1_dec" = "0x000c0291" # Superio HWM diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index ad9b961..a9cad93 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -38,8 +38,8 @@ register "gpe0_en" = "0" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb index 82b1c61..1044851 100644 --- a/src/mainboard/asus/p5qpl-am/devicetree.cb +++ b/src/mainboard/asus/p5qpl-am/devicetree.cb @@ -29,7 +29,7 @@ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set) - register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "gpe0_en" = "0x04000440" register "gen1_dec" = "0x00000295" # HWM diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index 578f13d..46bb422 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -31,8 +31,8 @@ register "gpe0_en" = "0x00000441" register "alt_gp_smi_en" = "0x0000" - register "ide_enable_primary" = "0x0" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "false" + register "ide_enable_secondary" = "false" register "sata_ports_implemented" = "0x3" register "gen1_dec" = "0x003c0a01" # Super I/O EC and GPIO diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 345bbd8..2514ad4 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -43,8 +43,8 @@ register "alt_gp_smi_en" = "0x0100" register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false" register "c3_latency" = "85" register "docking_supported" = "1" diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index 28af26f..673172d 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -61,8 +61,8 @@ register "gpe0_en" = "0" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index d216863..3a4ae45 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -32,8 +32,8 @@ register "pirqf_routing" = "0x0b" register "pirqg_routing" = "0x0b" register "pirqh_routing" = "0x0b" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x40" diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 1b59fcc..51ca420 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -34,8 +34,8 @@ # 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "1" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 0238e04..5c72c72 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -36,8 +36,8 @@ register "gpi13_routing" = "1" register "gpe0_en" = "0x20000601" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index 9e5c136..641ada5 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -50,7 +50,7 @@ register "gpi14_routing" = "2" register "gpi15_routing" = "2" - register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "gpe0_en" = "0x440" register "gen1_dec" = "0x00fc0a01" # HWM diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 90da56c..e58d8f3 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -35,8 +35,8 @@ register "gpi13_routing" = "1" register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x1" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "true" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 7ebe25e..5b38ec2 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -34,7 +34,7 @@ } else if (idedev && idedev->chip_info && h8_ultrabay_device_present()) { config = idedev->chip_info; - config->ide_enable_primary = 1; + config->ide_enable_primary = true; pmh7_ultrabay_power_enable(1); ec_write(0x0c, 0x84); } else { diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb index a4b9ac8..9a2c452 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb @@ -31,7 +31,7 @@ # 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "1" # ??vendor - register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "gpe0_en" = "0x440" register "gen1_dec" = "0x00fc0a01" diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 2eb0c38..238d949 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -37,7 +37,7 @@ idedev = pcidev_on_root(0x1f, 1); if (idedev && idedev->chip_info && dock_ultrabay_device_present()) { struct southbridge_intel_i82801gx_config *config = idedev->chip_info; - config->ide_enable_primary = 1; + config->ide_enable_primary = true; /* enable Ultrabay power */ outb(inb(0x1628) | 0x01, 0x1628); ec_write(0x0c, 0x84); diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 4023af80..eb0bdcd 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -46,8 +46,8 @@ register "p_cnt_throttling_supported" = "1" register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false" register "gen1_dec" = "0x001c02e1" # COM3, COM4 register "gen2_dec" = "0x00fc0601" # ?? diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 09a7126..ba8dd6f 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -55,8 +55,8 @@ uint16_t alt_gp_smi_en; /* IDE configuration */ - uint32_t ide_enable_primary; - uint32_t ide_enable_secondary; + bool ide_enable_primary; + bool ide_enable_secondary; enum sata_mode sata_mode; uint32_t sata_ports_implemented; -- To view, visit https://review.coreboot.org/c/coreboot/+/70114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia71692ecf74fd8921eeafabac9a4cb862da90e81 Gerrit-Change-Number: 70114 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: superio/nuvoton/nct5104d/chip.h: Use 'bool' when appropriate
by Elyes Haouas (Code Review) 02 Dec '22

02 Dec '22

Elyes Haouas has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/70255 ) Change subject: superio/nuvoton/nct5104d/chip.h: Use 'bool' when appropriate ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/70255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb321302bc82eb1b73bc1e732b82b9f726d2f363 Gerrit-Change-Number: 70255 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: acpi: Helper functions to add certain _DSD properties
by Kapil Porwal (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Lance Zhao, Tarun Tuli, Subrata Banik, Tim Wawrzynczak. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70063 ) Change subject: acpi: Helper functions to add certain _DSD properties ...................................................................... Patch Set 10: (1 comment) File src/acpi/device.c: https://review.coreboot.org/c/coreboot/+/70063/comment/ffa44738_e90fd7c9 PS9, Line 1236: > move into new line? […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/70063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5bb432dd4e8f320d2c0d7f378dc2d7b3a770b541 Gerrit-Change-Number: 70063 Gerrit-PatchSet: 10 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 14:39:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Drop casts around `soc_read_pmc_base()`
by Subrata Banik (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Tarun Tuli, Dinesh Gehlot, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70272 ) Change subject: soc/intel/meteorlake: Drop casts around `soc_read_pmc_base()` ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/70272/comment/66f33c42_399bc819 PS3, Line 9: The `soc_read_pmc_base()` function returns an `uintptr_t`, which is then : casted to a pointer type for use with `read32()` and/or `write32()`. But : since commit b324df6a540d154cc9267c0398654f9142aae052 (arch/x86: Provide : readXp/writeXp helpers in arch/mmio.h), the `read32p()` and `write32p()` : functions live in `arch/mmio.h`. These functions use the `uintptr_t type : for the address parameter instead of a pointer type, and using them with : the `soc_read_pmc_base()` function allows dropping the casts to pointer. : please use < 72 char per line -- To view, visit https://review.coreboot.org/c/coreboot/+/70272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I914190f2d2d0507c84b19340159990f9b62ce101 Gerrit-Change-Number: 70272 Gerrit-PatchSet: 3 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 14:39:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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