coreboot-gerrit December 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: mb/google/rex: Add MPTS method for WWAN over PCIe
by build bot (Jenkins) (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70229 ) Change subject: mb/google/rex: Add MPTS method for WWAN over PCIe ...................................................................... Patch Set 2: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165077): https://review.coreboot.org/c/coreboot/+/70229/comment/ab3ecc13_e4e50b0f PS2, Line 6: Possible long commit subject (prefer a maximum 65 characters) -- To view, visit https://review.coreboot.org/c/coreboot/+/70229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27ade63cfe0586aee9f03ba816b2590f14dcb610 Gerrit-Change-Number: 70229 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 12:34:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex: Implement S0ix hooks aka `MS0X` method
by Subrata Banik (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Utkarsh H Patel, Kapil Porwal, Ivy Jian, Sridhar Siricilla, Eric Lai. Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, Ivy Jian, Utkarsh H Patel, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70196 to look at the new patch set (#8). Change subject: mb/google/rex: Implement S0ix hooks aka `MS0X` method ...................................................................... mb/google/rex: Implement S0ix hooks aka `MS0X` method This patch ensures to be able to drive SYS_SLP_S0IX_L `low` based on the state of the system while `SLP_S0_L` signal is `low` (while the system is in S0ix). Implemented runtime ASL method (MS0X) being called by PEPD device _DSM to configure `SLP_S0_GATE (GPP_H14)` PIN at S0ix entry/exit. Scope (\_SB) { Method (MS0X, 1, Serialized) { If ((Arg0 == One)) { \_SB.PCI0.CTXS (0x75) } Else { \_SB.PCI0.STXS (0x75) } } BUG=b:256807255 TEST=Able to see SYS_SLP_S0IX_L goes low in S0ix. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/mainboard.c M src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h 4 files changed, 84 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/70196/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/70196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce Gerrit-Change-Number: 70196 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-CC: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/rex: Add MPTS method for WWAN over PCIe
by Subrata Banik (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70229 to look at the new patch set (#2). Change subject: mb/google/rex: Add MPTS method for WWAN over PCIe ...................................................................... mb/google/rex: Add MPTS method for WWAN over PCIe This patch generates the following for the mainboard: Scope (\_SB) { Method (MPTS, 1, Serialized) { Local0 = \_SB.PCI0.RP06.RTD3._STA () If ((Local0 == One)) { \_SB.PCI0.RP06.PXSX.DPTS (Arg0) } } } Change-Id: I27ade63cfe0586aee9f03ba816b2590f14dcb610 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/mainboard.c M src/mainboard/google/rex/variants/rex0/overridetree.cb 2 files changed, 63 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/70229/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27ade63cfe0586aee9f03ba816b2590f14dcb610 Gerrit-Change-Number: 70229 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/var/kinox: Add ACPI DmaProperty for WLAN device
by Kapil Porwal (Code Review) 02 Dec '22

02 Dec '22

Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70266 ) Change subject: mb/google/brya/var/kinox: Add ACPI DmaProperty for WLAN device ...................................................................... mb/google/brya/var/kinox: Add ACPI DmaProperty for WLAN device DmaProperty must only be present on endpoint devices. BUG=b:259716145 TEST=TBD Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: Ic5be85c3d13250646867f8c8f5950796ec339551 --- M src/mainboard/google/brya/variants/kinox/overridetree.cb 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/70266/1 diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index f79d7ea..9bfda79 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -235,13 +235,13 @@ }" chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" + register "add_acpi_dma_property" = "true" device pci 00.0 on end end chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" register "srcclk_pin" = "2" - register "add_acpi_dma_property" = "true" device generic 0 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/70266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5be85c3d13250646867f8c8f5950796ec339551 Gerrit-Change-Number: 70266 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Read ioapic configuration from hardware
by Kyösti Mälkki (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70265 ) Change subject: soc/intel/xeon_sp: Read ioapic configuration from hardware ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/70265/comment/8625d46b_1c098b35 PS3, Line 9: This more robust than hardcoding whathever FSP has set up and is a lot this is more ... whatever -- To view, visit https://review.coreboot.org/c/coreboot/+/70265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6423ddc139d742879d791b054ea082768749c0a7 Gerrit-Change-Number: 70265 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 12:07:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Read ioapic configuration from hardware
by Kyösti Mälkki (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70265 ) Change subject: soc/intel/xeon_sp: Read ioapic configuration from hardware ...................................................................... Patch Set 1: (2 comments) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/70265/comment/595c3da6_3147f060 PS1, Line 96: current += acpi_create_madt_ioapic_from_hw((void *)current, ioapic_table[i]); Currently GSIs are assigned in the order these calls are made. There are some assumptions that GSIs 0-15 are connected to legacy IRQs, so the first IOAPIC on the table needs to be the one delivering superio SERIRQs, i8254(?) timer etc. Could already be the case, I did not dig into soc_get_ioapic_info() and the HOBs to say. File src/soc/intel/xeon_sp/acpi.c: https://review.coreboot.org/c/coreboot/+/70265/comment/76bac003_70bb6082 PS1, Line 99: xeonsp_ioapic_bases[index++] = hob->PlatformData.IIO_resource[0].StackRes[0].IoApicBase; With XEON_SP_HAVE_IIO_IOAPIC=y, does this get added again at index 1, and emit associated MADT entries twice? I have no clue what is_iio_stack_res() checks. -- To view, visit https://review.coreboot.org/c/coreboot/+/70265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6423ddc139d742879d791b054ea082768749c0a7 Gerrit-Change-Number: 70265 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 12:04:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Read ioapic configuration from hardware
by Arthur Heymans (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Kyösti Mälkki, Tim Chu. Hello Jonathan Zhang, Johnny Lin, Christian Walter, Kyösti Mälkki, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70265 to look at the new patch set (#3). Change subject: soc/intel/xeon_sp: Read ioapic configuration from hardware ...................................................................... soc/intel/xeon_sp: Read ioapic configuration from hardware This more robust than hardcoding whathever FSP has set up and is a lot less code. Change-Id: I6423ddc139d742879d791b054ea082768749c0a7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Kconfig 5 files changed, 33 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/70265/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/70265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6423ddc139d742879d791b054ea082768749c0a7 Gerrit-Change-Number: 70265 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Read ioapic configuration from hardware
by Arthur Heymans (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Kyösti Mälkki, Tim Chu. Hello Jonathan Zhang, Johnny Lin, Christian Walter, Kyösti Mälkki, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70265 to look at the new patch set (#2). Change subject: soc/intel/xeon_sp: Read ioapic configuration from hardware ...................................................................... soc/intel/xeon_sp: Read ioapic configuration from hardware This more robust than hardcoding whathever FSP has set up and is a lot less code. Change-Id: I6423ddc139d742879d791b054ea082768749c0a7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Kconfig 5 files changed, 33 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/70265/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6423ddc139d742879d791b054ea082768749c0a7 Gerrit-Change-Number: 70265 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Read ioapic configuration from hardware
by build bot (Jenkins) (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Kyösti Mälkki, Tim Chu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70265 ) Change subject: soc/intel/xeon_sp: Read ioapic configuration from hardware ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/include/intelblocks/acpi.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165069): https://review.coreboot.org/c/coreboot/+/70265/comment/07d92cf2_514a69ae PS1, Line 98: * Return the number of table entires and takes a pointer to an array of ioapic bases. 'entires' may be misspelled - perhaps 'entries'? -- To view, visit https://review.coreboot.org/c/coreboot/+/70265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6423ddc139d742879d791b054ea082768749c0a7 Gerrit-Change-Number: 70265 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 11:45:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Read ioapic configuration from hardware
by Arthur Heymans (Code Review) 02 Dec '22

02 Dec '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70265 ) Change subject: soc/intel/xeon_sp: Read ioapic configuration from hardware ...................................................................... soc/intel/xeon_sp: Read ioapic configuration from hardware This more robust than hardcoding whathever FSP has set up and is a lot less code. Change-Id: I6423ddc139d742879d791b054ea082768749c0a7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Kconfig 5 files changed, 33 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/70265/1 diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 860c868..050facf 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -73,33 +73,27 @@ return current; } -__weak const struct madt_ioapic_info *soc_get_ioapic_info(size_t *entries) +static const uintptr_t default_ioapic_bases[] = { IO_APIC_ADDR }; + +__weak size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[]) { - *entries = 0; - return NULL; + *ioapic_bases = default_ioapic_bases; + return ARRAY_SIZE(default_ioapic_bases); } unsigned long acpi_fill_madt(unsigned long current) { - const struct madt_ioapic_info *ioapic_table; + const uintptr_t *ioapic_table; size_t ioapic_entries; /* Local APICs */ current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ - ioapic_table = soc_get_ioapic_info(&ioapic_entries); - if (ioapic_entries) { - for (int i = 0; i < ioapic_entries; i++) { - current += acpi_create_madt_ioapic( - (void *)current, - ioapic_table[i].id, - ioapic_table[i].addr, - ioapic_table[i].gsi_base); - } - } else { + ioapic_entries = soc_get_ioapic_info(&ioapic_table); + for (int i = 0; i < ioapic_entries; i++) { /* Default SOC IOAPIC entry */ - current += acpi_create_madt_ioapic_from_hw((void *)current, IO_APIC_ADDR); + current += acpi_create_madt_ioapic_from_hw((void *)current, ioapic_table[i]); } return acpi_madt_irq_overrides(current); diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index d05ddf3..fb4b096 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -93,17 +93,11 @@ */ int common_calculate_power_ratio(int tdp, int p1_ratio, int ratio); -struct madt_ioapic_info { - u8 id; - u32 addr; - u32 gsi_base; -}; /* - * Returns a table of MADT ioapic_info entries and the number of entries - * If the SOC doesn't implement this hook a default ioapic setting is used. + * Return the number of table entires and takes a pointer to an array of ioapic bases. */ -const struct madt_ioapic_info *soc_get_ioapic_info(size_t *entries); +size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[]); struct soc_pmc_lpm { unsigned int num_substates; diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 2abe433..81f50a2 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -87,41 +87,19 @@ return map; } -static void print_madt_ioapic(int socket, int stack, - int ioapic_id, uint32_t ioapic_base, int gsi_base) -{ - printk(BIOS_DEBUG, "Adding MADT IOAPIC for socket: %d, stack: %d, ioapic_id: 0x%x, " - "ioapic_base: 0x%x, gsi_base: 0x%x\n", - socket, stack, ioapic_id, ioapic_base, gsi_base); -} +static uintptr_t xeonsp_ioapic_bases[CONFIG(XEON_SP_HAVE_IIO_IOAPIC) * 8 + 1]; -const struct madt_ioapic_info *soc_get_ioapic_info(size_t *entries) +size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[]) { - int cur_index; - int gsi_per_iiostack = 0; - + int index = 0; const IIO_UDS *hob = get_iio_uds(); - uint8_t gsi_bases[CONFIG(XEON_SP_HAVE_IIO_IOAPIC) * 8 + 1] = { 0 }; + *ioapic_bases = xeonsp_ioapic_bases; - for (uint8_t i = 1; i < sizeof(gsi_bases); i++) { - int gsi_base = CONFIG_XEON_SP_PCH_IOAPIC_GSI_BASES; - gsi_bases[i] = gsi_base + (i * gsi_per_iiostack); - } - - static struct madt_ioapic_info madt_tbl[ARRAY_SIZE(gsi_bases)]; - - cur_index = 0; - madt_tbl[cur_index].id = PCH_IOAPIC_ID; - madt_tbl[cur_index].addr = hob->PlatformData.IIO_resource[0].StackRes[0].IoApicBase; - madt_tbl[cur_index].gsi_base = gsi_bases[cur_index]; - print_madt_ioapic(0, 0, madt_tbl[cur_index].id, - madt_tbl[cur_index].addr, madt_tbl[cur_index].gsi_base); - ++cur_index; + xeonsp_ioapic_bases[index++] = hob->PlatformData.IIO_resource[0].StackRes[0].IoApicBase; if (!CONFIG(XEON_SP_HAVE_IIO_IOAPIC)) { - *entries = cur_index; - return madt_tbl; + return index; } for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { @@ -130,25 +108,10 @@ &hob->PlatformData.IIO_resource[socket].StackRes[stack]; if (!is_iio_stack_res(ri)) continue; - assert(cur_index < ARRAY_SIZE(gsi_bases)); - madt_tbl[cur_index].id = soc_get_iio_ioapicid(socket, stack); - madt_tbl[cur_index].gsi_base = gsi_bases[cur_index]; - madt_tbl[cur_index].addr = ri->IoApicBase; - - /* - * Stack 0 has non-PCH IOAPIC and PCH IOAPIC. - * The IIO IOAPIC is placed at 0x1000 from the reported base. - */ - if (stack == 0 && socket == 0) - madt_tbl[cur_index].addr += 0x1000; - - print_madt_ioapic(socket, stack, madt_tbl[cur_index].id, - madt_tbl[cur_index].addr, - madt_tbl[cur_index].gsi_base); - ++cur_index; + assert(index < ARRAY_SIZE(xeonsp_ioapic_bases)); + xeonsp_ioapic_bases[index++] = ri->IoApicBase; } } - *entries = cur_index; - return madt_tbl; + return index; } diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 52de09a..aa344ce 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -112,10 +112,6 @@ bool default y -config XEON_SP_PCH_IOAPIC_GSI_BASES - hex - default 0x78 - if INTEL_TXT config INTEL_TXT_SINIT_SIZE diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index c325512..18e5f2f5 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -63,8 +63,4 @@ bool default y -config XEON_SP_PCH_IOAPIC_GSI_BASES - hex - default 0x18 - endif -- To view, visit https://review.coreboot.org/c/coreboot/+/70265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6423ddc139d742879d791b054ea082768749c0a7 Gerrit-Change-Number: 70265 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit December 2022