coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/skyrim: Use detect vs probed flag for touchscreens
by Felix Held (Code Review) 02 Nov '22

02 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67779 ) Change subject: mb/google/skyrim: Use detect vs probed flag for touchscreens ...................................................................... mb/google/skyrim: Use detect vs probed flag for touchscreens Now that coreboot performs the necessary power sequencing, switch from using the 'probed' flag to 'detect' for all I2C touchscreens. This alleviates ChromeOS from having to probe to see which touchscreen model is actually present, prevents breaking ACPI spec by generating device entries with status 'enabled and present' which aren't actually present, and improves compatibility with upstream Linux and Windows. BUG=b:121309055 TEST=build/boot ChromeOS and Linux on skyrim, ensure touchscreen is functional, and ACPI device entry generated for correct touchscreen model. Change-Id: Id9e3089decf0f94a1358929684ce248e52cbe41f Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67779 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> --- M src/mainboard/google/skyrim/variants/frostflow/overridetree.cb M src/mainboard/google/skyrim/variants/skyrim/overridetree.cb M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb 3 files changed, 32 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Frank Wu: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb index 1b49a10..a3858c8 100644 --- a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb @@ -49,7 +49,7 @@ register "generic.hid" = ""ELAN9008"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_29)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" register "generic.enable_delay_ms" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)" diff --git a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb index c36a8d4..65b4413 100644 --- a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb @@ -120,7 +120,7 @@ register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_29)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" register "generic.enable_delay_ms" = "10" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)" @@ -136,7 +136,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "probed" = "1" + register "detect" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_29)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" register "enable_delay_ms" = "1" diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index ab0bda2..78a8091 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -89,7 +89,7 @@ register "generic.hid" = ""ELAN900C"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_29)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" register "generic.enable_delay_ms" = "10" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)" @@ -105,7 +105,7 @@ chip drivers/i2c/generic register "hid" = ""MELF0410"" register "desc" = ""Melfas Touchscreen"" - register "probed" = "1" + register "detect" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_29)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" register "enable_delay_ms" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/67779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9e3089decf0f94a1358929684ce248e52cbe41f Gerrit-Change-Number: 67779 Gerrit-PatchSet: 7 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: util/cbfstool: fix memory leak in compress.c
by Felix Held (Code Review) 02 Nov '22

02 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69021 ) Change subject: util/cbfstool: fix memory leak in compress.c ...................................................................... util/cbfstool: fix memory leak in compress.c free the memory allocated in lz4_compress function before returning from it. Reported-by: Coverity (CID:1469433) Signed-off-by: Solomon Alan-Dei <alandei.solomon(a)gmail.com> Change-Id: I8698090d519964348e51fc3b6f2023d06d81fcd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69021 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M util/cbfstool/compress.c 1 file changed, 22 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/util/cbfstool/compress.c b/util/cbfstool/compress.c index 37fac22..96df1a7 100644 --- a/util/cbfstool/compress.c +++ b/util/cbfstool/compress.c @@ -23,9 +23,12 @@ if (!bounce) return -1; *out_len = LZ4F_compressFrame(bounce, worst_size, in, in_len, &prefs); - if (LZ4F_isError(*out_len) || *out_len >= in_len) + if (LZ4F_isError(*out_len) || *out_len >= in_len) { + free(bounce); return -1; + } memcpy(out, bounce, *out_len); + free(bounce); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/69021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8698090d519964348e51fc3b6f2023d06d81fcd5 Gerrit-Change-Number: 69021 Gerrit-PatchSet: 3 Gerrit-Owner: Solomon Alan-Dei <alandei.solomon(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/hatch/var/kohaku: ensure FPMCU is power cycled on reset
by Felix Held (Code Review) 02 Nov '22

02 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68819 ) ( 23 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/hatch/var/kohaku: ensure FPMCU is power cycled on reset ...................................................................... mb/google/hatch/var/kohaku: ensure FPMCU is power cycled on reset Leakage from the SPI CS line onto the FPMCU VDD rail was preventing the FPMCU from fully shutting down on AP reset. Instead of simply turning off the power rail, now ensure the CS line is not driven high until late in coreboot. This ensures it is completely off for the requisite minimum of 200ms (now measured at approx 1100ms). BUG=b:245953688 TEST=Confirmed FPMCU is still functional on Kohaku. Confirmed FpRebootPowerCycle unit test now passes BRANCH=Hatch Signed-off-by: Tarun Tuli <taruntuli(a)google.com> Change-Id: I1e7e32f61c3ac1b3154d42821cc1dd4c5d3de303 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68819 Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/hatch/variants/kohaku/gpio.c M src/mainboard/google/hatch/variants/kohaku/ramstage.c 2 files changed, 45 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index aa86932..ef80800 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -8,8 +8,6 @@ static const struct pad_config gpio_table[] = { /* A8 : PEN_GARAGE_DET_L (wake) */ PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), - /* A11 : PCH_SPI_FPMCU_CS_L */ - PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), /* A12 : FPMCU_RST_ODL */ PAD_CFG_GPO(GPP_A12, 0, DEEP), /* A16 : EMR_GARAGE_DET (notification) */ @@ -130,6 +128,23 @@ return early_gpio_table; } +/* Set the FPMCU SPI CS line very late to workaround + * leakage of this line onto the VDD of the MCU. + */ +static const struct pad_config finalize_gpio_table[] = { + /* A11 : PCH_SPI_FPMCU_CS_L */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2), +}; + +/* + * GPIOs configured during the mainboard finalize + */ +const struct pad_config *variant_finalize_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(finalize_gpio_table); + return finalize_gpio_table; +} + /* * Default GPIO settings before entering non-S5 sleep states. * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. diff --git a/src/mainboard/google/hatch/variants/kohaku/ramstage.c b/src/mainboard/google/hatch/variants/kohaku/ramstage.c index 176527b..e861cfb 100644 --- a/src/mainboard/google/hatch/variants/kohaku/ramstage.c +++ b/src/mainboard/google/hatch/variants/kohaku/ramstage.c @@ -5,7 +5,7 @@ #include <baseboard/variants.h> #include <soc/gpio.h> -void variant_ramstage_init(void) +void variant_final(void) { /* * Enable power to FPMCU, wait for power rail to stabilize, -- To view, visit https://review.coreboot.org/c/coreboot/+/68819 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e7e32f61c3ac1b3154d42821cc1dd4c5d3de303 Gerrit-Change-Number: 68819 Gerrit-PatchSet: 25 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in blobs[master]: mb/ocp/deltalake: Add descriptor + ME ignition binary
by Jonathan Zhang (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Nathaniel L Desimone, Isaac W Oram. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/57477 ) Change subject: mb/ocp/deltalake: Add descriptor + ME ignition binary ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > How should we proceed? I think we could proceed with merging this patch to enable coreboot focused developers to work on DeltaLake. To get latest and greatest end-to-end solution (FSP/coreboot/LinuxBoot), the OCP OSF repo (https://github.com/opencomputeproject/OpenSystemFirmware/tree/master/Wiwynn…) should be the way to go, as it gets and builds everything. -- To view, visit https://review.coreboot.org/c/blobs/+/57477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I6f0a404edebf982ee56f5fa30fb0880bdf138006 Gerrit-Change-Number: 57477 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Isaac W Oram <isaac.w.oram(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Attention: Isaac W Oram <isaac.w.oram(a)intel.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 21:37:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/hatch: Add variant finalize support for hatch devices
by Felix Held (Code Review) 02 Nov '22

02 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68821 ) Change subject: mb/google/hatch: Add variant finalize support for hatch devices ...................................................................... mb/google/hatch: Add variant finalize support for hatch devices Provide a variant_finalize() method and call to be invoked from mainboard_ops.final BUG=b:245953688 TEST=Hatch and variants build BRANCH=Hatch Signed-off-by: Tarun Tuli <taruntuli(a)google.com> Change-Id: I9253ed4be1b08d0c7f65526c9b26dbcd00ffccc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68821 Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/hatch/ramstage.c M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h 3 files changed, 48 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c index ff466a3..6cce734 100644 --- a/src/mainboard/google/hatch/ramstage.c +++ b/src/mainboard/google/hatch/ramstage.c @@ -55,7 +55,22 @@ variant_ramstage_init(); } +void __weak variant_final(void) +{ +} + +static void mainboard_final(void *chip_info) +{ + const struct pad_config *variant_finalize; + size_t variant_gpios; + variant_finalize = variant_finalize_gpio_table(&variant_gpios); + gpio_configure_pads(variant_finalize, variant_gpios); + + variant_final(); +} + struct chip_operations mainboard_ops = { .init = mainboard_chip_init, .enable_dev = mainboard_enable, + .final = mainboard_final, }; diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index eab831a..c65375e 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -433,3 +433,10 @@ *num = 0; return NULL; } + +/* Weak implementation of finalize gpio */ +const struct pad_config *__weak variant_finalize_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index 125f738..62479eb 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -27,12 +27,18 @@ /* Return GPIO pads that need to be configured before ramstage */ const struct pad_config *variant_early_gpio_table(size_t *num); +/* Return GPIO pads that need to be configured after ramstage */ +const struct pad_config *variant_finalize_gpio_table(size_t *num); + /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); /* Perform variant specific initialization early on in ramstage. */ void variant_ramstage_init(void); +/* Perform variant specific mainboard finalization */ +void variant_final(void); + /* Perform variant specific mainboard initialization */ void variant_mainboard_enable(struct device *dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/68821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9253ed4be1b08d0c7f65526c9b26dbcd00ffccc7 Gerrit-Change-Number: 68821 Gerrit-PatchSet: 15 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: util/cbmem: Update formatting for cbmem -l command
by Julius Werner (Code Review) 02 Nov '22

02 Nov '22

Attention is currently required from: Martin L Roth, Jon Murphy. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68644 ) Change subject: util/cbmem: Update formatting for cbmem -l command ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d91d21c6ad418d9fee9880550fb6cb9e41e93f0 Gerrit-Change-Number: 68644 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Comment-Date: Wed, 02 Nov 2022 21:37:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/lisbon: Enable SaGv
by Felix Held (Code Review) 02 Nov '22

02 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69013 ) Change subject: mb/google/brya/var/lisbon: Enable SaGv ...................................................................... mb/google/brya/var/lisbon: Enable SaGv Enable SaGv support for lisbon BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot pass RMT verification Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Change-Id: Ic7d3203bfe06973b023a38d1aa3d69cce5c3a60c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69013 Reviewed-by: Ricky Chang <rickytlchang(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/lisbon/overridetree.cb 1 file changed, 23 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Ricky Chang: Looks good to me, but someone else must approve Tarun Tuli: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/lisbon/overridetree.cb b/src/mainboard/google/brya/variants/lisbon/overridetree.cb index 67b0d9b..f952c3e 100644 --- a/src/mainboard/google/brya/variants/lisbon/overridetree.cb +++ b/src/mainboard/google/brya/variants/lisbon/overridetree.cb @@ -6,6 +6,8 @@ end chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/69013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7d3203bfe06973b023a38d1aa3d69cce5c3a60c Gerrit-Change-Number: 69013 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/var/lisbon: Include driver for GL9763E for eMMC boot disk
by Felix Held (Code Review) 02 Nov '22

02 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68888 ) Change subject: mb/google/brya/var/lisbon: Include driver for GL9763E for eMMC boot disk ...................................................................... mb/google/brya/var/lisbon: Include driver for GL9763E for eMMC boot disk Support GL9763E as a eMMC boot disk BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Change-Id: Ibe579a913225b5241412bbb1b8ea995a5102a3bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/68888 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ricky Chang <rickytlchang(a)google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 20 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Ricky Chang: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 7875986..647ae30 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -274,6 +274,7 @@ bool "-> Lisbon" select BOARD_GOOGLE_BASEBOARD_BRASK select DRIVERS_GENESYSLOGIC_GL9750 + select DRIVERS_GENESYSLOGIC_GL9763E config BOARD_GOOGLE_ZYDRON bool "-> Zydron" -- To view, visit https://review.coreboot.org/c/coreboot/+/68888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe579a913225b5241412bbb1b8ea995a5102a3bb Gerrit-Change-Number: 68888 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya: enable PCIe RP12 for lisbon eMMC support
by Felix Held (Code Review) 02 Nov '22

02 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68167 ) Change subject: mb/google/brya: enable PCIe RP12 for lisbon eMMC support ...................................................................... mb/google/brya: enable PCIe RP12 for lisbon eMMC support BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Change-Id: Ief8ca9cf845156ac761556d0eb49edb65894c001 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68167 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ricky Chang <rickytlchang(a)google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/lisbon/overridetree.cb 1 file changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Ricky Chang: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/lisbon/overridetree.cb b/src/mainboard/google/brya/variants/lisbon/overridetree.cb index a2a4043..67b0d9b 100644 --- a/src/mainboard/google/brya/variants/lisbon/overridetree.cb +++ b/src/mainboard/google/brya/variants/lisbon/overridetree.cb @@ -200,6 +200,14 @@ device generic 0 on end end end #PCIE8 SD card + device ref pcie_rp12 on + # Enable PCIE eMMC bridge 12 using clk 4 + register "pch_pcie_rp[PCH_RP(12)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER, + }" + end #PCIE12 EMMC device ref gspi1 off end device ref pch_espi on chip ec/google/chromeec -- To view, visit https://review.coreboot.org/c/coreboot/+/68167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief8ca9cf845156ac761556d0eb49edb65894c001 Gerrit-Change-Number: 68167 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/corsola: Add new board 'voltorb'
by Felix Held (Code Review) 02 Nov '22

02 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69095 ) Change subject: mb/google/corsola: Add new board 'voltorb' ...................................................................... mb/google/corsola: Add new board 'voltorb' Add a new kingler follower 'voltorb'. BUG=b:256737049 TEST=emerge-corsola coreboot Signed-off-by: Mars Chen <chenxiangrui(a)huaqin.corp-partner.google.com> Change-Id: Ic7175c38fcde76ab0360f62da161994ba2ee6a69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69095 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/Kconfig.name 2 files changed, 23 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index 65d26ef..e53ae82 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -53,6 +53,7 @@ default "Steelix" if BOARD_GOOGLE_STEELIX default "Tentacruel" if BOARD_GOOGLE_TENTACRUEL default "Magikarp" if BOARD_GOOGLE_MAGIKARP + default "Voltorb" if BOARD_GOOGLE_VOLTORB config BOOT_DEVICE_SPI_FLASH_BUS int diff --git a/src/mainboard/google/corsola/Kconfig.name b/src/mainboard/google/corsola/Kconfig.name index 176252f..902ed1d 100644 --- a/src/mainboard/google/corsola/Kconfig.name +++ b/src/mainboard/google/corsola/Kconfig.name @@ -8,6 +8,10 @@ bool "-> Steelix" select BOARD_GOOGLE_KINGLER_COMMON +config BOARD_GOOGLE_VOLTORB + bool "-> Voltorb" + select BOARD_GOOGLE_KINGLER_COMMON + comment "Krabby" config BOARD_GOOGLE_KRABBY -- To view, visit https://review.coreboot.org/c/coreboot/+/69095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7175c38fcde76ab0360f62da161994ba2ee6a69 Gerrit-Change-Number: 69095 Gerrit-PatchSet: 3 Gerrit-Owner: Mars Chen <chenxiangrui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Knox Chiou <knoxchiou(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2022