coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: Documentation/mb/starlabs: De-deplicate the building instructions
by Angel Pons (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Sean Rhodes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68585 ) Change subject: Documentation/mb/starlabs: De-deplicate the building instructions ...................................................................... Patch Set 7: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68585/comment/1fb5077e_a6a4ce18 PS7, Line 7: e typo: d*u*plicate File Documentation/mainboard/starlabs/labtop_cml.md: https://review.coreboot.org/c/coreboot/+/68585/comment/cfc41d1d_33dc218f PS7, Line 44: [here](../common/building.md) There was something against using `here` for links or something like that due to accessibility reasons, but can't remember the details... How about: > Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_cml` as config file. -- To view, visit https://review.coreboot.org/c/coreboot/+/68585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20301b3041a62eb416ed61a84544ec4e5cc66c1e Gerrit-Change-Number: 68585 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 04 Nov 2022 19:32:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: arch/arm: Fix assembling files with clang
by Arthur Heymans (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63058 ) Change subject: arch/arm: Fix assembling files with clang ...................................................................... Patch Set 16: Code-Review-2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia320dc2c460c99d934b8f17dee7748a9def4e750 Gerrit-Change-Number: 63058 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 19:30:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: arch/riscv: Use updated name for sbadaddr
by Arthur Heymans (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans, Philipp Hug, Angel Pons, ron minnich. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63073 ) Change subject: arch/riscv: Use updated name for sbadaddr ...................................................................... Patch Set 16: (1 comment) Patchset: PS16: wip. I probably should test this first. -- To view, visit https://review.coreboot.org/c/coreboot/+/63073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic86e5070b084bf1ce03fe30d46abbbd0c88b9532 Gerrit-Change-Number: 63073 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 19:30:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/sifive/ux00ddr.h: Remove set but unused variables
by Arthur Heymans (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans, Philipp Hug, ron minnich, Elyes Haouas. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63074 ) Change subject: soc/sifive/ux00ddr.h: Remove set but unused variables ...................................................................... Patch Set 17: (1 comment) Patchset: PS17: wip. I probably should test this first. -- To view, visit https://review.coreboot.org/c/coreboot/+/63074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I442a42e297f2968dd2c824a93a9a1e2bc74ea2f4 Gerrit-Change-Number: 63074 Gerrit-PatchSet: 17 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 04 Nov 2022 19:30:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: arch/riscv/mcall.h: Fix building with clang
by Arthur Heymans (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans, Philipp Hug, ron minnich. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63072 ) Change subject: arch/riscv/mcall.h: Fix building with clang ...................................................................... Patch Set 16: Code-Review-2 (1 comment) Patchset: PS16: wip. I probably should test this first. -- To view, visit https://review.coreboot.org/c/coreboot/+/63072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If24b2766404b892a006926f0cd45771ceebf1275 Gerrit-Change-Number: 63072 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 19:30:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/x86/smm/module_loader: Fix ASEG loading
by Arthur Heymans (Code Review) 04 Nov '22

04 Nov '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69233 ) Change subject: cpu/x86/smm/module_loader: Fix ASEG loading ...................................................................... cpu/x86/smm/module_loader: Fix ASEG loading This code was never tested with SSE enabled. Now qemu enables it and FX_SAVE encroaches on the save states. Without SSE enabled the handler just happened to be aligned downwards enough to have the save states fit. With SSE enabled that's not the case. The proper fix is to give the code setting up stubs the right base address, which is the same as for the TSEG codepath. Change-Id: I45355efb274c6ddd09a6fb57743d2f6a5b53d209 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 23 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/69233/1 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 71d49ab..6f334a2 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -409,6 +409,11 @@ int smm_load_module(const uintptr_t smram_base, const size_t smram_size, struct smm_loader_params *params) { + if (CONFIG(SMM_ASEG) && (smram_base != SMM_BASE || smram_size != SMM_CODE_SEGMENT_SIZE)) { + printk(BIOS_ERR, "SMM base & size are 0x%lx, 0x%zx, but must be 0x%x, 0x%x\n", + smram_base, smram_size, SMM_BASE, SMM_CODE_SEGMENT_SIZE); + return -1; + } /* * Place in .bss to reduce stack usage. * TODO: once CPU_INFO_V2 is used everywhere, use smaller stack for APs and move @@ -457,18 +462,7 @@ if (append_and_check_region(smram, handler, region_list, "HANDLER")) return -1; - uintptr_t stub_segment_base; - - if (CONFIG(SMM_TSEG)) { - stub_segment_base = handler_base - SMM_CODE_SEGMENT_SIZE; - } else if (CONFIG(SMM_ASEG)) { - stub_segment_base = smram_base; - if (smram_base != SMM_BASE || smram_size != SMM_CODE_SEGMENT_SIZE) { - printk(BIOS_ERR, "SMM base & size are 0x%lx, 0x%zx, but must be 0x%x, 0x%x\n", - smram_base, smram_size, SMM_BASE, SMM_CODE_SEGMENT_SIZE); - return -1; - } - } + uintptr_t stub_segment_base = handler_base - SMM_CODE_SEGMENT_SIZE; if (!smm_create_map(stub_segment_base, params->num_concurrent_save_states, params)) { printk(BIOS_ERR, "%s: Error creating CPU map\n", __func__); -- To view, visit https://review.coreboot.org/c/coreboot/+/69233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45355efb274c6ddd09a6fb57743d2f6a5b53d209 Gerrit-Change-Number: 69233 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: util/xcompile: Fix building for 64bit
by Arthur Heymans (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Martin L Roth. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69232 ) Change subject: util/xcompile: Fix building for 64bit ...................................................................... util/xcompile: Fix building for 64bit TESTED: This also boots on qemu q35 Change-Id: I7f99ebea18d5c09fdc7ced5c793d57d6fedd2e47 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/xcompile/xcompile 1 file changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/69232/1 diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index e35904f..e6d3123 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -235,6 +235,13 @@ GCC_ADAFLAGS_${TARCH}:=${FLAGS_GCC} GCC_COMPILER_RT_${TARCH}:=${CC_RT_GCC} GCC_COMPILER_RT_FLAGS_${TARCH}:=${CC_RT_EXTRA_GCC} +EOF +if [ "${TARCH}" = "x86_64" ]; then +cat <<EOF + GCC_CFLAGS_${TARCH} += -malign-data=abi +EOF +fi +cat <<EOF # Clang CLANG_CC_${TARCH}:=${CLANG} @@ -270,7 +277,7 @@ # to use i586 instead. if [ "${TARCH}" = "x86_64" ]; then cat <<EOF - CFLAGS_${TARCH} += -march=nocona -malign-data=abi + CFLAGS_${TARCH} += -march=nocona EOF fi @@ -459,7 +466,7 @@ # but that's more of a clang limitation. Let's be optimistic # that this will change in the future. CLANG="${clang_prefix}clang" - CFLAGS_CLANG="-target ${clang_arch}-${TABI} $CFLAGS_CLANG -ccc-gcc-name ${GCC}" + CFLAGS_CLANG="-target ${clang_arch}-${TABI} $CFLAGS_CLANG" fi } -- To view, visit https://review.coreboot.org/c/coreboot/+/69232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f99ebea18d5c09fdc7ced5c793d57d6fedd2e47 Gerrit-Change-Number: 69232 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: arch/x86/memmove.c: Add temporary fix for 64bit memmove
by Arthur Heymans (Code Review) 04 Nov '22

04 Nov '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69231 ) Change subject: arch/x86/memmove.c: Add temporary fix for 64bit memmove ...................................................................... arch/x86/memmove.c: Add temporary fix for 64bit memmove Change-Id: Ib43ec19df97194d6b1c18bfacb5fe8211ba0ffe5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/memmove.c 1 file changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/69231/1 diff --git a/src/arch/x86/memmove.c b/src/arch/x86/memmove.c index 3ec50b2..b05f03b 100644 --- a/src/arch/x86/memmove.c +++ b/src/arch/x86/memmove.c @@ -190,9 +190,11 @@ "11:" : "=&c" (d0), "=&S" (d1), "=&D" (d2), "=r" (d3), "=r" (d4), "=r"(d5) - : "0" (n), - "1" (src), - "2" (dest) + /* TODO: port proper memmove from Linux for 64bit. + For now it is ok as all coreboot core remains below 4G */ + : "0" ((uint32_t)(uintptr_t)n), + "1" ((uint32_t)(uintptr_t)src), + "2" ((uint32_t)(uintptr_t)dest) : "memory"); return ret; -- To view, visit https://review.coreboot.org/c/coreboot/+/69231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib43ec19df97194d6b1c18bfacb5fe8211ba0ffe5 Gerrit-Change-Number: 69231 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Don't sort struct device cpus for numa
by Jonathan Zhang (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Lance Zhao, Arthur Heymans, Anjaneya "Reddy" Chagam, Johnny Lin, Tim Wawrzynczak, Christian Walter, Angel Pons, Shuming Chu (Shuming), TangYiwei. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68912 ) Change subject: soc/intel/xeon_sp: Don't sort struct device cpus for numa ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: Yiwei, do you want to try this out? -- To view, visit https://review.coreboot.org/c/coreboot/+/68912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372bcea1932d28e9bf712cc712f19a76fe3199b1 Gerrit-Change-Number: 68912 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Fri, 04 Nov 2022 19:19:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: lib/coreboot_table: Rename lb_fill_pcie
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69183 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: lib/coreboot_table: Rename lb_fill_pcie ...................................................................... lib/coreboot_table: Rename lb_fill_pcie By convention 'fill_lb_xxx' is used. Change-Id: I046016b3898308bb56b4ad6a5834ab942fdd50f2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69183 Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c M src/soc/mediatek/common/pcie.c M src/soc/qualcomm/common/pcie_common.c 4 files changed, 20 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 4aab80e..e209e4b 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -22,7 +22,7 @@ enum cb_err fill_lb_serial(struct lb_serial *serial); void lb_add_console(uint16_t consoletype, void *data); -enum cb_err lb_fill_pcie(struct lb_pcie *pcie); +enum cb_err fill_lb_pcie(struct lb_pcie *pcie); /* Define this in mainboard.c to add board-specific table entries. */ void lb_board(struct lb_header *header); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 6c09cb1..0f20735 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -33,7 +33,7 @@ void lb_string_platform_blob_version(struct lb_header *header); #endif -__weak enum cb_err lb_fill_pcie(struct lb_pcie *pcie) +__weak enum cb_err fill_lb_pcie(struct lb_pcie *pcie) { return CB_ERR_NOT_IMPLEMENTED; } @@ -129,7 +129,7 @@ { struct lb_pcie pcie = { .tag = LB_TAG_PCIE, .size = sizeof(pcie) }; - if (lb_fill_pcie(&pcie) != CB_SUCCESS) + if (fill_lb_pcie(&pcie) != CB_SUCCESS) return; memcpy(lb_new_record(header), &pcie, sizeof(pcie)); diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index febb76d..fd93665 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -211,7 +211,7 @@ pci_domain_set_resources(dev); } -enum cb_err lb_fill_pcie(struct lb_pcie *pcie) +enum cb_err fill_lb_pcie(struct lb_pcie *pcie) { if (!pci_root_bus()) return CB_ERR; diff --git a/src/soc/qualcomm/common/pcie_common.c b/src/soc/qualcomm/common/pcie_common.c index e27b0fc..2f53e28 100644 --- a/src/soc/qualcomm/common/pcie_common.c +++ b/src/soc/qualcomm/common/pcie_common.c @@ -414,7 +414,7 @@ * Fill coreboot table with PCIe info. * It allows exporting this info to payloads. */ -enum cb_err lb_fill_pcie(struct lb_pcie *pcie) +enum cb_err fill_lb_pcie(struct lb_pcie *pcie) { pcie_cntlr_cfg_t *pcierc = qcom_pcie_cfg.cntlr_cfg; pcie->ctrl_base = (uintptr_t)pcierc->dbi_base; -- To view, visit https://review.coreboot.org/c/coreboot/+/69183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I046016b3898308bb56b4ad6a5834ab942fdd50f2 Gerrit-Change-Number: 69183 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2022