coreboot-gerrit November 2022

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[S] Change in coreboot[master]: vendorcode/amd/ccx_cppc_data.h: Fix header guard
by Arthur Heymans (Code Review) 04 Nov '22

04 Nov '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69230 ) Change subject: vendorcode/amd/ccx_cppc_data.h: Fix header guard ...................................................................... vendorcode/amd/ccx_cppc_data.h: Fix header guard Change-Id: I027c3aa7bb206112107ee120cf6f9854e37c5636 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/vendorcode/amd/fsp/common/ccx_cppc_data.h 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/69230/1 diff --git a/src/vendorcode/amd/fsp/common/ccx_cppc_data.h b/src/vendorcode/amd/fsp/common/ccx_cppc_data.h index ac88776..1f41d48 100644 --- a/src/vendorcode/amd/fsp/common/ccx_cppc_data.h +++ b/src/vendorcode/amd/fsp/common/ccx_cppc_data.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef COMMOM_FSP_CCX_CPPC_DATA_H +#ifndef COMMON_FSP_CCX_CPPC_DATA_H #define COMMON_FSP_CCX_CPPC_DATA_H #include <types.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/69230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I027c3aa7bb206112107ee120cf6f9854e37c5636 Gerrit-Change-Number: 69230 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]security/intel: Add option to eanble SMM flash access only
by Patrick Rudolph (Code Review) 04 Nov '22

04 Nov '22

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40830 ) Change subject: [WIP]security/intel: Add option to eanble SMM flash access only ...................................................................... [WIP]security/intel: Add option to eanble SMM flash access only On platforms where the boot media can be updated externally, for e.g. using a BMC, add the possibility to enable writes in SMM only. This allows to protect the BIOS region even without the use of vboot, but keeps the SMMSTORE working for the use in payloads. UNTESTED. Change-Id: I157db885b5f1d0f74009ede6fb2342b20d9429fa Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/security/lockdown/Kconfig M src/soc/intel/common/pch/lockdown/lockdown.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/common/spi.h M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/smi.c 8 files changed, 52 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/40830/1 diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig index d24c5e5..dbe6840 100644 --- a/src/security/lockdown/Kconfig +++ b/src/security/lockdown/Kconfig @@ -99,3 +99,13 @@ possible. This option prevents using write protecting facilities in ramstage, like the MRC cache for example. Use this option if you don't trust code running after verstage. + +config BOOTMEDIA_SMM_BWP + bool "Boot media only writable in SMM" + depends on ARCH_X86 + depends on HAVE_SMI_HANDLER + select SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE if SOC_INTEL_COMMON_BLOCK + help + Enable flash writes in SMM only. Select this if you want to secure + the SMM_STORE and don't need to update coreboot using the + internal controller. diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index a00e5c0..768c4cd 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -62,6 +62,12 @@ /* BIOS Interface Lock */ fast_spi_set_bios_interface_lock_down(); + /* Only allow writes in SMM */ + if (CONFIG(BOOTMEDIA_SMM_BWP)) { + fast_spi_set_eiss(); + fast_spi_enable_wp(); + } + /* BIOS Lock */ fast_spi_set_lock_enable(); } diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 278e90a..78bfb39 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -416,16 +416,6 @@ } } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - u8 reg8; - - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(1 << 5); - pci_write_config8(dev, BIOS_CNTL, reg8); -} - static void pch_fixups(struct device *dev) { u8 gen_pmcon_2; @@ -579,8 +569,6 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); - pch_set_acpi_mode(); pch_fixups(dev); diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 5e967af..253d33f 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -35,6 +35,10 @@ #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) +#define BIOS_CNTL 0xdc +#define LPC_BC_WE (1 << 0) /* WE */ +#define LPC_BC_LE (1 << 1) /* LE */ +#define LPC_BC_EISS (1 << 5) /* EISS */ static int spi_is_multichip(void); @@ -293,7 +297,6 @@ void spi_init(void) { - uint8_t bios_cntl; struct ich9_spi_regs *ich9_spi; struct ich7_spi_regs *ich7_spi; uint16_t hsfs; @@ -345,10 +348,7 @@ if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX) || CONFIG(SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9)) { /* Disable the BIOS write protect so write commands are allowed. */ - bios_cntl = pci_read_config8(dev, 0xdc); - /* Deassert SMM BIOS Write Protect Disable. */ - bios_cntl &= ~(1 << 5); - pci_write_config8(dev, 0xdc, bios_cntl | 0x1); + spi_smm_only_flashing(0); } } @@ -1108,12 +1108,35 @@ writeb_(spi_config->ops[i].op, &cntlr.opmenu[i]); } writew_(optype, cntlr.optype); + + spi_smm_only_flashing(CONFIG(BOOTMEDIA_SMM_BWP)); } __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) { } +void spi_smm_only_flashing(bool enable) +{ + pci_devfn_t dev = PCI_DEV(0, 31, 0); + u8 reg8 = pci_read_config8(dev, BIOS_CNTL); + + if (reg8 & LPC_BC_LE) + return; + + if (enable) { + reg8 |= LPC_BC_EISS; + reg8 &= ~LPC_BC_WE; + } else { + reg8 &= ~LPC_BC_EISS; + reg8 |= LPC_BC_WE; + } + pci_write_config8(dev, BIOS_CNTL, reg8); + + printk(BIOS_SPEW, "BIOS updates outside of SMM %s\n", + enable ? "enabled" : "disabled"); +} + static const struct spi_ctrlr spi_ctrlr = { .xfer_vector = xfer_vectors, .max_xfer_size = member_size(struct ich9_spi_regs, fdata), diff --git a/src/southbridge/intel/common/spi.h b/src/southbridge/intel/common/spi.h index 3b8410c..ad1cb27 100644 --- a/src/southbridge/intel/common/spi.h +++ b/src/southbridge/intel/common/spi.h @@ -32,6 +32,7 @@ struct intel_spi_op ops[8]; }; +void spi_smm_only_flashing(bool enable); void spi_finalize_ops(void); void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 395919e..67c03fa 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -420,16 +420,6 @@ } } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - u8 reg8; - - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(1 << 5); - pci_write_config8(dev, BIOS_CNTL, reg8); -} - static void pch_fixups(struct device *dev) { /* @@ -482,8 +472,6 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); - pch_set_acpi_mode(); pch_fixups(dev); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index d9ef5cc..dafb901 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -481,16 +481,6 @@ } } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - u8 reg8; - - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(1 << 5); - pci_write_config8(dev, BIOS_CNTL, reg8); -} - static void pch_fixups(struct device *dev) { u8 gen_pmcon_2; @@ -549,8 +539,6 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); - pch_set_acpi_mode(); pch_fixups(dev); diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 05b5bb5..82e96f3 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -40,6 +40,8 @@ void smm_southbridge_enable_smi(void) { + u32 mask; + printk(BIOS_DEBUG, "Enabling SMIs.\n"); /* Configure events */ enable_pm1(PWRBTN_EN | GBL_EN); @@ -49,11 +51,14 @@ * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) + * - on TCO events * No SMIs: * - on microcontroller writes (io 0x62/0x66) - * - on TCO events */ - enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); + mask = APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS; + if (CONFIG(BOOTMEDIA_SMM_BWP)) + mask |= TCO_EN; + enable_smi(mask); } static void __unused southbridge_trigger_smi(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/40830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I157db885b5f1d0f74009ede6fb2342b20d9429fa Gerrit-Change-Number: 40830 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: Revert "drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling"
by Patrick Georgi (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Felix Held. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69228 ) Change subject: Revert "drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling" ...................................................................... Patch Set 1: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb2fa27e75eede1648ddbf82c8bfbeeb2e9220a6 Gerrit-Change-Number: 69228 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Nov 2022 18:43:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/sifive/ux00ddr.h: Remove set but unused variables
by build bot (Jenkins) (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans, Philipp Hug, ron minnich, Elyes Haouas. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63074 ) Change subject: soc/sifive/ux00ddr.h: Remove set but unused variables ...................................................................... Patch Set 12: (4 comments) File src/soc/sifive/fu540/ux00ddr.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162446): https://review.coreboot.org/c/coreboot/+/63074/comment/a638c09d_07384f4f PS12, Line 179: /* char slicelsc = '0'; */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162446): https://review.coreboot.org/c/coreboot/+/63074/comment/fe19148a_ba42d044 PS12, Line 180: /* char slicemsc = '0'; */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162446): https://review.coreboot.org/c/coreboot/+/63074/comment/ccd8aa32_99d8dd0a PS12, Line 181: /* slicelsc += (dq % 10); */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162446): https://review.coreboot.org/c/coreboot/+/63074/comment/70663357_625b96f2 PS12, Line 182: /* slicemsc += (dq / 10); */ code indent should use tabs where possible -- To view, visit https://review.coreboot.org/c/coreboot/+/63074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I442a42e297f2968dd2c824a93a9a1e2bc74ea2f4 Gerrit-Change-Number: 63074 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 04 Nov 2022 18:40:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/adlrvp: Fix expected statement
by Arthur Heymans (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Michał Żygowski, Michał Kopeć, Elyes Haouas. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66266 ) Change subject: mb/intel/adlrvp: Fix expected statement ...................................................................... Patch Set 5: (1 comment) Patchset: PS2: > so, " case ADL_P_LP5_1: > case ADL_P_LP5_2:" will never happen? From K&R C: The case labeled default is executed if none of the other cases are satisfied. So no the other cases will get executed. Other C language texts suggest to put the default statement at the end of switch statements but there is no such thing in K&R C. With BUILD_TIMELESS=1 the binary remains identical btw. -- To view, visit https://review.coreboot.org/c/coreboot/+/66266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a5d39bb3cbde64f82fc90186b0f2fb64bcde595 Gerrit-Change-Number: 66266 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 04 Nov 2022 18:38:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: arch/arm: Fix assembling files with clang
by Arthur Heymans (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans. Arthur Heymans has uploaded a new patch set (#14) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/63058 ) Change subject: arch/arm: Fix assembling files with clang ...................................................................... arch/arm: Fix assembling files with clang Taken from Linux which also updated these files. Change-Id: Ia320dc2c460c99d934b8f17dee7748a9def4e750 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/arm/libgcc/lib1funcs.S M src/arch/arm/memcpy.S M src/arch/arm/memmove.S M src/arch/arm/memset.S 4 files changed, 55 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/63058/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/63058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia320dc2c460c99d934b8f17dee7748a9def4e750 Gerrit-Change-Number: 63058 Gerrit-PatchSet: 14 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/nvidia/tegra124: Fix building with clang
by Arthur Heymans (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans. Arthur Heymans has uploaded a new patch set (#14) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/63063 ) Change subject: soc/nvidia/tegra124: Fix building with clang ...................................................................... soc/nvidia/tegra124: Fix building with clang This kind of allocation without '=' is not working with clang. Change-Id: I2d3e9eb44c3e0e25e5a67c5386e5ddde1487cc74 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/nvidia/tegra124/clock.c 1 file changed, 19 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/63063/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/63063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d3e9eb44c3e0e25e5a67c5386e5ddde1487cc74 Gerrit-Change-Number: 63063 Gerrit-PatchSet: 14 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: arch/riscv/mcall.h: Fix building with clang
by Arthur Heymans (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans, Philipp Hug, ron minnich. Arthur Heymans has uploaded a new patch set (#14) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/63072 ) Change subject: arch/riscv/mcall.h: Fix building with clang ...................................................................... arch/riscv/mcall.h: Fix building with clang Having multiple statements hidden inside a macro that supposedly returns a pointer does not work well with clang. Moving the stack register to a global variable fixes this. Change-Id: If24b2766404b892a006926f0cd45771ceebf1275 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/riscv/include/mcall.h 1 file changed, 17 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/63072/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/63072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If24b2766404b892a006926f0cd45771ceebf1275 Gerrit-Change-Number: 63072 Gerrit-PatchSet: 14 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: arch/riscv: Use updated name for sbadaddr
by Arthur Heymans (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans, Philipp Hug, Angel Pons, ron minnich. Arthur Heymans has uploaded a new patch set (#14) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/63073 ) Change subject: arch/riscv: Use updated name for sbadaddr ...................................................................... arch/riscv: Use updated name for sbadaddr The riscv spec v1.10.0 updated this name. This fixes building with clang. Change-Id: Ic86e5070b084bf1ce03fe30d46abbbd0c88b9532 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/riscv/trap_handler.c M src/arch/riscv/trap_util.S 2 files changed, 15 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/63073/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/63073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic86e5070b084bf1ce03fe30d46abbbd0c88b9532 Gerrit-Change-Number: 63073 Gerrit-PatchSet: 14 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/sifive/ux00ddr.h: Remove set but unused variables
by Arthur Heymans (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans, Philipp Hug, ron minnich, Elyes Haouas. Arthur Heymans has uploaded a new patch set (#15) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/63074 ) Change subject: soc/sifive/ux00ddr.h: Remove set but unused variables ...................................................................... soc/sifive/ux00ddr.h: Remove set but unused variables It looks like this code was not finished so it's left commented out for now. Change-Id: I442a42e297f2968dd2c824a93a9a1e2bc74ea2f4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/sifive/fu540/ux00ddr.h 1 file changed, 17 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/63074/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/63074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I442a42e297f2968dd2c824a93a9a1e2bc74ea2f4 Gerrit-Change-Number: 63074 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2022