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[L] Change in coreboot[master]: lib/coreboot_table: Simplify API to set up lb_serial
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68768 ) Change subject: lib/coreboot_table: Simplify API to set up lb_serial ...................................................................... lib/coreboot_table: Simplify API to set up lb_serial Instead of having callbacks into serial console code to set up the coreboot table have the coreboot table code call IP specific code to get serial information. This makes it easier to reuse the information as the return value can be used in a different context (e.g. when filling in a FDT). This also removes boilerplate code to set up lb_console entries by setting entry based on the type in struct lb_uart. Change-Id: I6c08a88fb5fc035eb28d0becf19471c709c8043d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68768 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/drivers/uart/pl011.c M src/drivers/uart/sifive.c M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c M src/mainboard/emulation/qemu-power8/uart.c M src/soc/mediatek/common/uart.c M src/soc/nvidia/tegra124/uart.c M src/soc/nvidia/tegra210/uart.c M src/soc/qualcomm/common/qupv3_uart.c M src/soc/qualcomm/common/uart_bitbang.c M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/qcs405/uart.c M src/soc/samsung/exynos5250/uart.c M src/soc/samsung/exynos5420/uart.c M src/soc/ti/am335x/uart.c M tests/lib/coreboot_table-test.c 19 files changed, 145 insertions(+), 170 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 3653262..0661de1 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -35,15 +35,13 @@ return read8(&regs->dr); } -void uart_fill_lb(void *data) +enum cb_err fill_lb_serial(struct lb_serial *serial) { - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = get_uart_baudrate(); - serial.regwidth = 1; - serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); + serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial->baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial->baud = get_uart_baudrate(); + serial->regwidth = 1; + serial->input_hertz = uart_platform_refclk(); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return CB_SUCCESS; } diff --git a/src/drivers/uart/sifive.c b/src/drivers/uart/sifive.c index 31181aa..d1b89dc 100644 --- a/src/drivers/uart/sifive.c +++ b/src/drivers/uart/sifive.c @@ -100,7 +100,8 @@ return 1; } -void uart_fill_lb(void *data) +enum cb_err fill_lb_serial(struct lb_serial *serial) { + return CB_ERR; /* TODO */ } diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 7ca2452..a7fc346 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -109,15 +109,13 @@ uart8250_tx_flush(uart_platform_base(idx)); } -void uart_fill_lb(void *data) +enum cb_err fill_lb_serial(struct lb_serial *serial) { - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_IO_MAPPED; - serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = get_uart_baudrate(); - serial.regwidth = 1; - serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); + serial->type = LB_SERIAL_TYPE_IO_MAPPED; + serial->baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial->baud = get_uart_baudrate(); + serial->regwidth = 1; + serial->input_hertz = uart_platform_refclk(); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data); + return CB_SUCCESS; } diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 79e786b..19677a8 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -133,20 +133,18 @@ uart8250_mem_tx_flush(base); } -void uart_fill_lb(void *data) +enum cb_err fill_lb_serial(struct lb_serial *serial) { - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - if (!serial.baseaddr) - return; - serial.baud = get_uart_baudrate(); + serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial->baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + if (!serial->baseaddr) + return CB_ERR; + serial->baud = get_uart_baudrate(); if (CONFIG(DRIVERS_UART_8250MEM_32)) - serial.regwidth = sizeof(uint32_t); + serial->regwidth = sizeof(uint32_t); else - serial.regwidth = sizeof(uint8_t); - serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); + serial->regwidth = sizeof(uint8_t); + serial->input_hertz = uart_platform_refclk(); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return CB_SUCCESS; } diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 6188ce0..4aab80e 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -19,8 +19,7 @@ void lb_add_gpios(struct lb_gpios *gpios, const struct lb_gpio *gpio_table, size_t count); -void uart_fill_lb(void *data); -void lb_add_serial(struct lb_serial *serial, void *data); +enum cb_err fill_lb_serial(struct lb_serial *serial); void lb_add_console(uint16_t consoletype, void *data); enum cb_err lb_fill_pcie(struct lb_pcie *pcie); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 4df7039..6c09cb1 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -96,19 +96,22 @@ return mem; } -void lb_add_serial(struct lb_serial *new_serial, void *data) +static void lb_add_serial(struct lb_header *header) { - struct lb_header *header = (struct lb_header *)data; - struct lb_serial *serial; + struct lb_serial new_serial = { .tag = LB_TAG_SERIAL, + .size = sizeof(struct lb_serial), + }; + if (fill_lb_serial(&new_serial) != CB_SUCCESS) + return; - serial = (struct lb_serial *)lb_new_record(header); - serial->tag = LB_TAG_SERIAL; - serial->size = sizeof(*serial); - serial->type = new_serial->type; - serial->baseaddr = new_serial->baseaddr; - serial->baud = new_serial->baud; - serial->regwidth = new_serial->regwidth; - serial->input_hertz = new_serial->input_hertz; + struct lb_serial *serial = (struct lb_serial *)lb_new_record(header); + memcpy(serial, &new_serial, sizeof(*serial)); + assert(serial->type == LB_SERIAL_TYPE_IO_MAPPED + || serial->type == LB_SERIAL_TYPE_MEMORY_MAPPED) + if (serial->type == LB_SERIAL_TYPE_IO_MAPPED) + lb_add_console(LB_TAG_CONSOLE_SERIAL8250, header); + else + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, header); } void lb_add_console(uint16_t consoletype, void *data) @@ -492,7 +495,7 @@ /* Record the serial ports and consoles */ if (CONFIG(CONSOLE_SERIAL)) - uart_fill_lb(head); + lb_add_serial(head); if (CONFIG(CONSOLE_USB)) lb_add_console(LB_TAG_CONSOLE_EHCI, head); diff --git a/src/mainboard/emulation/qemu-power8/uart.c b/src/mainboard/emulation/qemu-power8/uart.c index a2f9116..a369e62 100644 --- a/src/mainboard/emulation/qemu-power8/uart.c +++ b/src/mainboard/emulation/qemu-power8/uart.c @@ -28,16 +28,13 @@ { } -void uart_fill_lb(void *data) +enum cb_err fill_lb_serial(struct lb_serial *serial) { - struct lb_serial serial; + serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial->baseaddr = 0; + serial->baud = 115200; + serial->regwidth = 1; + serial->input_hertz = uart_platform_refclk(); - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = 0; - serial.baud = 115200; - serial.regwidth = 1; - serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); - - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return CB_SUCCESS; } diff --git a/src/soc/mediatek/common/uart.c b/src/soc/mediatek/common/uart.c index 11c3452..79ca072 100644 --- a/src/soc/mediatek/common/uart.c +++ b/src/soc/mediatek/common/uart.c @@ -159,15 +159,13 @@ mtk_uart_tx_flush(); } -void uart_fill_lb(void *data) +enum cb_err fill_lb_serial(struct lb_serial *serial) { - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = UART0_BASE; - serial.baud = get_uart_baudrate(); - serial.regwidth = 4; - serial.input_hertz = UART_HZ; - lb_add_serial(&serial, data); + serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial->baseaddr = UART0_BASE; + serial->baud = get_uart_baudrate(); + serial->regwidth = 4; + serial->input_hertz = UART_HZ; - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return CB_SUCCESS; } diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index 77d6de2..557f0e8 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -114,15 +114,13 @@ tegra124_uart_tx_flush(uart_ptr); } -void uart_fill_lb(void *data) +enum cb_err fill_lb_serial(struct lb_serial *serial) { - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = get_uart_baudrate(); - serial.regwidth = 4; - serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); + serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial->baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial->baud = get_uart_baudrate(); + serial->regwidth = 4; + serial->input_hertz = uart_platform_refclk(); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return CB_SUCCESS; } diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c index b2cdf67..3366065 100644 --- a/src/soc/nvidia/tegra210/uart.c +++ b/src/soc/nvidia/tegra210/uart.c @@ -101,15 +101,13 @@ return tegra210_uart_rx_byte(); } -void uart_fill_lb(void *data) +enum cb_err fill_lb_serial(struct lb_serial *serial) { - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS; - serial.baud = get_uart_baudrate(); - serial.regwidth = 4; - serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); + serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial->baseaddr = CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS; + serial->baud = get_uart_baudrate(); + serial->regwidth = 4; + serial->input_hertz = uart_platform_refclk(); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return CB_SUCCESS; } diff --git a/src/soc/qualcomm/common/qupv3_uart.c b/src/soc/qualcomm/common/qupv3_uart.c index 2086c1d..f4ff53b 100644 --- a/src/soc/qualcomm/common/qupv3_uart.c +++ b/src/soc/qualcomm/common/qupv3_uart.c @@ -140,15 +140,13 @@ return (uintptr_t)qup[idx].regs; } -void uart_fill_lb(void *data) +enum cb_err fill_lb_serial(struct lb_serial *serial) { - struct lb_serial serial = {0}; + serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial->baseaddr = (uint32_t)uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial->baud = get_uart_baudrate(); + serial->regwidth = 4; + serial->input_hertz = SRC_XO_HZ; - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = (uint32_t)uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = get_uart_baudrate(); - serial.regwidth = 4; - serial.input_hertz = SRC_XO_HZ; - - lb_add_serial(&serial, data); + return CB_SUCCESS; } diff --git a/src/soc/qualcomm/common/uart_bitbang.c b/src/soc/qualcomm/common/uart_bitbang.c index 943dcf8..d6447f1 100644 --- a/src/soc/qualcomm/common/uart_bitbang.c +++ b/src/soc/qualcomm/common/uart_bitbang.c @@ -5,9 +5,9 @@ #include <boot/coreboot_tables.h> #include <soc/uart.h> -void uart_fill_lb(void *data) +enum cb_err fill_lb_serial(struct lb_serial *serial) { - + return CB_ERR; } static void set_tx(int line_state) diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index c04a773..45dc09a 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -256,16 +256,13 @@ } /* TODO: Implement function */ -void uart_fill_lb(void *data) +enum cb_err fill_lb_serial(struct lb_serial *serial) { - struct lb_serial serial; + serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial->baseaddr = (uint32_t)UART1_DM_BASE; + serial->baud = get_uart_baudrate(); + serial->regwidth = 1; + serial->input_hertz = uart_platform_refclk(); - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = (uint32_t)UART1_DM_BASE; - serial.baud = get_uart_baudrate(); - serial.regwidth = 1; - serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); - - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return CB_SUCCESS; } diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index 15a0998..6d69edc 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -368,6 +368,7 @@ } /* TODO: Implement function */ -void uart_fill_lb(void *data) +enum cb_err fill_lb_serial(struct lb_serial *serial) { + return CB_ERR; } diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c index 007a980..16c71b4 100644 --- a/src/soc/qualcomm/qcs405/uart.c +++ b/src/soc/qualcomm/qcs405/uart.c @@ -257,16 +257,13 @@ } #endif -void uart_fill_lb(void *data) +enum cb_err fill_lb_serial(struct lb_serial *serial) { - struct lb_serial serial; + serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial->baseaddr = (uint64_t)UART2_DM_BASE; + serial->baud = get_uart_baudrate(); + serial->regwidth = 1; + serial->input_hertz = uart_platform_refclk(); - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = (uint64_t)UART2_DM_BASE; - serial.baud = get_uart_baudrate(); - serial.regwidth = 1; - serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); - - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return CB_SUCCESS; } diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c index 7943651..7cd1d46 100644 --- a/src/soc/samsung/exynos5250/uart.c +++ b/src/soc/samsung/exynos5250/uart.c @@ -132,15 +132,13 @@ exynos5_uart_tx_flush(uart); } -void uart_fill_lb(void *data) +enum cb_err fill_lb_serial(struct lb_serial *serial) { - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = get_uart_baudrate(); - serial.regwidth = 4; - serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); + serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial->baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial->baud = get_uart_baudrate(); + serial->regwidth = 4; + serial->input_hertz = uart_platform_refclk(); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return CB_SUCCESS; } diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c index 1268183..eb1d3f9 100644 --- a/src/soc/samsung/exynos5420/uart.c +++ b/src/soc/samsung/exynos5420/uart.c @@ -123,15 +123,13 @@ /* Exynos5250 implements this too. */ } -void uart_fill_lb(void *data) +enum cb_err fill_lb_serial(struct lb_serial *serial) { - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = get_uart_baudrate(); - serial.regwidth = 4; - serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); + serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial->baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial->baud = get_uart_baudrate(); + serial->regwidth = 4; + serial->input_hertz = uart_platform_refclk(); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return CB_SUCCESS; } diff --git a/src/soc/ti/am335x/uart.c b/src/soc/ti/am335x/uart.c index 136d785..b19ba96 100644 --- a/src/soc/ti/am335x/uart.c +++ b/src/soc/ti/am335x/uart.c @@ -170,15 +170,13 @@ { } -void uart_fill_lb(void *data) +enum cb_err fill_lb_serial(struct lb_serial *serial) { - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); - serial.baud = get_uart_baudrate(); - serial.regwidth = 2; - serial.input_hertz = uart_platform_refclk(); - lb_add_serial(&serial, data); + serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial->baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial->baud = get_uart_baudrate(); + serial->regwidth = 2; + serial->input_hertz = uart_platform_refclk(); - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return CB_SUCCESS; } diff --git a/tests/lib/coreboot_table-test.c b/tests/lib/coreboot_table-test.c index 5257552..16ab97f 100644 --- a/tests/lib/coreboot_table-test.c +++ b/tests/lib/coreboot_table-test.c @@ -117,25 +117,6 @@ } } -static void test_lb_add_serial(void **state) -{ - struct lb_header *header = *state; - struct lb_serial serial; - - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = 0xFEDC6000; - serial.baud = 115200; - serial.regwidth = 1; - serial.input_hertz = 115200 * 16; - lb_add_serial(&serial, header); - - assert_int_equal(1, header->table_entries); - /* Table bytes and checksum should be zero, because it is updated with size of previous - record or when table is closed. No previous record is present. */ - assert_int_equal(0, header->table_bytes); - assert_int_equal(0, header->table_checksum); -} - static void test_lb_add_console(void **state) { struct lb_header *header = *state; @@ -235,17 +216,15 @@ } } -void uart_fill_lb(void *data) +enum cb_err fill_lb_serial(struct lb_serial *serial) { - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = 0xFEDC6000; - serial.baud = 115200; - serial.regwidth = 1; - serial.input_hertz = 115200 * 16; - lb_add_serial(&serial, data); + serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial->baseaddr = 0xFEDC6000; + serial->baud = 115200; + serial->regwidth = 1; + serial->input_hertz = 115200 * 16; - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); + return CB_SUCCESS; } struct cbfs_boot_device cbfs_boot_dev = { @@ -495,7 +474,6 @@ const struct CMUnitTest tests[] = { cmocka_unit_test(test_lb_add_gpios), cmocka_unit_test_setup(test_lb_new_record, setup_test_header), - cmocka_unit_test_setup(test_lb_add_serial, setup_test_header), cmocka_unit_test_setup(test_lb_add_console, setup_test_header), cmocka_unit_test_setup(test_multiple_entries, setup_test_header), cmocka_unit_test_setup(test_write_coreboot_forwarding_table, setup_test_header), -- To view, visit https://review.coreboot.org/c/coreboot/+/68768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c08a88fb5fc035eb28d0becf19471c709c8043d Gerrit-Change-Number: 68768 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: cpu/x86/mp_init.c: Use existing code to create cpu struct device
by Jonathan Zhang (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans, Kyösti Mälkki. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64341 ) Change subject: cpu/x86/mp_init.c: Use existing code to create cpu struct device ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80baadd405b31d6be2fdbb894b0f4b7c775da6f8 Gerrit-Change-Number: 64341 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 19:13:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brask/var/kuldax: Update PsysPL2 and PsysPmax
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69155 ) Change subject: mb/google/brask/var/kuldax: Update PsysPL2 and PsysPmax ...................................................................... mb/google/brask/var/kuldax: Update PsysPL2 and PsysPmax Update PsysPL2 and PsysPmax. BUG=b:253542746 TEST=Make sure PsysPL2 and PsysPamx values set properly (through debug output) Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I0ffad751e8a99b282a5d05563a60745ee09e892c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69155 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/kuldax/ramstage.c 1 file changed, 38 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kuldax/ramstage.c b/src/mainboard/google/brya/variants/kuldax/ramstage.c index 4bec1d4..5a71237 100644 --- a/src/mainboard/google/brya/variants/kuldax/ramstage.c +++ b/src/mainboard/google/brya/variants/kuldax/ramstage.c @@ -20,45 +20,45 @@ const struct system_power_limits sys_limits[] = { /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ - { PCI_DID_INTEL_ADL_P_ID_10, 15, 65 }, - { PCI_DID_INTEL_ADL_P_ID_7, 15, 150 }, - { PCI_DID_INTEL_ADL_P_ID_6, 15, 150 }, - { PCI_DID_INTEL_ADL_P_ID_5, 28, 150 }, - { PCI_DID_INTEL_ADL_P_ID_3, 28, 150 }, + { PCI_DID_INTEL_ADL_P_ID_10, 15, 83 }, + { PCI_DID_INTEL_ADL_P_ID_7, 15, 225 }, + { PCI_DID_INTEL_ADL_P_ID_6, 15, 225 }, + { PCI_DID_INTEL_ADL_P_ID_5, 28, 225 }, + { PCI_DID_INTEL_ADL_P_ID_3, 28, 225 }, }; const struct system_power_limits revise_sys_limits[] = { /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ - { PCI_DID_INTEL_ADL_P_ID_10, 15, 150 }, - { PCI_DID_INTEL_ADL_P_ID_7, 15, 150 }, - { PCI_DID_INTEL_ADL_P_ID_6, 15, 150 }, - { PCI_DID_INTEL_ADL_P_ID_5, 28, 150 }, - { PCI_DID_INTEL_ADL_P_ID_3, 28, 150 }, + { PCI_DID_INTEL_ADL_P_ID_10, 15, 225 }, + { PCI_DID_INTEL_ADL_P_ID_7, 15, 225 }, + { PCI_DID_INTEL_ADL_P_ID_6, 15, 225 }, + { PCI_DID_INTEL_ADL_P_ID_5, 28, 225 }, + { PCI_DID_INTEL_ADL_P_ID_3, 28, 225 }, }; /* * Psys_pmax considerations. * * Given the hardware design in kuldax, the serial shunt resistor is 0.005ohm. - * The full scale of hardware PSYS signal 1.6v maps to system current 7.5A + * The full scale of hardware PSYS signal 1.6v maps to system current 11.25A * instead of real system power. The equation is shown below: - * PSYS = 1.6v = (0.01ohm x 7.5A) x 50 (INA213, gain 50V/V) x R501/(R501 + R510) - * R501/(R501 + R510) = 0.858 = 20K / (20K + 3.3K) + * PSYS = 1.6v = (0.005ohm x 11.25A) x 50 (INA213, gain 50V/V) x R501/(R501 + R510) + * R501/(R501 + R510) = 0.57 = 20K / (20K + 15K) * * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping b/w system input * current and the actual system power. Since there is no voltage information * from PSYS, different voltage input would map to different Psys_pmax settings: - * For Type-C 15V, the Psys_pmax should be 15v x 7.5A = 112.5W - * For Type-C 20V, the Psys_pmax should be 20v x 7.5A = 150W - * For a barrel jack, the Psys_pmax should be 20v x 7.5A = 150W + * For Type-C 15V, the Psys_pmax should be 15v x 11.25A = 168.75W + * For Type-C 20V, the Psys_pmax should be 20v x 11.25A = 225W + * For a barrel jack, the Psys_pmax should be 20v x 11.25A = 225W * * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading, - * and the Psys_pmax setting is 150W. Then IMVP9.1 can calculate the current system - * power = 150W * 5A / 7.5A = 100W, which is the actual system power. + * and the Psys_pmax setting is 225W. Then IMVP9.1 can calculate the current system + * power = 225W * 5A / 11.25A = 100W, which is the actual system power. */ const struct psys_config psys_config = { .efficiency = 97, - .psys_imax_ma = 7500, + .psys_imax_ma = 11250, .bj_volts_mv = 20000 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/69155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ffad751e8a99b282a5d05563a60745ee09e892c Gerrit-Change-Number: 69155 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: include/device/pci_def.h: Add some PCIe DPC/AER definitions
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69106 ) Change subject: include/device/pci_def.h: Add some PCIe DPC/AER definitions ...................................................................... include/device/pci_def.h: Add some PCIe DPC/AER definitions * Add DPC related definitions which are defined in 7.9.14 of PCIe 6.0 spec. * Add AER related definitions which are defined in 7.8.4 of PCIe 6.0 spec. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: Ifb6722c326ef69ef1bf3b1c2c1d5bc0cb29d7c12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69106 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> --- M src/include/device/pci_def.h 1 file changed, 38 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Jonathan Zhang: Looks good to me, approved diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 64c1ac2..39369f8 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -478,6 +478,7 @@ #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ #define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */ #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ +#define PCI_ERR_SURPRISE_DN 0x00000020 /* Surprise Down */ #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ @@ -487,6 +488,8 @@ #define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ #define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ #define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ +#define PCI_ERR_UNC_INTL_ERR 0x00400000 /* Uncorrectable Internal Error */ +#define PCI_ERR_UNC_POISON_BLK 0x04000000 /* Poisoned TLP Egress Blocked */ #define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */ /* Same bits as above */ #define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */ @@ -497,6 +500,9 @@ #define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ #define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ #define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ +#define PCI_ERR_COR_ANF 0x00002000 /* Advisory Non-Fatal Error */ +#define PCI_ERR_COR_INTL_ERR 0x00004000 /* Corrected Internal Error */ +#define PCI_ERR_COR_LOG_OVER 0x00008000 /* Header Log Overflow Error */ #define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ /* Same bits as above */ #define PCI_ERR_CAP 24 /* Advanced Error Capabilities */ @@ -507,10 +513,23 @@ #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ #define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ #define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ +#define PCI_EXP_ROOT_CERE 0x0001 /* Correctable Error Reporting Enable */ +#define PCI_EXP_ROOT_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ +#define PCI_EXP_ROOT_FERE 0x0004 /* Fatal Error Reporting Enable */ #define PCI_ERR_ROOT_STATUS 48 #define PCI_ERR_ROOT_COR_SRC 52 #define PCI_ERR_ROOT_SRC 54 +/* DPC Capability Structure */ +#define PCIE_DPC_CAP_ID 0x1d +#define PCIE_DPC_CTL 0x6 +#define DPC_TRIGGER_EN (1 << 1) +#define DPC_INT_EN (1 << 3) +#define DPC_ERR_COR_EN (1 << 4) +#define DPC_POISON_TLP (1 << 5) +#define PCIE_DPC_RP_PIO_MASK 0x10 +#define PCIE_DPC_SEV 0x14 + /* Virtual Channel */ #define PCI_VC_PORT_REG1 4 #define PCI_VC_PORT_REG2 8 -- To view, visit https://review.coreboot.org/c/coreboot/+/69106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb6722c326ef69ef1bf3b1c2c1d5bc0cb29d7c12 Gerrit-Change-Number: 69106 Gerrit-PatchSet: 4 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/sifive/ux00ddr.h: Remove set but unused variables
by build bot (Jenkins) (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans, Philipp Hug, ron minnich, Elyes Haouas. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63074 ) Change subject: soc/sifive/ux00ddr.h: Remove set but unused variables ...................................................................... Patch Set 13: (4 comments) File src/soc/sifive/fu540/ux00ddr.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162456): https://review.coreboot.org/c/coreboot/+/63074/comment/fc7be944_7ee5047e PS13, Line 179: /* char slicelsc = '0'; */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162456): https://review.coreboot.org/c/coreboot/+/63074/comment/e79900a1_1fbfd214 PS13, Line 180: /* char slicemsc = '0'; */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162456): https://review.coreboot.org/c/coreboot/+/63074/comment/2b9d6659_e3c1b8e0 PS13, Line 181: /* slicelsc += (dq % 10); */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162456): https://review.coreboot.org/c/coreboot/+/63074/comment/322549d1_18635e0f PS13, Line 182: /* slicemsc += (dq / 10); */ code indent should use tabs where possible -- To view, visit https://review.coreboot.org/c/coreboot/+/63074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I442a42e297f2968dd2c824a93a9a1e2bc74ea2f4 Gerrit-Change-Number: 63074 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 04 Nov 2022 19:12:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Fix incompatible function pointers
by Subrata Banik (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Arthur Heymans, Elyes Haouas, Felix Held. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66263 ) Change subject: soc/intel/meteorlake: Fix incompatible function pointers ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/66263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia00706b9cd718e590819621986dbd20555f6c226 Gerrit-Change-Number: 66263 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Nov 2022 19:05:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/sifive/ux00ddr.h: Remove set but unused variables
by Angel Pons (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans, Philipp Hug, ron minnich, Elyes Haouas. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63074 ) Change subject: soc/sifive/ux00ddr.h: Remove set but unused variables ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I442a42e297f2968dd2c824a93a9a1e2bc74ea2f4 Gerrit-Change-Number: 63074 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 04 Nov 2022 18:49:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/testing: Buildtest with clang
by Angel Pons (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62173 ) Change subject: util/testing: Buildtest with clang ...................................................................... Patch Set 37: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82d756e071a0e575db73fbd91167d27cae3ddc18 Gerrit-Change-Number: 62173 Gerrit-PatchSet: 37 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 04 Nov 2022 18:49:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vendorcode/amd/ccx_cppc_data.h: Fix header guard
by Angel Pons (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69230 ) Change subject: vendorcode/amd/ccx_cppc_data.h: Fix header guard ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I027c3aa7bb206112107ee120cf6f9854e37c5636 Gerrit-Change-Number: 69230 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 04 Nov 2022 18:49:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/adlrvp: Fix expected statement
by Angel Pons (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Michał Żygowski, Michał Kopeć, Arthur Heymans, Elyes Haouas. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66266 ) Change subject: mb/intel/adlrvp: Fix expected statement ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/66266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a5d39bb3cbde64f82fc90186b0f2fb64bcde595 Gerrit-Change-Number: 66266 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 04 Nov 2022 18:48:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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