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Change subject: configs: Add 64bit buildtest for prodrive/hermes
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File configs/config.prodrive_hermes_x86_64:
PS1:
File might need to be named `config.prodrive_hermes.x86_64`
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Change subject: configs: Add 64bit buildtest for prodrive/hermes
......................................................................
configs: Add 64bit buildtest for prodrive/hermes
This configuration also boots on real hardware.
Change-Id: Ic62a33f8d8c3fdaa8182e797b2bf6fbed6b55731
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
A configs/config.prodrive_hermes_x86_64
1 file changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/69236/1
diff --git a/configs/config.prodrive_hermes_x86_64 b/configs/config.prodrive_hermes_x86_64
new file mode 100644
index 0000000..506f494
--- /dev/null
+++ b/configs/config.prodrive_hermes_x86_64
@@ -0,0 +1,17 @@
+# Settings used by Prodrive to build coreboot for the Hermes but with x86_64 enabled
+CONFIG_VENDOR_PRODRIVE=y
+CONFIG_BOARD_PRODRIVE_HERMES=y
+CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Prodrive Technologies B.V."
+CONFIG_POST_IO=y
+CONFIG_USE_LEGACY_8254_TIMER=y
+CONFIG_HERMES_USES_SPS_FIRMWARE=y
+CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
+CONFIG_SMMSTORE=y
+CONFIG_SMMSTORE_V2=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3=y
+CONFIG_POST_DEVICE_LPC=y
+CONFIG_MAINBOARD_SERIAL_NUMBER="N/A"
+CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y
+CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=36
+CONFIG_RUN_FSP_GOP=y
+CONFIG_USE_EXP_X86_64_SUPPORT=y
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Change subject: Set x86_64 as supported architecture for clang
......................................................................
Set x86_64 as supported architecture for clang
This boots on both qemu and real hardware now.
Change-Id: Ibd320059cff575847bbf1844b5bb100312f77916
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/arch/x86/Kconfig
1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/69235/1
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index b60f600..f7f87d6 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -64,6 +64,7 @@
select ARCH_VERSTAGE_X86_64
select ARCH_ROMSTAGE_X86_64
select ARCH_RAMSTAGE_X86_64
+ select ARCH_SUPPORTS_CLANG
config ARCH_ALL_STAGES_X86
bool
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Change subject: include/cper.h: Add CPER Memory Error Section definitions
......................................................................
Patch Set 2:
(1 comment)
File src/include/cper.h:
https://review.coreboot.org/c/coreboot/+/69198/comment/a131ad5d_290eaa3c
PS2, Line 508: /* UEFI Spec, Appendix N.2.5 Memory Error Types */
Let's add the spec version, table number, such as "IA32/X64 Processor Error Section (Table 255)"; also put it in the right sequence instead of end of the header file.
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Change subject: soc/sifive/ux00ddr.h: Remove set but unused variables
......................................................................
Patch Set 14:
(4 comments)
File src/soc/sifive/fu540/ux00ddr.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162465):
https://review.coreboot.org/c/coreboot/+/63074/comment/64508e29_6a1c22ce
PS14, Line 179: /* char slicelsc = '0'; */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162465):
https://review.coreboot.org/c/coreboot/+/63074/comment/81e32688_c5b526b5
PS14, Line 180: /* char slicemsc = '0'; */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162465):
https://review.coreboot.org/c/coreboot/+/63074/comment/72e82a13_9009a428
PS14, Line 181: /* slicelsc += (dq % 10); */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162465):
https://review.coreboot.org/c/coreboot/+/63074/comment/003028cb_eaa3a6fc
PS14, Line 182: /* slicemsc += (dq / 10); */
code indent should use tabs where possible
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Change subject: soc/intel/xeon_sp: Remove unused 'soc_chip.h' file
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/xeon_sp/include/soc/soc_chip.h:
https://review.coreboot.org/c/coreboot/+/69207/comment/989a0ca6_fe8b3ab0
PS1, Line 6: ../chip.h
> src/soc/intel/xeon_sp/cpx/chip.h or […]
Depends on which soc (cpx or skx) is defined in the .config, the appropriate chip.h is picked.
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Change subject: ec/starlabs/merlin: Add EC related files for Cezanne laptops
......................................................................
Patch Set 7: Code-Review+2
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Change subject: cpu/x86/topology: Add code to fill in topology on struct path
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
File src/cpu/x86/topology.c:
https://review.coreboot.org/c/coreboot/+/69222/comment/648d8568_46678071
PS1, Line 33: if (cpuid_max_func >= CPUID_EXTENDED_CPU_TOPOLOGY)
Should we print the failure and die() from the caller if CB_ERR is returned?
File src/include/cpu/x86/topology.h:
https://review.coreboot.org/c/coreboot/+/69222/comment/2bd74c00_32e4b512
PS1, Line 5:
It would be good to add a comment here to explain what this function does.
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