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[L] Change in coreboot[master]: soc/amd/*/data_fabric: Use common device ops
by Fred Reitberger (Code Review) 04 Nov '22

04 Nov '22

Fred Reitberger has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69174 ) Change subject: soc/amd/*/data_fabric: Use common device ops ...................................................................... soc/amd/*/data_fabric: Use common device ops Use the common device ops instead of an soc-specific device ops. TEST=builds for each soc Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I1804200c3c3f5ab492d237f4b03484c383862caf Reviewed-on: https://review.coreboot.org/c/coreboot/+/69174 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/chipset.cb D src/soc/amd/cezanne/data_fabric.c M src/soc/amd/glinda/Makefile.inc M src/soc/amd/glinda/chipset.cb D src/soc/amd/glinda/data_fabric.c M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb D src/soc/amd/mendocino/data_fabric.c M src/soc/amd/morgana/Makefile.inc M src/soc/amd/morgana/chipset.cb D src/soc/amd/morgana/data_fabric.c M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/chipset.cb D src/soc/amd/picasso/data_fabric.c 16 files changed, 65 insertions(+), 260 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index cdbbcfe..1f2bb6d 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -31,7 +31,6 @@ ramstage-y += agesa_acpi.c ramstage-y += chip.c ramstage-y += cpu.c -ramstage-y += data_fabric.c ramstage-y += fch.c ramstage-y += fsp_s_params.c ramstage-y += gpio.c diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb index 3b6e0d8..f0a3d86 100644 --- a/src/soc/amd/cezanne/chipset.cb +++ b/src/soc/amd/cezanne/chipset.cb @@ -97,14 +97,14 @@ device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function device pci 14.3 alias lpc_bridge on ops amd_lpc_ops end - device pci 18.0 alias data_fabric_0 on ops cezanne_data_fabric_ops end - device pci 18.1 alias data_fabric_1 on ops cezanne_data_fabric_ops end - device pci 18.2 alias data_fabric_2 on ops cezanne_data_fabric_ops end - device pci 18.3 alias data_fabric_3 on ops cezanne_data_fabric_ops end - device pci 18.4 alias data_fabric_4 on ops cezanne_data_fabric_ops end - device pci 18.5 alias data_fabric_5 on ops cezanne_data_fabric_ops end - device pci 18.6 alias data_fabric_6 on ops cezanne_data_fabric_ops end - device pci 18.7 alias data_fabric_7 on ops cezanne_data_fabric_ops end + device pci 18.0 alias data_fabric_0 on ops amd_data_fabric_ops end + device pci 18.1 alias data_fabric_1 on ops amd_data_fabric_ops end + device pci 18.2 alias data_fabric_2 on ops amd_data_fabric_ops end + device pci 18.3 alias data_fabric_3 on ops amd_data_fabric_ops end + device pci 18.4 alias data_fabric_4 on ops amd_data_fabric_ops end + device pci 18.5 alias data_fabric_5 on ops amd_data_fabric_ops end + device pci 18.6 alias data_fabric_6 on ops amd_data_fabric_ops end + device pci 18.7 alias data_fabric_7 on ops amd_data_fabric_ops end end device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end diff --git a/src/soc/amd/cezanne/data_fabric.c b/src/soc/amd/cezanne/data_fabric.c deleted file mode 100644 index 6a34a07..0000000 --- a/src/soc/amd/cezanne/data_fabric.c +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi_device.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> - -static const char *data_fabric_acpi_name(const struct device *dev) -{ - switch (dev->device) { - case PCI_DID_AMD_FAM17H_MODEL60H_DF0: - case PCI_DID_AMD_FAM19H_MODEL51H_DF0: - return "DFD0"; - case PCI_DID_AMD_FAM17H_MODEL60H_DF1: - case PCI_DID_AMD_FAM19H_MODEL51H_DF1: - return "DFD1"; - case PCI_DID_AMD_FAM17H_MODEL60H_DF2: - case PCI_DID_AMD_FAM19H_MODEL51H_DF2: - return "DFD2"; - case PCI_DID_AMD_FAM17H_MODEL60H_DF3: - case PCI_DID_AMD_FAM19H_MODEL51H_DF3: - return "DFD3"; - case PCI_DID_AMD_FAM17H_MODEL60H_DF4: - case PCI_DID_AMD_FAM19H_MODEL51H_DF4: - return "DFD4"; - case PCI_DID_AMD_FAM17H_MODEL60H_DF5: - case PCI_DID_AMD_FAM19H_MODEL51H_DF5: - return "DFD5"; - case PCI_DID_AMD_FAM17H_MODEL60H_DF6: - case PCI_DID_AMD_FAM19H_MODEL51H_DF6: - return "DFD6"; - case PCI_DID_AMD_FAM17H_MODEL60H_DF7: - case PCI_DID_AMD_FAM19H_MODEL51H_DF7: - return "DFD7"; - default: - printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, dev->device); - } - - return NULL; -} - -struct device_operations cezanne_data_fabric_ops = { - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, - .acpi_name = data_fabric_acpi_name, - .acpi_fill_ssdt = acpi_device_write_pci_dev, -}; diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index 2f5d9a9..e00421d 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -35,7 +35,6 @@ ramstage-y += agesa_acpi.c ramstage-y += chip.c ramstage-y += cpu.c -ramstage-y += data_fabric.c ramstage-y += fch.c ramstage-y += fsp_s_params.c ramstage-y += gpio.c diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb index 33bab512..3b095aa 100644 --- a/src/soc/amd/glinda/chipset.cb +++ b/src/soc/amd/glinda/chipset.cb @@ -76,14 +76,14 @@ device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function device pci 14.3 alias lpc_bridge on ops amd_lpc_ops end - device pci 18.0 alias data_fabric_0 on ops glinda_data_fabric_ops end - device pci 18.1 alias data_fabric_1 on ops glinda_data_fabric_ops end - device pci 18.2 alias data_fabric_2 on ops glinda_data_fabric_ops end - device pci 18.3 alias data_fabric_3 on ops glinda_data_fabric_ops end - device pci 18.4 alias data_fabric_4 on ops glinda_data_fabric_ops end - device pci 18.5 alias data_fabric_5 on ops glinda_data_fabric_ops end - device pci 18.6 alias data_fabric_6 on ops glinda_data_fabric_ops end - device pci 18.7 alias data_fabric_7 on ops glinda_data_fabric_ops end + device pci 18.0 alias data_fabric_0 on ops amd_data_fabric_ops end + device pci 18.1 alias data_fabric_1 on ops amd_data_fabric_ops end + device pci 18.2 alias data_fabric_2 on ops amd_data_fabric_ops end + device pci 18.3 alias data_fabric_3 on ops amd_data_fabric_ops end + device pci 18.4 alias data_fabric_4 on ops amd_data_fabric_ops end + device pci 18.5 alias data_fabric_5 on ops amd_data_fabric_ops end + device pci 18.6 alias data_fabric_6 on ops amd_data_fabric_ops end + device pci 18.7 alias data_fabric_7 on ops amd_data_fabric_ops end end device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end diff --git a/src/soc/amd/glinda/data_fabric.c b/src/soc/amd/glinda/data_fabric.c deleted file mode 100644 index 3bc0b6d..0000000 --- a/src/soc/amd/glinda/data_fabric.c +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Update for Glinda */ - -#include <acpi/acpi_device.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> - -static const char *data_fabric_acpi_name(const struct device *dev) -{ - switch (dev->device) { - case PCI_DID_AMD_FAM17H_MODELA0H_DF0: - return "DFD0"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF1: - return "DFD1"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF2: - return "DFD2"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF3: - return "DFD3"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF4: - return "DFD4"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF5: - return "DFD5"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF6: - return "DFD6"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF7: - return "DFD7"; - default: - printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, dev->device); - } - - return NULL; -} - -struct device_operations glinda_data_fabric_ops = { - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, - .acpi_name = data_fabric_acpi_name, - .acpi_fill_ssdt = acpi_device_write_pci_dev, -}; diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index 44a0e29..e1dda83 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -34,7 +34,6 @@ ramstage-y += agesa_acpi.c ramstage-y += chip.c ramstage-y += cpu.c -ramstage-y += data_fabric.c ramstage-y += fch.c ramstage-y += fsp_s_params.c ramstage-y += gpio.c diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index 23afdba..2900279 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -74,14 +74,14 @@ device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function device pci 14.3 alias lpc_bridge on ops amd_lpc_ops end - device pci 18.0 alias data_fabric_0 on ops mendocino_data_fabric_ops end - device pci 18.1 alias data_fabric_1 on ops mendocino_data_fabric_ops end - device pci 18.2 alias data_fabric_2 on ops mendocino_data_fabric_ops end - device pci 18.3 alias data_fabric_3 on ops mendocino_data_fabric_ops end - device pci 18.4 alias data_fabric_4 on ops mendocino_data_fabric_ops end - device pci 18.5 alias data_fabric_5 on ops mendocino_data_fabric_ops end - device pci 18.6 alias data_fabric_6 on ops mendocino_data_fabric_ops end - device pci 18.7 alias data_fabric_7 on ops mendocino_data_fabric_ops end + device pci 18.0 alias data_fabric_0 on ops amd_data_fabric_ops end + device pci 18.1 alias data_fabric_1 on ops amd_data_fabric_ops end + device pci 18.2 alias data_fabric_2 on ops amd_data_fabric_ops end + device pci 18.3 alias data_fabric_3 on ops amd_data_fabric_ops end + device pci 18.4 alias data_fabric_4 on ops amd_data_fabric_ops end + device pci 18.5 alias data_fabric_5 on ops amd_data_fabric_ops end + device pci 18.6 alias data_fabric_6 on ops amd_data_fabric_ops end + device pci 18.7 alias data_fabric_7 on ops amd_data_fabric_ops end end device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb index 23afdba..2900279 100644 --- a/src/soc/amd/mendocino/chipset_rembrandt.cb +++ b/src/soc/amd/mendocino/chipset_rembrandt.cb @@ -74,14 +74,14 @@ device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function device pci 14.3 alias lpc_bridge on ops amd_lpc_ops end - device pci 18.0 alias data_fabric_0 on ops mendocino_data_fabric_ops end - device pci 18.1 alias data_fabric_1 on ops mendocino_data_fabric_ops end - device pci 18.2 alias data_fabric_2 on ops mendocino_data_fabric_ops end - device pci 18.3 alias data_fabric_3 on ops mendocino_data_fabric_ops end - device pci 18.4 alias data_fabric_4 on ops mendocino_data_fabric_ops end - device pci 18.5 alias data_fabric_5 on ops mendocino_data_fabric_ops end - device pci 18.6 alias data_fabric_6 on ops mendocino_data_fabric_ops end - device pci 18.7 alias data_fabric_7 on ops mendocino_data_fabric_ops end + device pci 18.0 alias data_fabric_0 on ops amd_data_fabric_ops end + device pci 18.1 alias data_fabric_1 on ops amd_data_fabric_ops end + device pci 18.2 alias data_fabric_2 on ops amd_data_fabric_ops end + device pci 18.3 alias data_fabric_3 on ops amd_data_fabric_ops end + device pci 18.4 alias data_fabric_4 on ops amd_data_fabric_ops end + device pci 18.5 alias data_fabric_5 on ops amd_data_fabric_ops end + device pci 18.6 alias data_fabric_6 on ops amd_data_fabric_ops end + device pci 18.7 alias data_fabric_7 on ops amd_data_fabric_ops end end device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end diff --git a/src/soc/amd/mendocino/data_fabric.c b/src/soc/amd/mendocino/data_fabric.c deleted file mode 100644 index e0942f2..0000000 --- a/src/soc/amd/mendocino/data_fabric.c +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi_device.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <soc/pci_devs.h> - -static const char *data_fabric_acpi_name(const struct device *dev) -{ - const char *df_acpi_names[8] = { - "DFD0", - "DFD1", - "DFD2", - "DFD3", - "DFD4", - "DFD5", - "DFD6", - "DFD7" - }; - - if (dev->path.type == DEVICE_PATH_PCI && - PCI_SLOT(dev->path.pci.devfn) == DF_DEV) - return df_acpi_names[PCI_FUNC(dev->path.pci.devfn)]; - - printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, dev->device); - return NULL; -} - -struct device_operations mendocino_data_fabric_ops = { - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, - .acpi_name = data_fabric_acpi_name, - .acpi_fill_ssdt = acpi_device_write_pci_dev, -}; diff --git a/src/soc/amd/morgana/Makefile.inc b/src/soc/amd/morgana/Makefile.inc index a0065b8..a88e1a5 100644 --- a/src/soc/amd/morgana/Makefile.inc +++ b/src/soc/amd/morgana/Makefile.inc @@ -35,7 +35,6 @@ ramstage-y += agesa_acpi.c ramstage-y += chip.c ramstage-y += cpu.c -ramstage-y += data_fabric.c ramstage-y += fch.c ramstage-y += fsp_s_params.c ramstage-y += gpio.c diff --git a/src/soc/amd/morgana/chipset.cb b/src/soc/amd/morgana/chipset.cb index ffea57d..9b8d446 100644 --- a/src/soc/amd/morgana/chipset.cb +++ b/src/soc/amd/morgana/chipset.cb @@ -76,14 +76,14 @@ device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function device pci 14.3 alias lpc_bridge on ops amd_lpc_ops end - device pci 18.0 alias data_fabric_0 on ops morgana_data_fabric_ops end - device pci 18.1 alias data_fabric_1 on ops morgana_data_fabric_ops end - device pci 18.2 alias data_fabric_2 on ops morgana_data_fabric_ops end - device pci 18.3 alias data_fabric_3 on ops morgana_data_fabric_ops end - device pci 18.4 alias data_fabric_4 on ops morgana_data_fabric_ops end - device pci 18.5 alias data_fabric_5 on ops morgana_data_fabric_ops end - device pci 18.6 alias data_fabric_6 on ops morgana_data_fabric_ops end - device pci 18.7 alias data_fabric_7 on ops morgana_data_fabric_ops end + device pci 18.0 alias data_fabric_0 on ops amd_data_fabric_ops end + device pci 18.1 alias data_fabric_1 on ops amd_data_fabric_ops end + device pci 18.2 alias data_fabric_2 on ops amd_data_fabric_ops end + device pci 18.3 alias data_fabric_3 on ops amd_data_fabric_ops end + device pci 18.4 alias data_fabric_4 on ops amd_data_fabric_ops end + device pci 18.5 alias data_fabric_5 on ops amd_data_fabric_ops end + device pci 18.6 alias data_fabric_6 on ops amd_data_fabric_ops end + device pci 18.7 alias data_fabric_7 on ops amd_data_fabric_ops end end device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end diff --git a/src/soc/amd/morgana/data_fabric.c b/src/soc/amd/morgana/data_fabric.c deleted file mode 100644 index 6c02d21..0000000 --- a/src/soc/amd/morgana/data_fabric.c +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Update for Morgana */ - -#include <acpi/acpi_device.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> - -static const char *data_fabric_acpi_name(const struct device *dev) -{ - switch (dev->device) { - case PCI_DID_AMD_FAM17H_MODELA0H_DF0: - return "DFD0"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF1: - return "DFD1"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF2: - return "DFD2"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF3: - return "DFD3"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF4: - return "DFD4"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF5: - return "DFD5"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF6: - return "DFD6"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF7: - return "DFD7"; - default: - printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, dev->device); - } - - return NULL; -} - -struct device_operations morgana_data_fabric_ops = { - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, - .acpi_name = data_fabric_acpi_name, - .acpi_fill_ssdt = acpi_device_write_pci_dev, -}; diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 397c54d..ab18e3b 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -31,7 +31,6 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c ramstage-y += chip.c ramstage-y += cpu.c -ramstage-y += data_fabric.c ramstage-y += fch.c ramstage-y += fsp_s_params.c ramstage-y += gpio.c diff --git a/src/soc/amd/picasso/chipset.cb b/src/soc/amd/picasso/chipset.cb index e44ca8d..99b025e 100644 --- a/src/soc/amd/picasso/chipset.cb +++ b/src/soc/amd/picasso/chipset.cb @@ -37,14 +37,14 @@ device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function device pci 14.3 alias lpc_bridge on ops amd_lpc_ops end device pci 14.6 alias sdhci off end - device pci 18.0 alias data_fabric_0 on ops picasso_data_fabric_ops end - device pci 18.1 alias data_fabric_1 on ops picasso_data_fabric_ops end - device pci 18.2 alias data_fabric_2 on ops picasso_data_fabric_ops end - device pci 18.3 alias data_fabric_3 on ops picasso_data_fabric_ops end - device pci 18.4 alias data_fabric_4 on ops picasso_data_fabric_ops end - device pci 18.5 alias data_fabric_5 on ops picasso_data_fabric_ops end - device pci 18.6 alias data_fabric_6 on ops picasso_data_fabric_ops end - device pci 18.7 alias data_fabric_7 on ops picasso_data_fabric_ops end + device pci 18.0 alias data_fabric_0 on ops amd_data_fabric_ops end + device pci 18.1 alias data_fabric_1 on ops amd_data_fabric_ops end + device pci 18.2 alias data_fabric_2 on ops amd_data_fabric_ops end + device pci 18.3 alias data_fabric_3 on ops amd_data_fabric_ops end + device pci 18.4 alias data_fabric_4 on ops amd_data_fabric_ops end + device pci 18.5 alias data_fabric_5 on ops amd_data_fabric_ops end + device pci 18.6 alias data_fabric_6 on ops amd_data_fabric_ops end + device pci 18.7 alias data_fabric_7 on ops amd_data_fabric_ops end end device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end diff --git a/src/soc/amd/picasso/data_fabric.c b/src/soc/amd/picasso/data_fabric.c deleted file mode 100644 index a251158..0000000 --- a/src/soc/amd/picasso/data_fabric.c +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi_device.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> - -static const char *data_fabric_acpi_name(const struct device *dev) -{ - switch (dev->device) { - case PCI_DID_AMD_FAM17H_MODEL18H_DF0: - return "DFD0"; - case PCI_DID_AMD_FAM17H_MODEL18H_DF1: - return "DFD1"; - case PCI_DID_AMD_FAM17H_MODEL18H_DF2: - return "DFD2"; - case PCI_DID_AMD_FAM17H_MODEL18H_DF3: - return "DFD3"; - case PCI_DID_AMD_FAM17H_MODEL18H_DF4: - return "DFD4"; - case PCI_DID_AMD_FAM17H_MODEL18H_DF5: - return "DFD5"; - case PCI_DID_AMD_FAM17H_MODEL18H_DF6: - return "DFD6"; - case PCI_DID_AMD_FAM17H_MODEL18H_DF7: - return "DFD7"; - default: - printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, dev->device); - } - - return NULL; -} - -struct device_operations picasso_data_fabric_ops = { - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, - .acpi_name = data_fabric_acpi_name, - .acpi_fill_ssdt = acpi_device_write_pci_dev, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/69174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1804200c3c3f5ab492d237f4b03484c383862caf Gerrit-Change-Number: 69174 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/common/data_fabric: Make common device ops
by Fred Reitberger (Code Review) 04 Nov '22

04 Nov '22

Fred Reitberger has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69173 ) Change subject: soc/amd/common/data_fabric: Make common device ops ...................................................................... soc/amd/common/data_fabric: Make common device ops Add the generic data_fabric_acpi_name function and device ops to common code. Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I12053389a12081ddd81912a647bb532b31062093 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69173 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/data_fabric/data_fabric_helper.c 1 file changed, 45 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c index 181c71e..412daae 100644 --- a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c +++ b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_device.h> #include <amdblocks/data_fabric.h> #include <amdblocks/pci_devs.h> #include <arch/hpet.h> @@ -169,3 +170,31 @@ data_fabric_print_mmio_conf(); } + +static const char *data_fabric_acpi_name(const struct device *dev) +{ + const char *df_acpi_names[8] = { + "DFD0", + "DFD1", + "DFD2", + "DFD3", + "DFD4", + "DFD5", + "DFD6", + "DFD7" + }; + + if (dev->path.type == DEVICE_PATH_PCI && + PCI_SLOT(dev->path.pci.devfn) == DF_DEV) + return df_acpi_names[PCI_FUNC(dev->path.pci.devfn)]; + + printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, dev->device); + return NULL; +} + +struct device_operations amd_data_fabric_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = data_fabric_acpi_name, + .acpi_fill_ssdt = acpi_device_write_pci_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/69173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12053389a12081ddd81912a647bb532b31062093 Gerrit-Change-Number: 69173 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/mendocino/data_fabric.c: Make function more generic
by Fred Reitberger (Code Review) 04 Nov '22

04 Nov '22

Fred Reitberger has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69172 ) Change subject: soc/amd/mendocino/data_fabric.c: Make function more generic ...................................................................... soc/amd/mendocino/data_fabric.c: Make function more generic Make the data_fabric_acpi_name function more generic, in preparation to move it to common. TEST=build chausie, dump ACPI tables, and inspect DFD0 to DFD7 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I77140d8d0d6bf3e048b737de03d18142a6e23c1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69172 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/mendocino/data_fabric.c 1 file changed, 34 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/mendocino/data_fabric.c b/src/soc/amd/mendocino/data_fabric.c index 2569da8..e0942f2 100644 --- a/src/soc/amd/mendocino/data_fabric.c +++ b/src/soc/amd/mendocino/data_fabric.c @@ -4,31 +4,26 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> +#include <soc/pci_devs.h> static const char *data_fabric_acpi_name(const struct device *dev) { - switch (dev->device) { - case PCI_DID_AMD_FAM17H_MODELA0H_DF0: - return "DFD0"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF1: - return "DFD1"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF2: - return "DFD2"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF3: - return "DFD3"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF4: - return "DFD4"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF5: - return "DFD5"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF6: - return "DFD6"; - case PCI_DID_AMD_FAM17H_MODELA0H_DF7: - return "DFD7"; - default: - printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, dev->device); - } + const char *df_acpi_names[8] = { + "DFD0", + "DFD1", + "DFD2", + "DFD3", + "DFD4", + "DFD5", + "DFD6", + "DFD7" + }; + if (dev->path.type == DEVICE_PATH_PCI && + PCI_SLOT(dev->path.pci.devfn) == DF_DEV) + return df_acpi_names[PCI_FUNC(dev->path.pci.devfn)]; + + printk(BIOS_ERR, "%s: Unhandled device id 0x%x\n", __func__, dev->device); return NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/69172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77140d8d0d6bf3e048b737de03d18142a6e23c1d Gerrit-Change-Number: 69172 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/reef: Fix guarding of reading SKU from VPD
by Angel Pons (Code Review) 04 Nov '22

04 Nov '22

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68753 ) Change subject: mb/google/reef: Fix guarding of reading SKU from VPD ...................................................................... mb/google/reef: Fix guarding of reading SKU from VPD VPD read depends on CONFIG(VPD), not CONFIG(CHROMEOS). TEST=build/boot snappy, verify SKU set properly in SMBIOS Change-Id: I8aa57f793bd04dbe31f3b49bbff23e05c96592a6 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68753 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/reef/variants/snappy/mainboard.c 1 file changed, 18 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/reef/variants/snappy/mainboard.c b/src/mainboard/google/reef/variants/snappy/mainboard.c index fc0652c..0b15505 100644 --- a/src/mainboard/google/reef/variants/snappy/mainboard.c +++ b/src/mainboard/google/reef/variants/snappy/mainboard.c @@ -43,7 +43,7 @@ board_sku_num = sku_strapping_value(); - if (!CONFIG(CHROMEOS)) + if (!CONFIG(VPD)) return board_sku_num; if (!vpd_gets(vpd_skuid, vpd_buffer, ARRAY_SIZE(vpd_buffer), VPD_RO_THEN_RW)) -- To view, visit https://review.coreboot.org/c/coreboot/+/68753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8aa57f793bd04dbe31f3b49bbff23e05c96592a6 Gerrit-Change-Number: 68753 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/reef: Fix guarding of reading SKU from VPD
by Angel Pons (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Matt DeVillier. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68753 ) Change subject: mb/google/reef: Fix guarding of reading SKU from VPD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8aa57f793bd04dbe31f3b49bbff23e05c96592a6 Gerrit-Change-Number: 68753 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 20:37:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/*/data_fabric: Move register offsets to soc
by Fred Reitberger (Code Review) 04 Nov '22

04 Nov '22

Fred Reitberger has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69074 ) Change subject: soc/amd/*/data_fabric: Move register offsets to soc ...................................................................... soc/amd/*/data_fabric: Move register offsets to soc Morgana/Glinda have a different register mapping for data fabric access, although the registers themselves are mostly compatible. The register layouts defined by each soc capture the differences and the common code can use those. Move the register offsets to soc headers and update the offsets for morgana/glinda per morgana ppr #57396, rev 1.52 and glinda ppr #57254, rev 1.51 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I9e5e7c85f99a9afa873764ade9734831fb5cfe69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69074 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/include/soc/data_fabric.h D src/soc/amd/common/block/data_fabric/data_fabric_def.h M src/soc/amd/common/block/data_fabric/data_fabric_helper.c M src/soc/amd/common/block/include/amdblocks/data_fabric.h M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/include/soc/data_fabric.h M src/soc/amd/mendocino/include/soc/data_fabric.h M src/soc/amd/morgana/Kconfig M src/soc/amd/morgana/include/soc/data_fabric.h M src/soc/amd/picasso/include/soc/data_fabric.h 10 files changed, 68 insertions(+), 47 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/cezanne/include/soc/data_fabric.h b/src/soc/amd/cezanne/include/soc/data_fabric.h index 0a89971..a1f8b70 100644 --- a/src/soc/amd/cezanne/include/soc/data_fabric.h +++ b/src/soc/amd/cezanne/include/soc/data_fabric.h @@ -5,8 +5,15 @@ #include <types.h> -/* SoC-specific bits in D18F0_MMIO_CTRL0 */ -#define DF_MMIO_NP BIT(16) +/* D18F0 - Fabric Configuration registers */ +#define D18F0_MMIO_BASE0 0x200 +#define D18F0_MMIO_LIMIT0 0x204 +#define D18F0_MMIO_SHIFT 16 +#define D18F0_MMIO_CTRL0 0x208 + +#define DF_FICAA_BIOS 0x5C +#define DF_FICAD_LO 0x98 +#define DF_FICAD_HI 0x9C #define IOMS0_FABRIC_ID 10 diff --git a/src/soc/amd/common/block/data_fabric/data_fabric_def.h b/src/soc/amd/common/block/data_fabric/data_fabric_def.h deleted file mode 100644 index 2076d16..0000000 --- a/src/soc/amd/common/block/data_fabric/data_fabric_def.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef AMD_BLOCK_DATA_FABRIC_DEF_H -#define AMD_BLOCK_DATA_FABRIC_DEF_H - -#define DF_FICAA_BIOS 0x5C -#define DF_FICAD_LO 0x98 -#define DF_FICAD_HI 0x9C - -#define DF_IND_CFG_INST_ACC_EN (1 << 0) -#define DF_IND_CFG_ACC_REG_SHIFT 2 -#define DF_IND_CFG_ACC_REG_MASK (0x1ff << DF_IND_CFG_ACC_REG_SHIFT) -#define DF_IND_CFG_ACC_FUN_SHIFT 11 -#define DF_IND_CFG_ACC_FUN_MASK (0x7 << DF_IND_CFG_ACC_FUN_SHIFT) -#define DF_IND_CFG_64B_EN_SHIFT 14 -#define DF_IND_CFG_64B_EN (0x1 << DF_IND_CFG_64B_EN_SHIFT) -#define DF_IND_CFG_INST_ID_SHIFT 16 -#define DF_IND_CFG_INST_ID_MASK (0xff << DF_IND_CFG_INST_ID_SHIFT) - -#endif /* AMD_BLOCK_DATA_FABRIC_DEF_H */ diff --git a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c index 5a40ba5..181c71e 100644 --- a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c +++ b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c @@ -9,7 +9,6 @@ #include <soc/data_fabric.h> #include <soc/pci_devs.h> #include <types.h> -#include "data_fabric_def.h" static void data_fabric_set_indirect_address(uint8_t func, uint16_t reg, uint8_t instance_id) { diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h index 5cc7f48..4f8dcd4 100644 --- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h +++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h @@ -5,21 +5,12 @@ #include <amdblocks/pci_devs.h> #include <device/pci_ops.h> +#include <soc/data_fabric.h> #include <soc/pci_devs.h> #include <stdint.h> #define BROADCAST_FABRIC_ID 0xff -/* D18F0 - Fabric Configuration registers */ -#define D18F0_MMIO_BASE0 0x200 -#define D18F0_MMIO_LIMIT0 0x204 -#define D18F0_MMIO_SHIFT 16 -#define D18F0_MMIO_CTRL0 0x208 -/* The MMIO_NP bit is SoC-specific */ -#define DF_MMIO_DST_FABRIC_ID_SHIFT 4 -#define DF_MMIO_WE BIT(1) -#define DF_MMIO_RE BIT(0) - /* The number of data fabric MMIO registers is SoC-specific */ #define NB_MMIO_BASE(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_BASE0) #define NB_MMIO_LIMIT(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_LIMIT0) diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 9e99099..6c09ac9 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -54,7 +54,7 @@ select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_APOB_HASH # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_DATA_FABRIC # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_EMMC # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct diff --git a/src/soc/amd/glinda/include/soc/data_fabric.h b/src/soc/amd/glinda/include/soc/data_fabric.h index 32cbd20..7be4b15 100644 --- a/src/soc/amd/glinda/include/soc/data_fabric.h +++ b/src/soc/amd/glinda/include/soc/data_fabric.h @@ -1,14 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Glinda */ - #ifndef AMD_GLINDA_DATA_FABRIC_H #define AMD_GLINDA_DATA_FABRIC_H #include <types.h> -/* SoC-specific bits in D18F0_MMIO_CTRL0 */ -#define DF_MMIO_NP BIT(3) +/* D18F0 - Fabric Configuration registers */ +#define D18F0_MMIO_BASE0 0xD80 +#define D18F0_MMIO_LIMIT0 0xD84 +#define D18F0_MMIO_SHIFT 16 +#define D18F0_MMIO_CTRL0 0xD88 + +#define DF_FICAA_BIOS 0x8C +#define DF_FICAD_LO 0xB8 +#define DF_FICAD_HI 0xBC #define IOMS0_FABRIC_ID 15 diff --git a/src/soc/amd/mendocino/include/soc/data_fabric.h b/src/soc/amd/mendocino/include/soc/data_fabric.h index a1a1f4e..ae5f267 100644 --- a/src/soc/amd/mendocino/include/soc/data_fabric.h +++ b/src/soc/amd/mendocino/include/soc/data_fabric.h @@ -5,8 +5,15 @@ #include <types.h> -/* SoC-specific bits in D18F0_MMIO_CTRL0 */ -#define DF_MMIO_NP BIT(16) +/* D18F0 - Fabric Configuration registers */ +#define D18F0_MMIO_BASE0 0x200 +#define D18F0_MMIO_LIMIT0 0x204 +#define D18F0_MMIO_SHIFT 16 +#define D18F0_MMIO_CTRL0 0x208 + +#define DF_FICAA_BIOS 0x5C +#define DF_FICAD_LO 0x98 +#define DF_FICAD_HI 0x9C #define IOMS0_FABRIC_ID 9 diff --git a/src/soc/amd/morgana/Kconfig b/src/soc/amd/morgana/Kconfig index 814cb55..37d3613 100644 --- a/src/soc/amd/morgana/Kconfig +++ b/src/soc/amd/morgana/Kconfig @@ -54,7 +54,7 @@ select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_APOB_HASH # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_DATA_FABRIC # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_EMMC # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct diff --git a/src/soc/amd/morgana/include/soc/data_fabric.h b/src/soc/amd/morgana/include/soc/data_fabric.h index 203ca1c..46070f7 100644 --- a/src/soc/amd/morgana/include/soc/data_fabric.h +++ b/src/soc/amd/morgana/include/soc/data_fabric.h @@ -1,14 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Morgana */ - #ifndef AMD_MORGANA_DATA_FABRIC_H #define AMD_MORGANA_DATA_FABRIC_H #include <types.h> -/* SoC-specific bits in D18F0_MMIO_CTRL0 */ -#define DF_MMIO_NP BIT(3) +/* D18F0 - Fabric Configuration registers */ +#define D18F0_MMIO_BASE0 0xD80 +#define D18F0_MMIO_LIMIT0 0xD84 +#define D18F0_MMIO_SHIFT 16 +#define D18F0_MMIO_CTRL0 0xD88 + +#define DF_FICAA_BIOS 0x8C +#define DF_FICAD_LO 0xB8 +#define DF_FICAD_HI 0xBC #define IOMS0_FABRIC_ID 14 diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index f71abe0..dc77fee 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -6,9 +6,14 @@ #include <types.h> /* D18F0 - Fabric Configuration registers */ +#define D18F0_MMIO_BASE0 0x200 +#define D18F0_MMIO_LIMIT0 0x204 +#define D18F0_MMIO_SHIFT 16 +#define D18F0_MMIO_CTRL0 0x208 -/* SoC-specific bits in D18F0_MMIO_CTRL0 */ -#define DF_MMIO_NP BIT(12) +#define DF_FICAA_BIOS 0x5C +#define DF_FICAD_LO 0x98 +#define DF_FICAD_HI 0x9C #define IOMS0_FABRIC_ID 9 -- To view, visit https://review.coreboot.org/c/coreboot/+/69074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e5e7c85f99a9afa873764ade9734831fb5cfe69 Gerrit-Change-Number: 69074 Gerrit-PatchSet: 3 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/common/block/data_fabric: Use register bitslice structs
by Fred Reitberger (Code Review) 04 Nov '22

04 Nov '22

Fred Reitberger has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69073 ) Change subject: soc/amd/common/block/data_fabric: Use register bitslice structs ...................................................................... soc/amd/common/block/data_fabric: Use register bitslice structs Now that the socs have defined the DF FICAA and MMIO Control registers, update the common code to use them. Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: Ia5566f7af6cf5444fc8c627e004dd08185468c77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69073 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/data_fabric/data_fabric_helper.c 1 file changed, 35 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c index f1a067f..5a40ba5 100644 --- a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c +++ b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c @@ -13,14 +13,12 @@ static void data_fabric_set_indirect_address(uint8_t func, uint16_t reg, uint8_t instance_id) { - uint32_t fabric_indirect_access_reg = DF_IND_CFG_INST_ACC_EN; - /* Register offset field [10:2] in this register corresponds to [10:2] of the - requested offset. */ - fabric_indirect_access_reg |= reg & DF_IND_CFG_ACC_REG_MASK; - fabric_indirect_access_reg |= - (func << DF_IND_CFG_ACC_FUN_SHIFT) & DF_IND_CFG_ACC_FUN_MASK; - fabric_indirect_access_reg |= instance_id << DF_IND_CFG_INST_ID_SHIFT; - pci_write_config32(SOC_DF_F4_DEV, DF_FICAA_BIOS, fabric_indirect_access_reg); + union df_ficaa ficaa = { .cfg_inst_acc_en = 1 }; + /* convert register address to 32-bit register number */ + ficaa.reg_num = reg >> 2; + ficaa.func_num = func; + ficaa.inst_id = instance_id; + pci_write_config32(SOC_DF_F4_DEV, DF_FICAA_BIOS, ficaa.raw); } uint32_t data_fabric_read32(uint8_t function, uint16_t reg, uint8_t instance_id) @@ -64,16 +62,17 @@ void data_fabric_disable_mmio_reg(unsigned int reg) { - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), - IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT); + union df_mmio_control ctrl = { .fabric_id = IOMS0_FABRIC_ID }; + data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl.raw); data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), 0); data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), 0); } static bool is_mmio_reg_disabled(unsigned int reg) { - uint32_t val = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(reg)); - return !(val & (DF_MMIO_WE | DF_MMIO_RE)); + union df_mmio_control ctrl; + ctrl.raw = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(reg)); + return !(ctrl.we || ctrl.re); } int data_fabric_find_unused_mmio_reg(void) @@ -109,7 +108,8 @@ unsigned int i; int reg; - uint32_t base, limit, ctrl; + uint32_t base, limit; + union df_mmio_control ctrl; const uint32_t np_bot = HPET_BASE_ADDRESS >> D18F0_MMIO_SHIFT; const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> D18F0_MMIO_SHIFT; @@ -117,8 +117,8 @@ for (i = 0; i < NUM_NB_MMIO_REGS; i++) { /* Adjust all registers that overlap */ - ctrl = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); - if (!(ctrl & (DF_MMIO_WE | DF_MMIO_RE))) + ctrl.raw = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); + if (!(ctrl.we || ctrl.re)) continue; /* not enabled */ base = data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)); @@ -145,7 +145,7 @@ } data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_top + 1); data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), limit); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl); + data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), ctrl.raw); continue; } @@ -162,11 +162,11 @@ return; } + union df_mmio_control np_ctrl = { .fabric_id = IOMS0_FABRIC_ID, + .np = 1, .we = 1, .re = 1 }; data_fabric_broadcast_write32(0, NB_MMIO_BASE(reg), np_bot); data_fabric_broadcast_write32(0, NB_MMIO_LIMIT(reg), np_top); - data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), - (IOMS0_FABRIC_ID << DF_MMIO_DST_FABRIC_ID_SHIFT) | DF_MMIO_NP - | DF_MMIO_WE | DF_MMIO_RE); + data_fabric_broadcast_write32(0, NB_MMIO_CONTROL(reg), np_ctrl.raw); data_fabric_print_mmio_conf(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5566f7af6cf5444fc8c627e004dd08185468c77 Gerrit-Change-Number: 69073 Gerrit-PatchSet: 3 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/rex: Enable RFIM for CNVi
by Angel Pons (Code Review) 04 Nov '22

04 Nov '22

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67791 ) Change subject: mb/google/rex: Enable RFIM for CNVi ...................................................................... mb/google/rex: Enable RFIM for CNVi This patch enables the radio frequency interference mitigation for Rex. BUG=b:248391777 TEST=Booted to OS on Rex board. Verified RFIM DSM is presented to kernel through ACPI SSDT. Change-Id: I22f9861452c2c222dd7a33bfeb02c63b026bf2f7 Signed-off-by: zhaojohn <john.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67791 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/rex0/overridetree.cb 1 file changed, 23 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 7cf950e..00cbe8c 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -229,6 +229,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" register "is_untrusted" = "true" + register "enable_cnvi_ddr_rfim" = "true" device generic 0 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/67791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22f9861452c2c222dd7a33bfeb02c63b026bf2f7 Gerrit-Change-Number: 67791 Gerrit-PatchSet: 4 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/meteorlake: Provide mitigation support for CNVi RFI
by Angel Pons (Code Review) 04 Nov '22

04 Nov '22

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67789 ) Change subject: soc/intel/meteorlake: Provide mitigation support for CNVi RFI ...................................................................... soc/intel/meteorlake: Provide mitigation support for CNVi RFI The DDR RFIM is a frequency shifting RFI mitigation feature required by the Intel integrated Wi-Fi firmware(CNVi) for Meteor Lake. Please refer to Intel technical white paper 640438_Intel_DDR_Mem_RFIM_Policy_Enable once it is externally available. This change has backport changes from commit hash 6f73a20 (soc/intel/alderlake: Move CnviDdrRfim property to drivers) and provides the CNVi RFIM support for Meteor Lake. BUG=b:248391777 TEST=Booted to OS on Rex. Looked the DDR_DVFS_RFI_CONFIG_PCU_REG register at the offset 0x5A40 of Mchbar and verified the BIT0 (RFI_DISABLE bit) is 0. Change-Id: I87110bc10b98a27a8f274680597b15a1df488824 Signed-off-by: zhaojohn <john.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67789 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/meteorlake/romstage/fsp_params.c 1 file changed, 43 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 0ca3756..0b7e79e6 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -5,6 +5,7 @@ #include <cpu/intel/cpu_ids.h> #include <cpu/x86/msr.h> #include <device/device.h> +#include <drivers/wifi/generic/wifi.h> #include <fsp/fsp_debug_event.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> @@ -199,6 +200,19 @@ memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); } +static void fill_fspm_cnvi_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_meteorlake_config *config) +{ + /* CNVi DDR RFI Mitigation */ + const struct device_path path[] = { + { .type = DEVICE_PATH_PCI, .pci.devfn = PCI_DEVFN_CNVI_WIFI }, + { .type = DEVICE_PATH_GENERIC, .generic.id = 0 } }; + const struct device *dev = find_dev_nested_path(pci_root_bus(), path, + ARRAY_SIZE(path)); + if (is_dev_enabled(dev)) + m_cfg->CnviDdrRfim = wifi_generic_cnvi_ddr_rfim_enabled(dev); +} + static void fill_fspm_ish_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_meteorlake_config *config) { @@ -281,6 +295,7 @@ fill_fspm_smbus_params, fill_fspm_misc_params, fill_fspm_audio_params, + fill_fspm_cnvi_params, fill_fspm_pcie_rp_params, fill_fspm_ish_params, fill_fspm_tcss_params, -- To view, visit https://review.coreboot.org/c/coreboot/+/67789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87110bc10b98a27a8f274680597b15a1df488824 Gerrit-Change-Number: 67789 Gerrit-PatchSet: 11 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/meteorlake: Provide mitigation support for CNVi RFI
by Angel Pons (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Tarun Tuli, John Zhao, Kapil Porwal, Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67789 ) Change subject: soc/intel/meteorlake: Provide mitigation support for CNVi RFI ...................................................................... Patch Set 10: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/67789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87110bc10b98a27a8f274680597b15a1df488824 Gerrit-Change-Number: 67789 Gerrit-PatchSet: 10 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 20:35:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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