coreboot-gerrit November 2022

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[S] Change in coreboot[master]: configs: Rename saved configs as config.vendor_board.description
by Martin L Roth (Code Review) 04 Nov '22

04 Nov '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69213 ) Change subject: configs: Rename saved configs as config.vendor_board.description ...................................................................... configs: Rename saved configs as config.vendor_board.description There were numerous configs which were not saved in the correct format for the config to be found by the build system. Rename all of the boards to the correct format. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I008610ff87b3dd6c4b6c6b04fbdbc30a18ba776b --- R configs/config.asus_p2b.ramdebug R configs/config.asus_p8x7x-series.p8z77-v_lx2_debug_smmstore_hotplug_yabel_em100 R configs/config.cavium_cn8100_sff_evb.bdk_verbose_fit_payload_support R configs/config.dell_snb_ivb_workstations.optiplex_9010_sff R configs/config.emulation_qemu-aarch64.fit_support_timestamps R configs/config.emulation_qemu-i440fx R configs/config.emulation_qemu-i440fx.asan R configs/config.emulation_qemu-i440fx.noserial R configs/config.emulation_qemu-i440fx.x86_64 R configs/config.emulation_qemu-power9 R configs/config.emulation_qemu-q35.smm_tseg R configs/config.emulation_qemu-riscv.rv64 D configs/config.emulation_qemu_x86_i440fx_debug R configs/config.foxconn_g41s-k.g41m R configs/config.google_beltino.panther.pch_serialio_uart R configs/config.google_gru.kevin_secdata_mock R configs/config.google_jecht.guado_pch_serialio_uart R configs/config.google_octopus.meep_cros R configs/config.google_octopus.spi_flash_console R configs/config.google_reef.cros R configs/config.hp_compaq_8200_elite_sff.pc.x86_64 R configs/config.intel_coffeelake_rvp.fsp_car R configs/config.intel_galileo.gen1 R configs/config.intel_galileo.gen2 R configs/config.intel_galileo.gen2_debug R configs/config.intel_galileo.gen2_fsp2.0 R configs/config.intel_galileo.gen2_sd R configs/config.intel_galileo.gen2_vboot R configs/config.lenovo_t400.vboot_and_debug R configs/config.lenovo_t420.static_option_table_no_mem_fuses R configs/config.lenovo_t430.all_debug_and_option_table R configs/config.lenovo_x201.all_debug_option_table_bt_on_wifi R configs/config.lenovo_x220.mrc_bin R configs/config.lenovo_x220.option_table_debug_tpm_extended_cbfs R configs/config.ocp_deltalake.cbnt R configs/config.pcengines_apu2.apu3 R configs/config.pcengines_apu2.apu4 R configs/config.pcengines_apu2.apu5 R configs/config.purism_librem_skl.librem15_v4.txt_build_test R configs/config.purism_librem_skl.librem15_v4_stm 40 files changed, 15 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/69213/1 diff --git a/configs/config.asus_p2b_ramdebug b/configs/config.asus_p2b.ramdebug similarity index 100% rename from configs/config.asus_p2b_ramdebug rename to configs/config.asus_p2b.ramdebug diff --git a/configs/config.asus_p8z77-v_lx2.debug_smmstore_hotplug_yabel_em100 b/configs/config.asus_p8x7x-series.p8z77-v_lx2_debug_smmstore_hotplug_yabel_em100 similarity index 100% rename from configs/config.asus_p8z77-v_lx2.debug_smmstore_hotplug_yabel_em100 rename to configs/config.asus_p8x7x-series.p8z77-v_lx2_debug_smmstore_hotplug_yabel_em100 diff --git a/configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support b/configs/config.cavium_cn8100_sff_evb.bdk_verbose_fit_payload_support similarity index 100% rename from configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support rename to configs/config.cavium_cn8100_sff_evb.bdk_verbose_fit_payload_support diff --git a/configs/config.dell_optiplex_9010_sff b/configs/config.dell_snb_ivb_workstations.optiplex_9010_sff similarity index 100% rename from configs/config.dell_optiplex_9010_sff rename to configs/config.dell_snb_ivb_workstations.optiplex_9010_sff diff --git a/configs/config.emulation_qemu_aarch64_fit_support_timestamps b/configs/config.emulation_qemu-aarch64.fit_support_timestamps similarity index 100% rename from configs/config.emulation_qemu_aarch64_fit_support_timestamps rename to configs/config.emulation_qemu-aarch64.fit_support_timestamps diff --git a/configs/config.emulation_qemu_x86_i440fx b/configs/config.emulation_qemu-i440fx similarity index 100% rename from configs/config.emulation_qemu_x86_i440fx rename to configs/config.emulation_qemu-i440fx diff --git a/configs/config.emulation_qemu_x86_i440fx_asan b/configs/config.emulation_qemu-i440fx.asan similarity index 100% rename from configs/config.emulation_qemu_x86_i440fx_asan rename to configs/config.emulation_qemu-i440fx.asan diff --git a/configs/config.emulation_qemu_x86_i440fx_noserial b/configs/config.emulation_qemu-i440fx.noserial similarity index 100% rename from configs/config.emulation_qemu_x86_i440fx_noserial rename to configs/config.emulation_qemu-i440fx.noserial diff --git a/configs/config.emulation_qemu_x86_i440fx_x86_64 b/configs/config.emulation_qemu-i440fx.x86_64 similarity index 100% rename from configs/config.emulation_qemu_x86_i440fx_x86_64 rename to configs/config.emulation_qemu-i440fx.x86_64 diff --git a/configs/config.emulation_qemu_power9 b/configs/config.emulation_qemu-power9 similarity index 100% rename from configs/config.emulation_qemu_power9 rename to configs/config.emulation_qemu-power9 diff --git a/configs/config.emulation_qemu_x86_q35_smm_tseg b/configs/config.emulation_qemu-q35.smm_tseg similarity index 100% rename from configs/config.emulation_qemu_x86_q35_smm_tseg rename to configs/config.emulation_qemu-q35.smm_tseg diff --git a/configs/config.emulation_qemu_riscv_rv64 b/configs/config.emulation_qemu-riscv.rv64 similarity index 100% rename from configs/config.emulation_qemu_riscv_rv64 rename to configs/config.emulation_qemu-riscv.rv64 diff --git a/configs/config.emulation_qemu_x86_i440fx_debug b/configs/config.emulation_qemu_x86_i440fx_debug deleted file mode 100644 index 3cff033..0000000 --- a/configs/config.emulation_qemu_x86_i440fx_debug +++ /dev/null @@ -1,11 +0,0 @@ -CONFIG_VENDOR_EMULATION=y -CONFIG_BOARD_EMULATION_QEMU_X86_I440FX=y -CONFIG_GDB_STUB=y -CONFIG_GDB_WAIT=y -CONFIG_FATAL_ASSERTS=y -CONFIG_DEBUG_CBFS=y -CONFIG_DEBUG_PIRQ=y -CONFIG_DEBUG_MALLOC=y -CONFIG_DEBUG_BOOT_STATE=y -CONFIG_DEBUG_ADA_CODE=y -CONFIG_CPU_QEMU_X86_PARALLEL_MP=y diff --git a/configs/config.foxconn_g41m b/configs/config.foxconn_g41s-k.g41m similarity index 100% rename from configs/config.foxconn_g41m rename to configs/config.foxconn_g41s-k.g41m diff --git a/configs/config.google_panther.pch_serialio_uart b/configs/config.google_beltino.panther.pch_serialio_uart similarity index 100% rename from configs/config.google_panther.pch_serialio_uart rename to configs/config.google_beltino.panther.pch_serialio_uart diff --git a/configs/config.google_kevin_secdata_mock b/configs/config.google_gru.kevin_secdata_mock similarity index 100% rename from configs/config.google_kevin_secdata_mock rename to configs/config.google_gru.kevin_secdata_mock diff --git a/configs/config.google_guado.pch_serialio_uart b/configs/config.google_jecht.guado_pch_serialio_uart similarity index 100% rename from configs/config.google_guado.pch_serialio_uart rename to configs/config.google_jecht.guado_pch_serialio_uart diff --git a/configs/config.google_meep_cros b/configs/config.google_octopus.meep_cros similarity index 100% rename from configs/config.google_meep_cros rename to configs/config.google_octopus.meep_cros diff --git a/configs/config.google_octopus_spi_flash_console b/configs/config.google_octopus.spi_flash_console similarity index 100% rename from configs/config.google_octopus_spi_flash_console rename to configs/config.google_octopus.spi_flash_console diff --git a/configs/config.google_reef_cros b/configs/config.google_reef.cros similarity index 100% rename from configs/config.google_reef_cros rename to configs/config.google_reef.cros diff --git a/configs/config.hp_compaq_8200_elite_sff_pc.x86_64 b/configs/config.hp_compaq_8200_elite_sff.pc.x86_64 similarity index 100% rename from configs/config.hp_compaq_8200_elite_sff_pc.x86_64 rename to configs/config.hp_compaq_8200_elite_sff.pc.x86_64 diff --git a/configs/config.intel_coffeelake_rvp11.fsp_car b/configs/config.intel_coffeelake_rvp.fsp_car similarity index 100% rename from configs/config.intel_coffeelake_rvp11.fsp_car rename to configs/config.intel_coffeelake_rvp.fsp_car diff --git a/configs/config.intel_galileo_gen1 b/configs/config.intel_galileo.gen1 similarity index 100% rename from configs/config.intel_galileo_gen1 rename to configs/config.intel_galileo.gen1 diff --git a/configs/config.intel_galileo_gen2 b/configs/config.intel_galileo.gen2 similarity index 100% rename from configs/config.intel_galileo_gen2 rename to configs/config.intel_galileo.gen2 diff --git a/configs/config.intel_galileo_gen2.debug b/configs/config.intel_galileo.gen2_debug similarity index 100% rename from configs/config.intel_galileo_gen2.debug rename to configs/config.intel_galileo.gen2_debug diff --git a/configs/config.intel_galileo_gen2.fsp2.0 b/configs/config.intel_galileo.gen2_fsp2.0 similarity index 100% rename from configs/config.intel_galileo_gen2.fsp2.0 rename to configs/config.intel_galileo.gen2_fsp2.0 diff --git a/configs/config.intel_galileo_gen2.sd b/configs/config.intel_galileo.gen2_sd similarity index 100% rename from configs/config.intel_galileo_gen2.sd rename to configs/config.intel_galileo.gen2_sd diff --git a/configs/config.intel_galileo_gen2.vboot b/configs/config.intel_galileo.gen2_vboot similarity index 100% rename from configs/config.intel_galileo_gen2.vboot rename to configs/config.intel_galileo.gen2_vboot diff --git a/configs/config.lenovo_t400_vboot_and_debug b/configs/config.lenovo_t400.vboot_and_debug similarity index 100% rename from configs/config.lenovo_t400_vboot_and_debug rename to configs/config.lenovo_t400.vboot_and_debug diff --git a/configs/config.lenovo_t420_static_option_table_no_mem_fuses b/configs/config.lenovo_t420.static_option_table_no_mem_fuses similarity index 100% rename from configs/config.lenovo_t420_static_option_table_no_mem_fuses rename to configs/config.lenovo_t420.static_option_table_no_mem_fuses diff --git a/configs/config.lenovo_thinkpad_t430_all_debug_and_option_table b/configs/config.lenovo_t430.all_debug_and_option_table similarity index 100% rename from configs/config.lenovo_thinkpad_t430_all_debug_and_option_table rename to configs/config.lenovo_t430.all_debug_and_option_table diff --git a/configs/config.lenovo_x201_all_debug_option_table_bt_on_wifi b/configs/config.lenovo_x201.all_debug_option_table_bt_on_wifi similarity index 100% rename from configs/config.lenovo_x201_all_debug_option_table_bt_on_wifi rename to configs/config.lenovo_x201.all_debug_option_table_bt_on_wifi diff --git a/configs/config.lenovo_x220_mrc_bin b/configs/config.lenovo_x220.mrc_bin similarity index 100% rename from configs/config.lenovo_x220_mrc_bin rename to configs/config.lenovo_x220.mrc_bin diff --git a/configs/config.lenovo_x220_option_table_debug_tpm_extended_cbfs b/configs/config.lenovo_x220.option_table_debug_tpm_extended_cbfs similarity index 100% rename from configs/config.lenovo_x220_option_table_debug_tpm_extended_cbfs rename to configs/config.lenovo_x220.option_table_debug_tpm_extended_cbfs diff --git a/configs/config.ocp_deltalake_cbnt b/configs/config.ocp_deltalake.cbnt similarity index 100% rename from configs/config.ocp_deltalake_cbnt rename to configs/config.ocp_deltalake.cbnt diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu2.apu3 similarity index 100% rename from configs/config.pcengines_apu3 rename to configs/config.pcengines_apu2.apu3 diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu2.apu4 similarity index 100% rename from configs/config.pcengines_apu4 rename to configs/config.pcengines_apu2.apu4 diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu2.apu5 similarity index 100% rename from configs/config.pcengines_apu5 rename to configs/config.pcengines_apu2.apu5 diff --git a/configs/config.purism_librem15_v4.txt_build_test b/configs/config.purism_librem_skl.librem15_v4.txt_build_test similarity index 100% rename from configs/config.purism_librem15_v4.txt_build_test rename to configs/config.purism_librem_skl.librem15_v4.txt_build_test diff --git a/configs/config.purism_librem15_v4_stm b/configs/config.purism_librem_skl.librem15_v4_stm similarity index 100% rename from configs/config.purism_librem15_v4_stm rename to configs/config.purism_librem_skl.librem15_v4_stm -- To view, visit https://review.coreboot.org/c/coreboot/+/69213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I008610ff87b3dd6c4b6c6b04fbdbc30a18ba776b Gerrit-Change-Number: 69213 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: drivers/amd & soc/amd: Define bootblock postcodes
by Martin L Roth (Code Review) 04 Nov '22

04 Nov '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69212 ) Change subject: drivers/amd & soc/amd: Define bootblock postcodes ...................................................................... drivers/amd & soc/amd: Define bootblock postcodes Postcodes 0x50 - 0x52 are used for bootblock functions. This change makes this standard across all AMD chips. - bootblock_c_entry: 0x50 - bootblock_soc_early_init: 0x51 - bootblock_soc_init: 0x52 Stoney was previously using 0x90 for bootblock_soc_early_init. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I7b5de5887d36072b94e05602f787668818fd0d99 --- M src/drivers/amd/agesa/bootblock.c M src/soc/amd/common/block/cpu/noncar/bootblock.c A src/soc/amd/common/block/include/amdblocks/post_codes.h M src/soc/amd/stoneyridge/bootblock.c 4 files changed, 77 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/69212/1 diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index df9876a..5acddfd 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -4,6 +4,7 @@ #include <halt.h> #include <amdblocks/amd_pci_mmconf.h> #include <amdblocks/biosram.h> +#include <amdblocks/post_codes.h> #include <arch/bootblock.h> #include <cpu/amd/msr.h> #include <cpu/x86/mtrr.h> @@ -20,11 +21,15 @@ void bootblock_soc_early_init(void) { + post_code(POST_SOC_AMD_BOOTBLOCK_INIT_EARLY); + bootblock_early_southbridge_init(); } asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_SOC_AMD_BOOTBLOCK_ENTRY); + enable_pci_mmconf(); set_early_mtrrs(); @@ -36,6 +41,8 @@ asmlinkage void ap_bootblock_c_entry(void) { + post_code(POST_SOC_AMD_BOOTBLOCK_ENTRY); + enable_pci_mmconf(); set_early_mtrrs(); diff --git a/src/soc/amd/common/block/cpu/noncar/bootblock.c b/src/soc/amd/common/block/cpu/noncar/bootblock.c index 13bac18..c76ebb3 100644 --- a/src/soc/amd/common/block/cpu/noncar/bootblock.c +++ b/src/soc/amd/common/block/cpu/noncar/bootblock.c @@ -2,6 +2,7 @@ #include <amdblocks/amd_pci_mmconf.h> #include <amdblocks/cpu.h> +#include <amdblocks/post_codes.h> #include <bootblock_common.h> #include <console/console.h> #include <cpu/cpu.h> @@ -12,6 +13,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_SOC_AMD_BOOTBLOCK_ENTRY); + early_cache_setup(); write_resume_eip(); enable_pci_mmconf(); @@ -34,12 +37,17 @@ void bootblock_soc_early_init(void) { + post_code(POST_SOC_AMD_BOOTBLOCK_INIT_EARLY); + fch_pre_init(); } void bootblock_soc_init(void) { - u32 val = cpuid_eax(1); + u32 val; + post_code(POST_SOC_AMD_BOOTBLOCK_INIT); + + val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { diff --git a/src/soc/amd/common/block/include/amdblocks/post_codes.h b/src/soc/amd/common/block/include/amdblocks/post_codes.h new file mode 100644 index 0000000..4537498 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/post_codes.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/** + * @file post_codes.h + */ + +/* + * The post codes 0x50-0x5f are reserved for use by SoCs. These values should + * not be used in other areas of coreboot, so should uniquely identify the SoC + * area. + * + * For AMD, we should unify the values between the various chips so that the + * same code means the same thing on each. + */ + +/** + * @brief Entering SoC bootblock + * + * coreboot entered the bootblock_c_entry function + */ + #define POST_SOC_AMD_BOOTBLOCK_ENTRY 0x50 + +/** + * @brief Entering SoC early init code + * + * coreboot entered the bootblock_soc_early_init function + */ + #define POST_SOC_AMD_BOOTBLOCK_INIT_EARLY 0x51 + + /** + * @brief Entered SoC bootblock init code + * + * coreboot entered the bootblock_soc_init function + */ + #define POST_SOC_AMD_BOOTBLOCK_INIT 0x52 diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c index 0a67d9b..79b8945 100644 --- a/src/soc/amd/stoneyridge/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock.c @@ -13,6 +13,7 @@ #include <amdblocks/amd_pci_mmconf.h> #include <amdblocks/biosram.h> #include <amdblocks/iomap.h> +#include <amdblocks/post_codes.h> #include <soc/pci_devs.h> #include <soc/cpu.h> #include <soc/southbridge.h> @@ -57,6 +58,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_SOC_AMD_BOOTBLOCK_ENTRY); + enable_pci_mmconf(); amd_initmmio(); /* @@ -76,12 +79,15 @@ void bootblock_soc_early_init(void) { + post_code(POST_SOC_AMD_BOOTBLOCK_INIT_EARLY); + bootblock_fch_early_init(); - post_code(0x90); } void bootblock_soc_init(void) { + post_code(POST_SOC_AMD_BOOTBLOCK_INIT); + if (CONFIG(AMD_SOC_CONSOLE_UART)) assert(CONFIG_UART_FOR_CONSOLE >= 0 && CONFIG_UART_FOR_CONSOLE <= 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/69212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b5de5887d36072b94e05602f787668818fd0d99 Gerrit-Change-Number: 69212 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/sifive/ux00ddr.h: Remove set but unused variables
by build bot (Jenkins) (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans, Philipp Hug, ron minnich, Elyes Haouas. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63074 ) Change subject: soc/sifive/ux00ddr.h: Remove set but unused variables ...................................................................... Patch Set 19: (4 comments) File src/soc/sifive/fu540/ux00ddr.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162514): https://review.coreboot.org/c/coreboot/+/63074/comment/02aff3ae_620e2cbe PS19, Line 179: /* char slicelsc = '0'; */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162514): https://review.coreboot.org/c/coreboot/+/63074/comment/9e721d66_bad140b7 PS19, Line 180: /* char slicemsc = '0'; */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162514): https://review.coreboot.org/c/coreboot/+/63074/comment/4130f760_b78b11a6 PS19, Line 181: /* slicelsc += (dq % 10); */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162514): https://review.coreboot.org/c/coreboot/+/63074/comment/ed2024f9_a5455512 PS19, Line 182: /* slicemsc += (dq / 10); */ code indent should use tabs where possible -- To view, visit https://review.coreboot.org/c/coreboot/+/63074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I442a42e297f2968dd2c824a93a9a1e2bc74ea2f4 Gerrit-Change-Number: 63074 Gerrit-PatchSet: 19 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 04 Nov 2022 22:04:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: security/vboot: Update build rules using x86 SHA extension
by Karthik Ramasubramanian (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Julius Werner, Karthik Ramasubramanian. Hello build bot (Jenkins), Raul Rangel, Kangheui Won, Julius Werner, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68953 to look at the new patch set (#4). Change subject: security/vboot: Update build rules using x86 SHA extension ...................................................................... security/vboot: Update build rules using x86 SHA extension Currently build rules allow using x86 SHA extensions for all coreboot stages when enabled. On some SoCs where verstage can run in non-x86 environment, x86 SHA extension cannot be used. Update build rules accordingly such that x86 SHA extensions can be used in AMD SoCs. This is particularly useful when CBFS verificiation is enabled which verifies the hash of the CBFS file being loaded. BUG=b:227809919 TEST=Build and boot to OS in Skyrim. Observe that hardware acceleration is used when a CBFS file is loaded and observe an overall improvement of 10 ms. Change-Id: I4f388e963eb82990cda41d3880e66ad937334908 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/security/vboot/Makefile.inc 1 file changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/68953/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/68953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f388e963eb82990cda41d3880e66ad937334908 Gerrit-Change-Number: 68953 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: arch/x86/memmove: Add 64bit version
by Arthur Heymans (Code Review) 04 Nov '22

04 Nov '22

Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/69231 ) Change subject: arch/x86/memmove: Add 64bit version ...................................................................... arch/x86/memmove: Add 64bit version The 64bit handles 64bit input variables properly. TESTED: Both qemu and real hardware can use LZ4 properly which use this code Change-Id: Ib43ec19df97194d6b1c18bfacb5fe8211ba0ffe5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Makefile.inc A src/arch/x86/memmove_64.S 2 files changed, 224 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/69231/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib43ec19df97194d6b1c18bfacb5fe8211ba0ffe5 Gerrit-Change-Number: 69231 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/sifive/ux00ddr.h: Remove set but unused variables
by build bot (Jenkins) (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans, Philipp Hug, ron minnich, Elyes Haouas. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63074 ) Change subject: soc/sifive/ux00ddr.h: Remove set but unused variables ...................................................................... Patch Set 18: (4 comments) File src/soc/sifive/fu540/ux00ddr.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162501): https://review.coreboot.org/c/coreboot/+/63074/comment/d1d8a254_e532571b PS18, Line 179: /* char slicelsc = '0'; */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162501): https://review.coreboot.org/c/coreboot/+/63074/comment/ae6ff2d7_f6f1e677 PS18, Line 180: /* char slicemsc = '0'; */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162501): https://review.coreboot.org/c/coreboot/+/63074/comment/5ca99bc4_9c2b4b8e PS18, Line 181: /* slicelsc += (dq % 10); */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162501): https://review.coreboot.org/c/coreboot/+/63074/comment/0858fc7b_36ffdd22 PS18, Line 182: /* slicemsc += (dq / 10); */ code indent should use tabs where possible -- To view, visit https://review.coreboot.org/c/coreboot/+/63074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I442a42e297f2968dd2c824a93a9a1e2bc74ea2f4 Gerrit-Change-Number: 63074 Gerrit-PatchSet: 18 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 04 Nov 2022 21:44:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/xcompile: Fix building for clang + 64bit
by Arthur Heymans (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Martin L Roth. Hello Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69232 to look at the new patch set (#2). Change subject: util/xcompile: Fix building for clang + 64bit ...................................................................... util/xcompile: Fix building for clang + 64bit -malign-abi does not exist on clang and the -ccc-gcc-name variable is not needed anymore. TESTED: This also boots on qemu q35 Change-Id: I7f99ebea18d5c09fdc7ced5c793d57d6fedd2e47 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/xcompile/xcompile 1 file changed, 24 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/69232/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f99ebea18d5c09fdc7ced5c793d57d6fedd2e47 Gerrit-Change-Number: 69232 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: vendorcode/amd/ccx_cppc_data.h: Fix header guard
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69230 ) Change subject: vendorcode/amd/ccx_cppc_data.h: Fix header guard ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I027c3aa7bb206112107ee120cf6f9854e37c5636 Gerrit-Change-Number: 69230 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 04 Nov 2022 21:21:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/sifive/ux00ddr.h: Remove set but unused variables
by build bot (Jenkins) (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Arthur Heymans, Philipp Hug, ron minnich, Elyes Haouas. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63074 ) Change subject: soc/sifive/ux00ddr.h: Remove set but unused variables ...................................................................... Patch Set 17: (4 comments) File src/soc/sifive/fu540/ux00ddr.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162491): https://review.coreboot.org/c/coreboot/+/63074/comment/de27ba82_961015df PS17, Line 179: /* char slicelsc = '0'; */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162491): https://review.coreboot.org/c/coreboot/+/63074/comment/fd07cad6_adc3bd63 PS17, Line 180: /* char slicemsc = '0'; */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162491): https://review.coreboot.org/c/coreboot/+/63074/comment/ca27a890_d80d1d03 PS17, Line 181: /* slicelsc += (dq % 10); */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162491): https://review.coreboot.org/c/coreboot/+/63074/comment/4543a3c9_bd2024c6 PS17, Line 182: /* slicemsc += (dq / 10); */ code indent should use tabs where possible -- To view, visit https://review.coreboot.org/c/coreboot/+/63074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I442a42e297f2968dd2c824a93a9a1e2bc74ea2f4 Gerrit-Change-Number: 63074 Gerrit-PatchSet: 17 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 04 Nov 2022 21:17:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Remove PM Energy Report WA
by Ravishankar Sarawadi (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69042 ) Change subject: soc/intel/meteorlake: Remove PM Energy Report WA ...................................................................... Patch Set 4: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69042/comment/547c5300_db071472 PS1, Line 7: Enery > nit: `Energy` Done https://review.coreboot.org/c/coreboot/+/69042/comment/c106650e_39b65c98 PS1, Line 7: meterolake > nit: `meteorlake` Done https://review.coreboot.org/c/coreboot/+/69042/comment/046ed8a2_19dde74b PS1, Line 9: boottime > boot time Done https://review.coreboot.org/c/coreboot/+/69042/comment/ab8ad56d_19ae5031 PS1, Line 9: Pm > PM Done https://review.coreboot.org/c/coreboot/+/69042/comment/81ef6456_b9b0d389 PS1, Line 13: build/boot > Build and Boot Google, Rex and Intel, MTLRVP without any boot time regression. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5f1f9c6ab31652977d436a49a3531edffbd60c5 Gerrit-Change-Number: 69042 Gerrit-PatchSet: 4 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 21:09:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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