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Change subject: ec/clevo/it5570: Add Clevo EC implementation found on Clevo laptops
......................................................................
Patch Set 8: -Code-Review
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Change subject: mb/asus/p5qc: Add ASUS P5Q-E as a variant
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
> While I cannot say anything about the P5Q-E, this does not appear to negatively affect the P5Q.
It shouldn't even change the binary for the P5Q. You can try diffing the coreboot.rom built with `make BUILD_TIMELESS=1 -j` before and after this commit; it should be identical.
PS1:
Can't recall if this was ever tested.
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Change subject: gm45 boards: Drop unneeded MP table stuff
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/66611/comment/c124e3f4_c9fafd61
PS2, Line 8:
> Given Nico's confusion, I decided to write a sliiiiightly longer (only 3 paragraphs) commit message. […]
Done
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Change subject: soc/sifive/ux00ddr.h: Remove set but unused variables
......................................................................
Patch Set 16:
(4 comments)
File src/soc/sifive/fu540/ux00ddr.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162479):
https://review.coreboot.org/c/coreboot/+/63074/comment/bce6ee20_2cb66079
PS16, Line 179: /* char slicelsc = '0'; */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162479):
https://review.coreboot.org/c/coreboot/+/63074/comment/8ae2404f_e510c757
PS16, Line 180: /* char slicemsc = '0'; */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162479):
https://review.coreboot.org/c/coreboot/+/63074/comment/03f920da_84d4a687
PS16, Line 181: /* slicelsc += (dq % 10); */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162479):
https://review.coreboot.org/c/coreboot/+/63074/comment/e408e12c_3fcd9834
PS16, Line 182: /* slicemsc += (dq / 10); */
code indent should use tabs where possible
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Change subject: cpu/x86/smm/module_loader: Fix ASEG loading
......................................................................
Patch Set 2: Code-Review+1
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Change subject: mb/prodrive/hermes: Fix format mismatch
......................................................................
mb/prodrive/hermes: Fix format mismatch
Change-Id: I2a6947c1a39b115a7c7f5da1c9becfd51f45fad9
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/prodrive/hermes/eeprom.c
1 file changed, 11 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/69239/1
diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c
index 70a163f..c4a2695 100644
--- a/src/mainboard/prodrive/hermes/eeprom.c
+++ b/src/mainboard/prodrive/hermes/eeprom.c
@@ -65,7 +65,7 @@
if (crc != board_cfg->signature)
continue;
- printk(BIOS_DEBUG, "CFG EEPROM: Board settings CRC OK for %zu / %lu bytes\n",
+ printk(BIOS_DEBUG, "CFG EEPROM: Board settings CRC OK for %zu / %zu bytes\n",
len, sizeof(board_cfg->raw_settings));
return len;
}
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Change subject: soc/sifive/ux00ddr.h: Remove set but unused variables
......................................................................
Patch Set 15:
(4 comments)
File src/soc/sifive/fu540/ux00ddr.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162472):
https://review.coreboot.org/c/coreboot/+/63074/comment/f4b8a1e3_8bf101c0
PS15, Line 179: /* char slicelsc = '0'; */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162472):
https://review.coreboot.org/c/coreboot/+/63074/comment/1024eb7d_60fd94dc
PS15, Line 180: /* char slicemsc = '0'; */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162472):
https://review.coreboot.org/c/coreboot/+/63074/comment/5268fac5_6b7cd844
PS15, Line 181: /* slicelsc += (dq % 10); */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162472):
https://review.coreboot.org/c/coreboot/+/63074/comment/1315decc_2dd90ecb
PS15, Line 182: /* slicemsc += (dq / 10); */
code indent should use tabs where possible
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Change subject: cpu/x86/topology: Add code to fill in topology on struct path
......................................................................
Patch Set 1:
(1 comment)
File src/cpu/x86/topology.c:
https://review.coreboot.org/c/coreboot/+/69222/comment/4399bf03_6cd945e3
PS1, Line 33: if (cpuid_max_func >= CPUID_EXTENDED_CPU_TOPOLOGY)
> Should we print the failure and die() from the caller if CB_ERR is returned?
absolutely not :-) CPUs that don't implement this for sure exist. Then those CPU simply don't get their topology filled in, which is not a big problem since they tend to not feature thread. Even if those have threads then there is no regression as this currently does not exist.
I'll add a comment to the code to clarify this.
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