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Change subject: mb/google/rex: Add fingerprint SPI
......................................................................
Patch Set 18:
(8 comments)
This change is ready for review.
Commit Message:
https://review.coreboot.org/c/coreboot/+/66992/comment/6ad019ec_22522113
PS14, Line 10: CL:66915
> need to add the commit sha and title
Done
https://review.coreboot.org/c/coreboot/+/66992/comment/8efead9d_108c0ecb
PS14, Line 12: TEST=None yet. Awaiting Hardware
> do we have correct device now to test ?
Done
https://review.coreboot.org/c/coreboot/+/66992/comment/60448b51_95b7f168
PS14, Line 12: TEST=None yet. Awaiting Hardware
> do we have correct device now to test ?
Done
File src/mainboard/google/rex/variants/rex0/gpio.c:
https://review.coreboot.org/c/coreboot/+/66992/comment/5f9d2024_b6a836c2
PS14, Line 435: A20
> nit: please submit a separate CL to fix this typo
Ack
https://review.coreboot.org/c/coreboot/+/66992/comment/7eb49a5c_88257e1f
PS14, Line 387: PAD_CFG_GPO(GPP_B11, 1, DEEP),
> This was a copy paste over from Brya where we couldn't change bootblock anymore? This isn't directl […]
Done
https://review.coreboot.org/c/coreboot/+/66992/comment/9cdc9c3a_40fe5d05
PS14, Line 396: /* GPP_C23 : [] ==> FP_RST_ODL */
: PAD_CFG_GPO(GPP_C23, 0, DEEP),
> line number 444, already drove this signal low. […]
Done
https://review.coreboot.org/c/coreboot/+/66992/comment/f8160723_8fb37a2e
PS14, Line 439: /* GPP_B11 : [] ==> EN_FP_PWR */
: PAD_CFG_GPO(GPP_B11, 0, DEEP),
> do u know the default state of this signal ?
Not sure, but followed the same procedure as in https://review.coreboot.org/c/coreboot/+/66915 to keep it powered off till the kernel driver takes over to power sequence it.
https://review.coreboot.org/c/coreboot/+/66992/comment/3dabaef8_c6465912
PS14, Line 443:
> use tab
Done
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Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters
......................................................................
Patch Set 21:
(1 comment)
File src/soc/amd/mendocino/root_complex.c:
https://review.coreboot.org/c/coreboot/+/68649/comment/ab26a0bf_99728c3c
PS16, Line 393: #else
> I assume below behavior is your suggestion?
Yes, only tables B through F should be conditionally included by `#if (CONFIG(FEATURE_DYNAMIC_DPTC))`. All boards require normal and low/no battery modes to properly support that feature, so they must be included in every build.
It is a requirement that low/no battery boot is supported on all Skyrim devices/variants, so we can't exclude those tables if `FEATURE_DYNAMIC_DPTC` is enabled. We also do not want the default and low/now battery entries duplicated.
Since those tables are missing values that are required to use the same (expanded) macro, please work with AMD to determine what the missing values are. They may be the same values that are already defined for Table A, but that needs to be verified by AMD.
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Change subject: soc/sifive/ux00ddr.h: Remove set but unused variables
......................................................................
Patch Set 23: Verified-1
(4 comments)
File src/soc/sifive/fu540/ux00ddr.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162822):
https://review.coreboot.org/c/coreboot/+/63074/comment/4fb83407_c50245bf
PS23, Line 179: /* char slicelsc = '0'; */
code indent should use tabs where possible
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https://review.coreboot.org/c/coreboot/+/63074/comment/41a9f6b6_5a8348ec
PS23, Line 180: /* char slicemsc = '0'; */
code indent should use tabs where possible
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https://review.coreboot.org/c/coreboot/+/63074/comment/8cffa8fc_5c5c176b
PS23, Line 181: /* slicelsc += (dq % 10); */
code indent should use tabs where possible
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https://review.coreboot.org/c/coreboot/+/63074/comment/1d096c7f_115f0ba0
PS23, Line 182: /* slicemsc += (dq / 10); */
code indent should use tabs where possible
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Change subject: arch/x86/memmove: Add 64bit version
......................................................................
Patch Set 5:
(1 comment)
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PS5, Line 10:
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Change subject: soc/sifive/ux00ddr.h: Remove set but unused variables
......................................................................
Patch Set 22: Verified-1
(4 comments)
File src/soc/sifive/fu540/ux00ddr.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162811):
https://review.coreboot.org/c/coreboot/+/63074/comment/74ed68ec_1a06bea8
PS22, Line 179: /* char slicelsc = '0'; */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162811):
https://review.coreboot.org/c/coreboot/+/63074/comment/8b0403b0_a65abdae
PS22, Line 180: /* char slicemsc = '0'; */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162811):
https://review.coreboot.org/c/coreboot/+/63074/comment/3998330e_30956a0b
PS22, Line 181: /* slicelsc += (dq % 10); */
code indent should use tabs where possible
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PS22, Line 182: /* slicemsc += (dq / 10); */
code indent should use tabs where possible
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Change subject: arch/x86/memmove: Add 64bit version
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Patch Set 4: Verified-1
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Change subject: cpu/intel/model_1067x: Use apic exposed in static.c directly
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