coreboot-gerrit November 2022

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[S] Change in coreboot[master]: mb/hp/memphis-s: Update unlicensable files with the CC-PDDC SPDX ID
by Ravi Mistry (Code Review) 07 Nov '22

07 Nov '22

Ravi Mistry has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69321 ) Change subject: mb/hp/memphis-s: Update unlicensable files with the CC-PDDC SPDX ID ...................................................................... mb/hp/memphis-s: Update unlicensable files with the CC-PDDC SPDX ID These files contain no creative content, and therefore have no copyright. This effectively means that they are in the public domain. This commit updates the unlicensable empty (and effectively empty) files with the CC-PDDX identifier for license compliance scanning. Change-Id: I2eae45830cd951b924c18402385fe474c8531dd7 Signed-off-by: Ravi Mistry <rvstry(a)protonmail.com> --- M src/mainboard/hp/memphis-s/acpi/ec.asl M src/mainboard/hp/memphis-s/acpi/superio.asl 2 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/69321/1 diff --git a/src/mainboard/hp/memphis-s/acpi/ec.asl b/src/mainboard/hp/memphis-s/acpi/ec.asl index e69de29..16990d4 100644 --- a/src/mainboard/hp/memphis-s/acpi/ec.asl +++ b/src/mainboard/hp/memphis-s/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/hp/memphis-s/acpi/superio.asl b/src/mainboard/hp/memphis-s/acpi/superio.asl index e69de29..16990d4 100644 --- a/src/mainboard/hp/memphis-s/acpi/superio.asl +++ b/src/mainboard/hp/memphis-s/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2eae45830cd951b924c18402385fe474c8531dd7 Gerrit-Change-Number: 69321 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi Mistry Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/common/block/spi: Mainboard to override SPI Read Mode
by Jon Murphy (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68946 ) Change subject: soc/amd/common/block/spi: Mainboard to override SPI Read Mode ...................................................................... Patch Set 1: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68946/comment/de47ac0f_3ec14dda PS1, Line 15: BUG=b:225213679 > Yeah. This bug provides background regarding the hardware limitation mentioned in the CL. […] Done File src/mainboard/google/guybrush/spi_speeds.c: https://review.coreboot.org/c/coreboot/+/68946/comment/534b245c_2215e69c PS1, Line 7: void mainboard_spi_cfg_override(uint8_t *fast_speed, uint8_t *read_mode) > It is still fast_speed only that we are overriding. There are other speeds that are not touched yet. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I160b56f6201a798ce59e977ca40301e23ab63805 Gerrit-Change-Number: 68946 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 07 Nov 2022 21:47:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb: Add HP Memphis-S (IPM87-MP)
by build bot (Jenkins) (Code Review) 07 Nov '22

07 Nov '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69320 ) Change subject: mb: Add HP Memphis-S (IPM87-MP) ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162833): https://review.coreboot.org/c/coreboot/+/69320/comment/c8620c50_fc157a1b PS1, Line 11: Specs: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3162fa4c60374877d9e67e9e1f6121743f03b21 Gerrit-Change-Number: 69320 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi Mistry Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 07 Nov 2022 21:46:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb: Add HP Memphis-S (IPM87-MP)
by Ravi Mistry (Code Review) 07 Nov '22

07 Nov '22

Ravi Mistry has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69320 ) Change subject: mb: Add HP Memphis-S (IPM87-MP) ...................................................................... mb: Add HP Memphis-S (IPM87-MP) This is a µATX mainboard with an LGA1150 socket and two DDR3 DIMM slots. Specs: - HP Memphis-S (IPM87-MP) - Intel H87 - Macronix MX25L6473E (8MB) - Fintek F71808A - Realtek RTL8111 compatible Gigabit Tested with EDK2 payload to boot Fedora Linux 36. Working: - PCIE slots (including MINI_CARD1) - USB 2.0, 3.0 - Both DIMM slots - SATA (except mSATA) - Ethernet - VGA, DVI (libgfxinit and VBT) - S0/S3/S5 - Audio - Hardware monitor Untested: - mSATA - HOOD_SENSE - MINI_LED header - EHCI debug port, LPC debug - CMOS Change-Id: If3162fa4c60374877d9e67e9e1f6121743f03b21 Signed-off-by: Ravi Mistry <rvstry(a)protonmail.com> --- A src/mainboard/hp/memphis-s/Kconfig A src/mainboard/hp/memphis-s/Kconfig.name A src/mainboard/hp/memphis-s/Makefile.inc A src/mainboard/hp/memphis-s/acpi/ec.asl A src/mainboard/hp/memphis-s/acpi/platform.asl A src/mainboard/hp/memphis-s/acpi/superio.asl A src/mainboard/hp/memphis-s/board_info.txt A src/mainboard/hp/memphis-s/bootblock.c A src/mainboard/hp/memphis-s/cmos.default A src/mainboard/hp/memphis-s/cmos.layout A src/mainboard/hp/memphis-s/data.vbt A src/mainboard/hp/memphis-s/devicetree.cb A src/mainboard/hp/memphis-s/dsdt.asl A src/mainboard/hp/memphis-s/gma-mainboard.ads A src/mainboard/hp/memphis-s/gpio.c A src/mainboard/hp/memphis-s/hda_verb.c A src/mainboard/hp/memphis-s/romstage.c 17 files changed, 650 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/69320/1 diff --git a/src/mainboard/hp/memphis-s/Kconfig b/src/mainboard/hp/memphis-s/Kconfig new file mode 100644 index 0000000..a67209d0 --- /dev/null +++ b/src/mainboard/hp/memphis-s/Kconfig @@ -0,0 +1,35 @@ +if BOARD_HP_MEMPHIS_S + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_HASWELL + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_FINTEK_F71808A + select NO_UART_ON_SUPERIO + +config MAINBOARD_DIR + string + default "hp/memphis-s" + +config MAINBOARD_PART_NUMBER + string + default "Memphis-S" + +config VGA_BIOS_ID + string + default "8086,0412" + +#config USBDEBUG_HCD_INDEX +# int +# default 2 +# This board has an EHCI debug port that has not yet been tested +endif diff --git a/src/mainboard/hp/memphis-s/Kconfig.name b/src/mainboard/hp/memphis-s/Kconfig.name new file mode 100644 index 0000000..8268d31 --- /dev/null +++ b/src/mainboard/hp/memphis-s/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_MEMPHIS_S + bool "Memphis-S" diff --git a/src/mainboard/hp/memphis-s/Makefile.inc b/src/mainboard/hp/memphis-s/Makefile.inc new file mode 100644 index 0000000..d9a8d18 --- /dev/null +++ b/src/mainboard/hp/memphis-s/Makefile.inc @@ -0,0 +1,5 @@ +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += bootblock.c diff --git a/src/mainboard/hp/memphis-s/acpi/ec.asl b/src/mainboard/hp/memphis-s/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/hp/memphis-s/acpi/ec.asl diff --git a/src/mainboard/hp/memphis-s/acpi/platform.asl b/src/mainboard/hp/memphis-s/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/hp/memphis-s/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/hp/memphis-s/acpi/superio.asl b/src/mainboard/hp/memphis-s/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/hp/memphis-s/acpi/superio.asl diff --git a/src/mainboard/hp/memphis-s/board_info.txt b/src/mainboard/hp/memphis-s/board_info.txt new file mode 100644 index 0000000..ff5c890 --- /dev/null +++ b/src/mainboard/hp/memphis-s/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +ROM protocol: SPI +Flashrom support: n +ROM package: SOIC-8 +ROM socketed: n +Release year: 2014 + diff --git a/src/mainboard/hp/memphis-s/bootblock.c b/src/mainboard/hp/memphis-s/bootblock.c new file mode 100644 index 0000000..4801fc9 --- /dev/null +++ b/src/mainboard/hp/memphis-s/bootblock.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f71808a/f71808a.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define KEYBOARD_DEV PNP_DEV(0x2e, F71808A_KBC) +#define ACPI_DEV PNP_DEV(0x2e, F71808A_PME) + +void mainboard_config_superio(void) +{ + pnp_enter_conf_state(GLOBAL_DEV); + + pnp_write_config(GLOBAL_DEV, 0x25, 0x02); + pnp_write_config(GLOBAL_DEV, 0x27, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2d, 0x00); + + pnp_set_logical_device(KEYBOARD_DEV); + pnp_write_config(KEYBOARD_DEV, 0xfe, 0x81); + +/* GPIO register 0xe2, ACPI register 0xf1 values (0x1f and 0x60) */ +/* don't match values using vendor firmware (0x1d and 0x00), */ +/* but nothing appears to be wrong */ + +/* HWM register 0x21 (expected value 0xd6, actual value 0xd5) */ + + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe0, 0x00); + pnp_write_config(ACPI_DEV, 0xe1, 0xc6); + pnp_write_config(ACPI_DEV, 0xe8, 0x6f); + pnp_write_config(ACPI_DEV, 0xed, 0xc0); + pnp_write_config(ACPI_DEV, 0xf0, 0xf2); + pnp_write_config(ACPI_DEV, 0xf1, 0x00); + pnp_write_config(ACPI_DEV, 0xf2, 0x13); + pnp_write_config(ACPI_DEV, 0xf8, 0x04); + pnp_write_config(ACPI_DEV, 0xf9, 0x01); + + pnp_exit_conf_state(GLOBAL_DEV); +} diff --git a/src/mainboard/hp/memphis-s/cmos.default b/src/mainboard/hp/memphis-s/cmos.default new file mode 100644 index 0000000..c51001c --- /dev/null +++ b/src/mainboard/hp/memphis-s/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Debug +nmi=Enable +power_on_after_fail=Disable diff --git a/src/mainboard/hp/memphis-s/cmos.layout b/src/mainboard/hp/memphis-s/cmos.layout new file mode 100644 index 0000000..c9ba76c --- /dev/null +++ b/src/mainboard/hp/memphis-s/cmos.layout @@ -0,0 +1,58 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 4 debug_level + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 5 power_on_after_fail + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Enable +2 1 Disable + +3 0 Fallback +3 1 Normal + +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +5 0 Disable +5 1 Enable +5 2 Keep + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/hp/memphis-s/data.vbt b/src/mainboard/hp/memphis-s/data.vbt new file mode 100644 index 0000000..069abc6 --- /dev/null +++ b/src/mainboard/hp/memphis-s/data.vbt Binary files differ diff --git a/src/mainboard/hp/memphis-s/devicetree.cb b/src/mainboard/hp/memphis-s/devicetree.cb new file mode 100644 index 0000000..8b09ab5 --- /dev/null +++ b/src/mainboard/hp/memphis-s/devicetree.cb @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/haswell + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "usb_xhci_on_resume" = "true" + register "ec_present" = "false" + device cpu_cluster 0x0 on + chip cpu/intel/haswell + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0291" + register "gpe0_en_1" = "0x46" + register "gpe0_en_2" = "0x0" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x8" + device pci 14.0 on # xHCI Controller + subsystemid 0x103c 0x2af7 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x103c 0x2af7 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x103c 0x2af7 + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x103c 0x2af7 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x103c 0x2af7 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 on # PCIE_X1_1 + end + device pci 1c.3 on # PCIE_X1_2 + end + device pci 1c.4 on # PCIE_X1_3 + end + device pci 1c.5 on # MINI_CARD1 + end + device pci 1c.6 on # PCIe Port #7 + subsystemid 0x103c 0x2af7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x103c 0x2af7 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x103c 0x2af7 + chip superio/fintek/f71808a + register "multi_function_register_0" = "0x00" + register "multi_function_register_1" = "0x80" + register "multi_function_register_2" = "0x21" + register "multi_function_register_3" = "0x4f" + register "multi_function_register_4" = "0x1c" + register "hwm_peci_tsi_ctrl" = "0x02" # PECI enabled, 1.23 V + register "hwm_tcc_temp" = "0x5c" # TCC temperature = 92 °C + register "hwm_fan1_boundary_hysteresis" = "0x44" + register "hwm_fan1_seg1_speed" = "0xff" # Fan 1 segment 1 = 100% + register "hwm_fan1_seg2_speed" = "0xff" # Fan 1 segment 2 = 100% + register "hwm_fan1_seg3_speed" = "0x93" # Fan 1 segment 3 = 58% + register "hwm_fan1_seg4_speed" = "0x7f" # Fan 1 segment 4 = 50% + register "hwm_fan1_seg5_speed" = "0x5b" # Fan 1 segment 5 = 36% + register "hwm_fan1_temp_src" = "0x1c" # Fan 1 source = PECI + register "hwm_vt1_boundary_1_temperature" = "0x61" # Fan 1 boundary 1 = 97°C + register "hwm_vt1_boundary_2_temperature" = "0x5c" # Fan 1 boundary 2 = 92°C + register "hwm_vt1_boundary_3_temperature" = "0x3c" # Fan 1 boundary 3 = 60°C + register "hwm_vt1_boundary_4_temperature" = "0x2d" # Fan 1 boundary 4 = 45°C + register "hwm_fan2_seg1_speed" = "0xff" # Fan 2 segment 1 = 100% + register "hwm_fan2_seg2_speed" = "0xff" # Fan 2 segment 2 = 100% + register "hwm_fan2_seg3_speed" = "0x7f" # Fan 2 segment 3 = 50% + register "hwm_fan2_seg4_speed" = "0x72" # Fan 2 segment 4 = 45% + register "hwm_fan2_seg5_speed" = "0x5b" # Fan 2 segment 5 = 36% + register "hwm_fan2_temp_src" = "0x1c" # Fan 2 source = PECI + register "hwm_vt2_boundary_1_temperature" = "0x61" # Fan 2 boundary 1 = 97°C + register "hwm_vt2_boundary_2_temperature" = "0x5c" # Fan 2 boundary 2 = 92°C + register "hwm_vt2_boundary_3_temperature" = "0x3c" # Fan 2 boundary 3 = 60°C + register "hwm_vt2_boundary_4_temperature" = "0x2d" # Fan 2 boundary 4 = 45°C + device pnp 2e.1 off end # COM1 + device pnp 2e.4 on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0x00 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + irq 0x70 = 0x01 + irq 0x72 = 0x0c + end + device pnp 2e.6 on # GPIO + irq 0x70 = 0x00 + end + device pnp 2e.7 off end # WDT + device pnp 2e.8 off end # CIR + device pnp 2e.a on # PME, ACPI, EUP + end + end + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x103c 0x2af7 + end + device pci 1f.3 on # SMBus + subsystemid 0x103c 0x2af7 + end + device pci 1f.5 off # SATA Controller (Legacy) + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Desktop Host bridge + subsystemid 0x103c 0x2af7 + end + device pci 01.0 on # PCIE_X16 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x103c 0x2af7 + end + device pci 03.0 off # Mini-HD audio + end + end +end diff --git a/src/mainboard/hp/memphis-s/dsdt.asl b/src/mainboard/hp/memphis-s/dsdt.asl new file mode 100644 index 0000000..13a5b6a --- /dev/null +++ b/src/mainboard/hp/memphis-s/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/hp/memphis-s/gma-mainboard.ads b/src/mainboard/hp/memphis-s/gma-mainboard.ads new file mode 100644 index 0000000..c9e4326 --- /dev/null +++ b/src/mainboard/hp/memphis-s/gma-mainboard.ads @@ -0,0 +1,16 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/memphis-s/gpio.c b/src/mainboard/hp/memphis-s/gpio.c new file mode 100644 index 0000000..042d9af --- /dev/null +++ b/src/mainboard/hp/memphis-s/gpio.c @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_NATIVE, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio35 = GPIO_LEVEL_LOW, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio50 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/memphis-s/hda_verb.c b/src/mainboard/hp/memphis-s/hda_verb.c new file mode 100644 index 0000000..4de0104 --- /dev/null +++ b/src/mainboard/hp/memphis-s/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d76f3, /* Codec Vendor / Device ID: IDT */ + 0x103c2af7, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c2af7), + AZALIA_PIN_CFG(0, 0x0a, 0x0221402f), + AZALIA_PIN_CFG(0, 0x0b, 0x01114020), + AZALIA_PIN_CFG(0, 0x0c, 0x02a19041), + AZALIA_PIN_CFG(0, 0x0e, 0x01a1904e), + AZALIA_PIN_CFG(0, 0x0f, 0x01813050), + AZALIA_PIN_CFG(0, 0x10, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x11, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x20, 0x40f000f0), + AZALIA_PIN_CFG(0, 0x24, 0x40f000f0), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/memphis-s/romstage.c b/src/mainboard/hp/memphis-s/romstage.c new file mode 100644 index 0000000..143b8c6 --- /dev/null +++ b/src/mainboard/hp/memphis-s/romstage.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[2] = 0x52; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/69320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3162fa4c60374877d9e67e9e1f6121743f03b21 Gerrit-Change-Number: 69320 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi Mistry Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: include/cper.h: Add CPER Memory Error Section definitions
by Jonathan Zhang (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Johnny Lin, Angel Pons, Shuming Chu (Shuming), Tim Chu. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69198 ) Change subject: include/cper.h: Add CPER Memory Error Section definitions ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a165350a16a4cbe4033a3e7c43fa23a5b27c44b Gerrit-Change-Number: 69198 Gerrit-PatchSet: 3 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 21:11:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: mb/aopen/dxplplusu: Remove board
by 9elements QA (Code Review) 07 Nov '22

07 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69114 ) Change subject: mb/aopen/dxplplusu: Remove board ...................................................................... Patch Set 6: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134231 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134230 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/134229 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/134228 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/134227 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134226 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/134225 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/134224 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/134223 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/134222 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/134221 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/134220 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134219 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/134218 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/134217 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/134216 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf37ade31ddb55697df1a65062c092a0a485e175 Gerrit-Change-Number: 69114 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Mon, 07 Nov 2022 21:01:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: vendorcode/amd/agesa: Drop unused common code
by 9elements QA (Code Review) 07 Nov '22

07 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69127 ) Change subject: vendorcode/amd/agesa: Drop unused common code ...................................................................... Patch Set 7: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134247 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134246 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/134245 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/134244 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/134243 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134242 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/134241 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/134240 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/134239 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/134238 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/134237 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/134236 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134235 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/134234 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/134233 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/134232 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If32a4de7ef263f1d4f7ab7a36751ad9dcf52dc7e Gerrit-Change-Number: 69127 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 21:01:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XL] Change in coreboot[master]: vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3361.07
by Nick Vaccaro (Code Review) 07 Nov '22

07 Nov '22

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68495 ) Change subject: vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3361.07 ...................................................................... vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3361.07 The headers added are generated as per FSP v3361.07 In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake fsp headers can be deleted and Raptor Lake soc will also use headers from alderlake/ folder. BUG=b:254054169 BRANCH=firmware-brya-14505.B TEST=Boot to OS Signed-off-by: Selma Bensaid <selma.bensaid(a)intel.com> Change-Id: If486867477c88ad3e2ec5041ef94a0c364f5dfd6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68495 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h 2 files changed, 908 insertions(+), 861 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h index 55aa5ea..cfd5595 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h @@ -78,271 +78,279 @@ **/ UINT8 CpuCrashLogDevice; -/** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0 +/** Offset 0x004C - Reserved +**/ + UINT8 Reserved0[3]; + +/** Offset 0x004F - Reserved +**/ + UINT8 Reserved1; + +/** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 0 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ UINT32 MemorySpdPtr000; -/** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1 +/** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ UINT32 MemorySpdPtr001; -/** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0 +/** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ UINT32 MemorySpdPtr010; -/** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1 +/** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 1 Dimm 1 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ UINT32 MemorySpdPtr011; -/** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 2 Dimm 0 +/** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 0 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ UINT32 MemorySpdPtr020; -/** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1 +/** Offset 0x0064 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ UINT32 MemorySpdPtr021; -/** Offset 0x0064 - Memory SPD Pointer Controller 0 Channel 3 Dimm 0 +/** Offset 0x0068 - Memory SPD Pointer Controller 0 Channel 3 Dimm 0 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ UINT32 MemorySpdPtr030; -/** Offset 0x0068 - Memory SPD Pointer Controller 0 Channel 3 Dimm 1 +/** Offset 0x006C - Memory SPD Pointer Controller 0 Channel 3 Dimm 1 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ UINT32 MemorySpdPtr031; -/** Offset 0x006C - Memory SPD Pointer Controller 1 Channel 0 Dimm 0 +/** Offset 0x0070 - Memory SPD Pointer Controller 1 Channel 0 Dimm 0 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ UINT32 MemorySpdPtr100; -/** Offset 0x0070 - Memory SPD Pointer Controller 1 Channel 0 Dimm 1 +/** Offset 0x0074 - Memory SPD Pointer Controller 1 Channel 0 Dimm 1 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ UINT32 MemorySpdPtr101; -/** Offset 0x0074 - Memory SPD Pointer Controller 1 Channel 1 Dimm 0 +/** Offset 0x0078 - Memory SPD Pointer Controller 1 Channel 1 Dimm 0 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ UINT32 MemorySpdPtr110; -/** Offset 0x0078 - Memory SPD Pointer Controller 1 Channel 1 Dimm 1 +/** Offset 0x007C - Memory SPD Pointer Controller 1 Channel 1 Dimm 1 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ UINT32 MemorySpdPtr111; -/** Offset 0x007C - Memory SPD Pointer Controller 1 Channel 2 Dimm 0 +/** Offset 0x0080 - Memory SPD Pointer Controller 1 Channel 2 Dimm 0 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ UINT32 MemorySpdPtr120; -/** Offset 0x0080 - Memory SPD Pointer Controller 1 Channel 2 Dimm 1 +/** Offset 0x0084 - Memory SPD Pointer Controller 1 Channel 2 Dimm 1 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ UINT32 MemorySpdPtr121; -/** Offset 0x0084 - Memory SPD Pointer Controller 1 Channel 3 Dimm 0 +/** Offset 0x0088 - Memory SPD Pointer Controller 1 Channel 3 Dimm 0 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ UINT32 MemorySpdPtr130; -/** Offset 0x0088 - Memory SPD Pointer Controller 1 Channel 3 Dimm 1 +/** Offset 0x008C - Memory SPD Pointer Controller 1 Channel 3 Dimm 1 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ UINT32 MemorySpdPtr131; -/** Offset 0x008C - RcompResistor settings +/** Offset 0x0090 - RcompResistor settings Indicates RcompResistor settings: Board-dependent **/ UINT16 RcompResistor; -/** Offset 0x008E - RcompTarget settings +/** Offset 0x0092 - RcompTarget settings RcompTarget settings: board-dependent **/ UINT16 RcompTarget[5]; -/** Offset 0x0098 - Dqs Map CPU to DRAM MC 0 CH 0 +/** Offset 0x009C - Dqs Map CPU to DRAM MC 0 CH 0 Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent **/ UINT8 DqsMapCpu2DramMc0Ch0[2]; -/** Offset 0x009A - Dqs Map CPU to DRAM MC 0 CH 1 +/** Offset 0x009E - Dqs Map CPU to DRAM MC 0 CH 1 Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent **/ UINT8 DqsMapCpu2DramMc0Ch1[2]; -/** Offset 0x009C - Dqs Map CPU to DRAM MC 0 CH 2 +/** Offset 0x00A0 - Dqs Map CPU to DRAM MC 0 CH 2 Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent **/ UINT8 DqsMapCpu2DramMc0Ch2[2]; -/** Offset 0x009E - Dqs Map CPU to DRAM MC 0 CH 3 +/** Offset 0x00A2 - Dqs Map CPU to DRAM MC 0 CH 3 Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent **/ UINT8 DqsMapCpu2DramMc0Ch3[2]; -/** Offset 0x00A0 - Dqs Map CPU to DRAM MC 1 CH 0 +/** Offset 0x00A4 - Dqs Map CPU to DRAM MC 1 CH 0 Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent **/ UINT8 DqsMapCpu2DramMc1Ch0[2]; -/** Offset 0x00A2 - Dqs Map CPU to DRAM MC 1 CH 1 +/** Offset 0x00A6 - Dqs Map CPU to DRAM MC 1 CH 1 Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent **/ UINT8 DqsMapCpu2DramMc1Ch1[2]; -/** Offset 0x00A4 - Dqs Map CPU to DRAM MC 1 CH 2 +/** Offset 0x00A8 - Dqs Map CPU to DRAM MC 1 CH 2 Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent **/ UINT8 DqsMapCpu2DramMc1Ch2[2]; -/** Offset 0x00A6 - Dqs Map CPU to DRAM MC 1 CH 3 +/** Offset 0x00AA - Dqs Map CPU to DRAM MC 1 CH 3 Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent **/ UINT8 DqsMapCpu2DramMc1Ch3[2]; -/** Offset 0x00A8 - Dq Map CPU to DRAM MC 0 CH 0 +/** Offset 0x00AC - Dq Map CPU to DRAM MC 0 CH 0 Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent **/ UINT8 DqMapCpu2DramMc0Ch0[16]; -/** Offset 0x00B8 - Dq Map CPU to DRAM MC 0 CH 1 +/** Offset 0x00BC - Dq Map CPU to DRAM MC 0 CH 1 Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent **/ UINT8 DqMapCpu2DramMc0Ch1[16]; -/** Offset 0x00C8 - Dq Map CPU to DRAM MC 0 CH 2 +/** Offset 0x00CC - Dq Map CPU to DRAM MC 0 CH 2 Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependet **/ UINT8 DqMapCpu2DramMc0Ch2[16]; -/** Offset 0x00D8 - Dq Map CPU to DRAM MC 0 CH 3 +/** Offset 0x00DC - Dq Map CPU to DRAM MC 0 CH 3 Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent **/ UINT8 DqMapCpu2DramMc0Ch3[16]; -/** Offset 0x00E8 - Dq Map CPU to DRAM MC 1 CH 0 +/** Offset 0x00EC - Dq Map CPU to DRAM MC 1 CH 0 Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent **/ UINT8 DqMapCpu2DramMc1Ch0[16]; -/** Offset 0x00F8 - Dq Map CPU to DRAM MC 1 CH 1 +/** Offset 0x00FC - Dq Map CPU to DRAM MC 1 CH 1 Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent **/ UINT8 DqMapCpu2DramMc1Ch1[16]; -/** Offset 0x0108 - Dq Map CPU to DRAM MC 1 CH 2 +/** Offset 0x010C - Dq Map CPU to DRAM MC 1 CH 2 Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent **/ UINT8 DqMapCpu2DramMc1Ch2[16]; -/** Offset 0x0118 - Dq Map CPU to DRAM MC 1 CH 3 +/** Offset 0x011C - Dq Map CPU to DRAM MC 1 CH 3 Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent **/ UINT8 DqMapCpu2DramMc1Ch3[16]; -/** Offset 0x0128 - Dqs Pins Interleaved Setting +/** Offset 0x012C - Dqs Pins Interleaved Setting Indicates DqPinsInterleaved setting: board-dependent $EN_DIS **/ UINT8 DqPinsInterleaved; -/** Offset 0x0129 - Smram Mask +/** Offset 0x012D - Smram Mask The SMM Regions AB-SEG and/or H-SEG reserved 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both **/ UINT8 SmramMask; -/** Offset 0x012A - Ibecc +/** Offset 0x012E - Ibecc Enable/Disable Ibecc $EN_DIS **/ UINT8 Ibecc; -/** Offset 0x012B - IbeccOperationMode +/** Offset 0x012F - IbeccOperationMode In-Band ECC Operation Mode 0:Protect base on address range, 1:Non-protected, 2:All protected **/ UINT8 IbeccOperationMode; -/** Offset 0x012C - IbeccProtectedRangeEnable +/** Offset 0x0130 - IbeccProtectedRangeEnable In-Band ECC Protected Region Enable $EN_DIS **/ UINT8 IbeccProtectedRangeEnable[8]; -/** Offset 0x0134 - IbeccProtectedRangeBase +/** Offset 0x0138 - IbeccProtectedRangeBase IBECC Protected Region Base **/ UINT32 IbeccProtectedRangeBase[8]; -/** Offset 0x0154 - IbeccProtectedRangeMask +/** Offset 0x0158 - IbeccProtectedRangeMask IBECC Protected Region Mask **/ UINT32 IbeccProtectedRangeMask[8]; -/** Offset 0x0174 - MRC Fast Boot +/** Offset 0x0178 - MRC Fast Boot Enables/Disable the MRC fast path thru the MRC $EN_DIS **/ UINT8 MrcFastBoot; -/** Offset 0x0175 - Rank Margin Tool per Task +/** Offset 0x0179 - Rank Margin Tool per Task This option enables the user to execute Rank Margin Tool per major training step in the MRC. $EN_DIS **/ UINT8 RmtPerTask; -/** Offset 0x0176 - Training Trace +/** Offset 0x017A - Training Trace This option enables the trained state tracing feature in MRC. This feature will print out the key training parameters state across major training steps. $EN_DIS **/ UINT8 TrainTrace; -/** Offset 0x0177 - Reserved +/** Offset 0x017B - Reserved **/ - UINT8 Reserved0; + UINT8 Reserved2; -/** Offset 0x0178 - Tseg Size +/** Offset 0x017C - Tseg Size Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build 0x0400000:4MB, 0x01000000:16MB **/ UINT32 TsegSize; -/** Offset 0x017C - MMIO Size +/** Offset 0x0180 - MMIO Size Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB **/ UINT16 MmioSize; -/** Offset 0x017E - Probeless Trace +/** Offset 0x0182 - Probeless Trace Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. This also requires IED to be enabled. $EN_DIS **/ UINT8 ProbelessTrace; -/** Offset 0x017F - Enable SMBus +/** Offset 0x0183 - Enable SMBus Enable/disable SMBus controller. $EN_DIS **/ UINT8 SmbusEnable; -/** Offset 0x0180 - Spd Address Tabl +/** Offset 0x0184 - Spd Address Tabl Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used if SPD Address is 00 **/ UINT8 SpdAddressTable[16]; -/** Offset 0x0190 - Platform Debug Consent +/** Offset 0x0194 - Platform Debug Consent Enabled(All Probes+TraceHub) supports all probes with TraceHub enabled and blocks s0ix\n \n @@ -354,118 +362,122 @@ **/ UINT8 PlatformDebugConsent; -/** Offset 0x0191 - DCI Enable +/** Offset 0x0195 - DCI Enable Determine if to enable DCI debug from host $EN_DIS **/ UINT8 DciEn; -/** Offset 0x0192 - DCI DbC Mode +/** Offset 0x0196 - DCI DbC Mode Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both: Set both USB2/3DBCEN; No Change: Comply with HW value 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change **/ UINT8 DciDbcMode; -/** Offset 0x0193 - Enable DCI ModPHY Power Gate +/** Offset 0x0197 - Enable DCI ModPHY Power Gate DEPRECATED $EN_DIS **/ UINT8 DciModphyPg; -/** Offset 0x0194 - USB3 Type-C UFP2DFP Kernel/Platform Debug Support +/** Offset 0x0198 - USB3 Type-C UFP2DFP Kernel/Platform Debug Support This BIOS option enables kernel and platform debug for USB3 interface over a UFP Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. 0:Disabled, 1:Enabled, 2:No Change **/ UINT8 DciUsb3TypecUfpDbg; -/** Offset 0x0195 - PCH Trace Hub Mode +/** Offset 0x0199 - PCH Trace Hub Mode Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode **/ UINT8 PchTraceHubMode; -/** Offset 0x0196 - PCH Trace Hub Memory Region 0 buffer Size +/** Offset 0x019A - PCH Trace Hub Memory Region 0 buffer Size Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB **/ UINT8 PchTraceHubMemReg0Size; -/** Offset 0x0197 - PCH Trace Hub Memory Region 1 buffer Size +/** Offset 0x019B - PCH Trace Hub Memory Region 1 buffer Size Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB **/ UINT8 PchTraceHubMemReg1Size; -/** Offset 0x0198 - HD Audio DMIC Link Clock Select +/** Offset 0x019C - HD Audio DMIC Link Clock Select Determines DMIC<N> Clock Source. 0: Both, 1: ClkA, 2: ClkB 0: Both, 1: ClkA, 2: ClkB **/ UINT8 PchHdaAudioLinkDmicClockSelect[2]; -/** Offset 0x019A - Reserved +/** Offset 0x019E - Reserved **/ - UINT8 Reserved1[5]; + UINT8 Reserved3; -/** Offset 0x019F - State of X2APIC_OPT_OUT bit in the DMAR table +/** Offset 0x019F - Reserved +**/ + UINT8 Reserved4[4]; + +/** Offset 0x01A3 - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set $EN_DIS **/ UINT8 X2ApicOptOut; -/** Offset 0x01A0 - State of DMA_CONTROL_GUARANTEE bit in the DMAR table +/** Offset 0x01A4 - State of DMA_CONTROL_GUARANTEE bit in the DMAR table 0=Disable/Clear, 1=Enable/Set $EN_DIS **/ UINT8 DmaControlGuarantee; -/** Offset 0x01A1 - Reserved +/** Offset 0x01A5 - Reserved **/ - UINT8 Reserved2[3]; + UINT8 Reserved5[3]; -/** Offset 0x01A4 - Base addresses for VT-d function MMIO access +/** Offset 0x01A8 - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d engine **/ UINT32 VtdBaseAddress[9]; -/** Offset 0x01C8 - Disable VT-d +/** Offset 0x01CC - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) $EN_DIS **/ UINT8 VtdDisable; -/** Offset 0x01C9 - Vtd Programming for Igd +/** Offset 0x01CD - Vtd Programming for Igd 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar programming disabled) $EN_DIS **/ UINT8 VtdIgdEnable; -/** Offset 0x01CA - Vtd Programming for Ipu +/** Offset 0x01CE - Vtd Programming for Ipu 1=Enable/TRUE (Ipu VT-d Bar programming enabled), 0=Disable/FLASE (Ipu VT-d Bar programming disabled) $EN_DIS **/ UINT8 VtdIpuEnable; -/** Offset 0x01CB - Vtd Programming for Iop +/** Offset 0x01CF - Vtd Programming for Iop 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar programming disabled) $EN_DIS **/ UINT8 VtdIopEnable; -/** Offset 0x01CC - Vtd Programming for ITbt +/** Offset 0x01D0 - Vtd Programming for ITbt DEPRECATED $EN_DIS **/ UINT8 VtdItbtEnable; -/** Offset 0x01CD - Internal Graphics Pre-allocated Memory +/** Offset 0x01D1 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics. 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, @@ -473,19 +485,19 @@ **/ UINT8 IgdDvmt50PreAlloc; -/** Offset 0x01CE - Internal Graphics +/** Offset 0x01D2 - Internal Graphics Enable/disable internal graphics. $EN_DIS **/ UINT8 InternalGfx; -/** Offset 0x01CF - Aperture Size +/** Offset 0x01D3 - Aperture Size Select the Aperture Size. 0:128 MB, 1:256 MB, 3:512 MB, 7:1024 MB, 15: 2048 MB **/ UINT8 ApertureSize; -/** Offset 0x01D0 - Board Type +/** Offset 0x01D4 - Board Type MrcBoardType, Options are 0:Mobile, 1:Desktop1Dpc, 2:Desktop2DpcDaisyChain, 3:Desktop2DpcTeeTopologyAsymmetrical, 4:Desktop2DpcTeeTopology, 5:UltMobile, 7:UP Server 0:Mobile, 1:Desktop1Dpc, 2:Desktop2DpcDaisyChain, 3:Desktop2DpcTeeTopologyAsymmetrical, @@ -493,97 +505,97 @@ **/ UINT8 UserBd; -/** Offset 0x01D1 - Reserved +/** Offset 0x01D5 - Reserved **/ - UINT8 Reserved3; + UINT8 Reserved6; -/** Offset 0x01D2 - DDR Frequency Limit +/** Offset 0x01D6 - DDR Frequency Limit Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933 and 0 for Auto. 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto **/ UINT16 DdrFreqLimit; -/** Offset 0x01D4 - SA GV +/** Offset 0x01D8 - SA GV System Agent dynamic frequency support and when enabled memory will be training at four different frequencies. 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, 4:FixedPoint3, 5:Enabled **/ UINT8 SaGv; -/** Offset 0x01D5 - Memory Test on Warm Boot +/** Offset 0x01D9 - Memory Test on Warm Boot Run Base Memory Test on Warm Boot 0:Disable, 1:Enable **/ UINT8 MemTestOnWarmBoot; -/** Offset 0x01D6 - DDR Speed Control +/** Offset 0x01DA - DDR Speed Control DDR Frequency and Gear control for all SAGV points. 0:Auto, 1:Manual **/ UINT8 DdrSpeedControl; -/** Offset 0x01D7 - Rank Margin Tool +/** Offset 0x01DB - Rank Margin Tool Enable/disable Rank Margin Tool. $EN_DIS **/ UINT8 RMT; -/** Offset 0x01D8 - Controller 0 Channel 0 DIMM Control +/** Offset 0x01DC - Controller 0 Channel 0 DIMM Control Enable / Disable DIMMs on Controller 0 Channel 0 $EN_DIS **/ UINT8 DisableMc0Ch0; -/** Offset 0x01D9 - Controller 0 Channel 1 DIMM Control +/** Offset 0x01DD - Controller 0 Channel 1 DIMM Control Enable / Disable DIMMs on Controller 0 Channel 1 $EN_DIS **/ UINT8 DisableMc0Ch1; -/** Offset 0x01DA - Controller 0 Channel 2 DIMM Control +/** Offset 0x01DE - Controller 0 Channel 2 DIMM Control Enable / Disable DIMMs on Controller 0 Channel 2 $EN_DIS **/ UINT8 DisableMc0Ch2; -/** Offset 0x01DB - Controller 0 Channel 3 DIMM Control +/** Offset 0x01DF - Controller 0 Channel 3 DIMM Control Enable / Disable DIMMs on Controller 0 Channel 3 $EN_DIS **/ UINT8 DisableMc0Ch3; -/** Offset 0x01DC - Controller 1 Channel 0 DIMM Control +/** Offset 0x01E0 - Controller 1 Channel 0 DIMM Control Enable / Disable DIMMs on Controller 1 Channel 0 $EN_DIS **/ UINT8 DisableMc1Ch0; -/** Offset 0x01DD - Controller 1 Channel 1 DIMM Control +/** Offset 0x01E1 - Controller 1 Channel 1 DIMM Control Enable / Disable DIMMs on Controller 1 Channel 1 $EN_DIS **/ UINT8 DisableMc1Ch1; -/** Offset 0x01DE - Controller 1 Channel 2 DIMM Control +/** Offset 0x01E2 - Controller 1 Channel 2 DIMM Control Enable / Disable DIMMs on Controller 1 Channel 2 $EN_DIS **/ UINT8 DisableMc1Ch2; -/** Offset 0x01DF - Controller 1 Channel 3 DIMM Control +/** Offset 0x01E3 - Controller 1 Channel 3 DIMM Control Enable / Disable DIMMs on Controller 1 Channel 3 $EN_DIS **/ UINT8 DisableMc1Ch3; -/** Offset 0x01E0 - Scrambler Support +/** Offset 0x01E4 - Scrambler Support This option enables data scrambling in memory. $EN_DIS **/ UINT8 ScramblerSupport; -/** Offset 0x01E1 - SPD Profile Selected +/** Offset 0x01E5 - SPD Profile Selected Select DIMM timing profile. Options are 0:Default SPD Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2, 4:XMP Profile 3, 5:XMP User Profile 4, 6:XMP User Profile 5 @@ -592,93 +604,93 @@ **/ UINT8 SpdProfileSelected; -/** Offset 0x01E2 - Memory Reference Clock +/** Offset 0x01E6 - Memory Reference Clock 100MHz, 133MHz. 0:133MHz, 1:100MHz **/ UINT8 RefClk; -/** Offset 0x01E3 - Reserved +/** Offset 0x01E7 - Reserved **/ - UINT8 Reserved4; + UINT8 Reserved7; -/** Offset 0x01E4 - Memory Voltage +/** Offset 0x01E8 - Memory Voltage DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM chips) in millivolts from 0 - default to 1435mv. **/ UINT16 VddVoltage; -/** Offset 0x01E6 - Memory Ratio +/** Offset 0x01EA - Memory Ratio Automatic or the frequency will equal ratio times reference clock. Set to Auto to recalculate memory timings listed below. 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 **/ UINT8 Ratio; -/** Offset 0x01E7 - tCL +/** Offset 0x01EB - tCL CAS Latency, 0: AUTO, max: 31. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). **/ UINT8 tCL; -/** Offset 0x01E8 - tCWL +/** Offset 0x01EC - tCWL Min CAS Write Latency Delay Time, 0: AUTO, max: 34. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). **/ UINT8 tCWL; -/** Offset 0x01E9 - Reserved +/** Offset 0x01ED - Reserved **/ - UINT8 Reserved5; + UINT8 Reserved8; -/** Offset 0x01EA - tFAW +/** Offset 0x01EE - tFAW Min Four Activate Window Delay Time, 0: AUTO, max: 63. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). **/ UINT16 tFAW; -/** Offset 0x01EC - tRAS +/** Offset 0x01F0 - tRAS RAS Active Time, 0: AUTO, max: 64. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). **/ UINT16 tRAS; -/** Offset 0x01EE - tRCD/tRP +/** Offset 0x01F2 - tRCD/tRP RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). **/ UINT8 tRCDtRP; -/** Offset 0x01EF - Reserved +/** Offset 0x01F3 - Reserved **/ - UINT8 Reserved6; + UINT8 Reserved9; -/** Offset 0x01F0 - tREFI +/** Offset 0x01F4 - tREFI Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). **/ UINT16 tREFI; -/** Offset 0x01F2 - tRFC +/** Offset 0x01F6 - tRFC Min Refresh Recovery Delay Time, 0: AUTO, max: 1023. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). **/ UINT16 tRFC; -/** Offset 0x01F4 - tRRD +/** Offset 0x01F8 - tRRD Min Row Active to Row Active Delay Time, 0: AUTO, max: 15. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). **/ UINT8 tRRD; -/** Offset 0x01F5 - tRTP +/** Offset 0x01F9 - tRTP Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). **/ UINT8 tRTP; -/** Offset 0x01F6 - tWR +/** Offset 0x01FA - tWR Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, @@ -686,105 +698,105 @@ **/ UINT8 tWR; -/** Offset 0x01F7 - tWTR +/** Offset 0x01FB - tWTR Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). **/ UINT8 tWTR; -/** Offset 0x01F8 - NMode +/** Offset 0x01FC - NMode System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N **/ UINT8 NModeSupport; -/** Offset 0x01F9 - Enable Intel HD Audio (Azalia) +/** Offset 0x01FD - Enable Intel HD Audio (Azalia) 0: Disable, 1: Enable (Default) Azalia controller $EN_DIS **/ UINT8 PchHdaEnable; -/** Offset 0x01FA - Enable PCH ISH Controller +/** Offset 0x01FE - Enable PCH ISH Controller 0: Disable, 1: Enable (Default) ISH Controller $EN_DIS **/ UINT8 PchIshEnable; -/** Offset 0x01FB - CPU Trace Hub Mode +/** Offset 0x01FF - CPU Trace Hub Mode Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode **/ UINT8 CpuTraceHubMode; -/** Offset 0x01FC - CPU Trace Hub Memory Region 0 +/** Offset 0x0200 - CPU Trace Hub Memory Region 0 CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB **/ UINT8 CpuTraceHubMemReg0Size; -/** Offset 0x01FD - CPU Trace Hub Memory Region 1 +/** Offset 0x0201 - CPU Trace Hub Memory Region 1 CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB **/ UINT8 CpuTraceHubMemReg1Size; -/** Offset 0x01FE - SAGV Gear Ratio +/** Offset 0x0202 - SAGV Gear Ratio Gear Selection for SAGV points. 0 - Auto, 1-1 Gear 1, 2-Gear 2 **/ UINT8 SaGvGear[4]; -/** Offset 0x0202 - SAGV Frequency +/** Offset 0x0206 - SAGV Frequency SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300. **/ UINT16 SaGvFreq[4]; -/** Offset 0x020A - SAGV Disabled Gear Ratio +/** Offset 0x020E - SAGV Disabled Gear Ratio Gear Selection for SAGV Disabled. 0 - Auto, 1-1 Gear 1, 2-Gear 2 **/ UINT8 GearRatio; -/** Offset 0x020B - HECI Timeouts +/** Offset 0x020F - HECI Timeouts 0: Disable, 1: Enable (Default) timeout check for HECI $EN_DIS **/ UINT8 HeciTimeouts; -/** Offset 0x020C - HECI1 BAR address +/** Offset 0x0210 - HECI1 BAR address BAR address of HECI1 **/ UINT32 Heci1BarAddress; -/** Offset 0x0210 - HECI2 BAR address +/** Offset 0x0214 - HECI2 BAR address BAR address of HECI2 **/ UINT32 Heci2BarAddress; -/** Offset 0x0214 - HECI3 BAR address +/** Offset 0x0218 - HECI3 BAR address BAR address of HECI3 **/ UINT32 Heci3BarAddress; -/** Offset 0x0218 - HG dGPU Power Delay +/** Offset 0x021C - HG dGPU Power Delay HG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is 300=300 microseconds **/ UINT16 HgDelayAfterPwrEn; -/** Offset 0x021A - HG dGPU Reset Delay +/** Offset 0x021E - HG dGPU Reset Delay HG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 microseconds **/ UINT16 HgDelayAfterHoldReset; -/** Offset 0x021C - MMIO size adjustment for AUTO mode +/** Offset 0x0220 - MMIO size adjustment for AUTO mode Positive number means increasing MMIO size, Negative value means decreasing MMIO size: 0 (Default)=no change to AUTO mode MMIO size **/ UINT16 MmioSizeAdjustment; -/** Offset 0x021E - PCIe ASPM programming will happen in relation to the Oprom +/** Offset 0x0222 - PCIe ASPM programming will happen in relation to the Oprom Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume @@ -792,28 +804,28 @@ **/ UINT8 InitPcieAspmAfterOprom; -/** Offset 0x021F - Selection of the primary display device +/** Offset 0x0223 - Selection of the primary display device 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Hybrid Graphics 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Hybrid Graphics **/ UINT8 PrimaryDisplay; -/** Offset 0x0220 - Selection of PSMI Region size +/** Offset 0x0224 - Selection of PSMI Region size 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB **/ UINT8 PsmiRegionSize; -/** Offset 0x0221 - Reserved +/** Offset 0x0225 - Reserved **/ - UINT8 Reserved7[3]; + UINT8 Reserved10[3]; -/** Offset 0x0224 - Temporary MMIO address for GMADR +/** Offset 0x0228 - Temporary MMIO address for GMADR Obsolete field now and it has been extended to 64 bit address, used GmAdr64 **/ UINT32 GmAdr; -/** Offset 0x0228 - Temporary MMIO address for GTTMMADR +/** Offset 0x022C - Temporary MMIO address for GTTMMADR The reference code will use this as Temporary MMIO address space to access GTTMMADR Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO @@ -821,234 +833,234 @@ **/ UINT32 GttMmAdr; -/** Offset 0x022C - Selection of iGFX GTT Memory size +/** Offset 0x0230 - Selection of iGFX GTT Memory size 1=2MB, 2=4MB, 3=8MB, Default is 3 1:2MB, 2:4MB, 3:8MB **/ UINT16 GttSize; -/** Offset 0x022E - Hybrid Graphics GPIO information for PEG 0 +/** Offset 0x0232 - Hybrid Graphics GPIO information for PEG 0 Hybrid Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs **/ UINT8 CpuPcie0Rtd3Gpio[24]; -/** Offset 0x0246 - Enable/Disable MRC TXT dependency +/** Offset 0x024A - Enable/Disable MRC TXT dependency When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization $EN_DIS **/ UINT8 TxtImplemented; -/** Offset 0x0247 - Enable/Disable SA OcSupport +/** Offset 0x024B - Enable/Disable SA OcSupport Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport $EN_DIS **/ UINT8 SaOcSupport; -/** Offset 0x0248 - GT slice Voltage Mode +/** Offset 0x024C - GT slice Voltage Mode 0(Default): Adaptive, 1: Override 0: Adaptive, 1: Override **/ UINT8 GtVoltageMode; -/** Offset 0x0249 - Maximum GTs turbo ratio override +/** Offset 0x024D - Maximum GTs turbo ratio override 0(Default)=Minimal/Auto, 60=Maximum **/ UINT8 GtMaxOcRatio; -/** Offset 0x024A - The voltage offset applied to GT slice +/** Offset 0x024E - The voltage offset applied to GT slice 0(Default)=Minimal, 1000=Maximum **/ UINT16 GtVoltageOffset; -/** Offset 0x024C - The GT slice voltage override which is applied to the entire range of GT frequencies +/** Offset 0x0250 - The GT slice voltage override which is applied to the entire range of GT frequencies 0(Default)=Minimal, 2000=Maximum **/ UINT16 GtVoltageOverride; -/** Offset 0x024E - adaptive voltage applied during turbo frequencies +/** Offset 0x0252 - adaptive voltage applied during turbo frequencies 0(Default)=Minimal, 2000=Maximum **/ UINT16 GtExtraTurboVoltage; -/** Offset 0x0250 - voltage offset applied to the SA +/** Offset 0x0254 - voltage offset applied to the SA 0(Default)=Minimal, 1000=Maximum **/ UINT16 SaVoltageOffset; -/** Offset 0x0252 - PCIe root port Function number for Hybrid Graphics dGPU +/** Offset 0x0256 - PCIe root port Function number for Hybrid Graphics dGPU Root port Index number to indicate which PCIe root port has dGPU **/ UINT8 RootPortIndex; -/** Offset 0x0253 - Realtime Memory Timing +/** Offset 0x0257 - Realtime Memory Timing 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform realtime memory timing changes after MRC_DONE. 0: Disabled, 1: Enabled **/ UINT8 RealtimeMemoryTiming; -/** Offset 0x0254 - iTBT PCIe Multiple Segment setting +/** Offset 0x0258 - iTBT PCIe Multiple Segment setting DEPRECATED $EN_DIS **/ UINT8 PcieMultipleSegmentEnabled; -/** Offset 0x0255 - Enable/Disable SA IPU +/** Offset 0x0259 - Enable/Disable SA IPU Enable(Default): Enable SA IPU, Disable: Disable SA IPU $EN_DIS **/ UINT8 SaIpuEnable; -/** Offset 0x0256 - Lane Used of CSI port +/** Offset 0x025A - Lane Used of CSI port Lane Used of each CSI port 1:x1, 2:x2, 3:x3, 4:x4, 8:x8 **/ UINT8 IpuLaneUsed[8]; -/** Offset 0x025E - Lane Used of CSI port +/** Offset 0x0262 - Lane Used of CSI port Speed of each CSI port 0:Sensor default, 1:<416Mbps, 2:<1.5Gbps, 3:<2Gbps, 4:<2.5Gbps, 5:<4Gbps, 6:>4Gbps **/ UINT8 CsiSpeed[8]; -/** Offset 0x0266 - IMGU CLKOUT Configuration +/** Offset 0x026A - IMGU CLKOUT Configuration The configuration of IMGU CLKOUT, 0: Disable;1: Enable. $EN_DIS **/ UINT8 ImguClkOutEn[6]; -/** Offset 0x026C - Enable PCIE RP Mask +/** Offset 0x0270 - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 CpuPcieRpEnableMask; -/** Offset 0x0270 - Assertion on Link Down GPIOs +/** Offset 0x0274 - Assertion on Link Down GPIOs GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs 0:Disable, 1:Enable **/ UINT8 CpuPcieRpLinkDownGpios; -/** Offset 0x0271 - Enable ClockReq Messaging +/** Offset 0x0275 - Enable ClockReq Messaging ClockReq Messaging. Disabled(0x0): Disable ClockReq Messaging, Enabled(0x1)(Default): Enable ClockReq Messaging 0:Disable, 1:Enable **/ UINT8 CpuPcieRpClockReqMsgEnable[3]; -/** Offset 0x0274 - PCIE RP Pcie Speed +/** Offset 0x0278 - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 (see: CPU_PCIE_SPEED). **/ UINT8 CpuPcieRpPcieSpeed[4]; -/** Offset 0x0278 - Selection of PSMI Support On/Off +/** Offset 0x027C - Selection of PSMI Support On/Off 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support $EN_DIS **/ UINT8 GtPsmiSupport; -/** Offset 0x0279 - Program GPIOs for LFP on DDI port-A device +/** Offset 0x027D - Program GPIOs for LFP on DDI port-A device 0=Disabled,1(Default)=eDP, 2=MIPI DSI 0:Disabled, 1:eDP, 2:MIPI DSI **/ UINT8 DdiPortAConfig; -/** Offset 0x027A - Program GPIOs for LFP on DDI port-B device +/** Offset 0x027E - Program GPIOs for LFP on DDI port-B device 0(Default)=Disabled,1=eDP, 2=MIPI DSI 0:Disabled, 1:eDP, 2:MIPI DSI **/ UINT8 DdiPortBConfig; -/** Offset 0x027B - Enable or disable HPD of DDI port A +/** Offset 0x027F - Enable or disable HPD of DDI port A 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortAHpd; -/** Offset 0x027C - Enable or disable HPD of DDI port B +/** Offset 0x0280 - Enable or disable HPD of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortBHpd; -/** Offset 0x027D - Enable or disable HPD of DDI port C +/** Offset 0x0281 - Enable or disable HPD of DDI port C 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortCHpd; -/** Offset 0x027E - Enable or disable HPD of DDI port 1 +/** Offset 0x0282 - Enable or disable HPD of DDI port 1 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPort1Hpd; -/** Offset 0x027F - Enable or disable HPD of DDI port 2 +/** Offset 0x0283 - Enable or disable HPD of DDI port 2 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort2Hpd; -/** Offset 0x0280 - Enable or disable HPD of DDI port 3 +/** Offset 0x0284 - Enable or disable HPD of DDI port 3 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort3Hpd; -/** Offset 0x0281 - Enable or disable HPD of DDI port 4 +/** Offset 0x0285 - Enable or disable HPD of DDI port 4 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort4Hpd; -/** Offset 0x0282 - Enable or disable DDC of DDI port A +/** Offset 0x0286 - Enable or disable DDC of DDI port A 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortADdc; -/** Offset 0x0283 - Enable or disable DDC of DDI port B +/** Offset 0x0287 - Enable or disable DDC of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 DdiPortBDdc; -/** Offset 0x0284 - Enable or disable DDC of DDI port C +/** Offset 0x0288 - Enable or disable DDC of DDI port C 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPortCDdc; -/** Offset 0x0285 - Enable DDC setting of DDI Port 1 +/** Offset 0x0289 - Enable DDC setting of DDI Port 1 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort1Ddc; -/** Offset 0x0286 - Enable DDC setting of DDI Port 2 +/** Offset 0x028A - Enable DDC setting of DDI Port 2 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort2Ddc; -/** Offset 0x0287 - Enable DDC setting of DDI Port 3 +/** Offset 0x028B - Enable DDC setting of DDI Port 3 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort3Ddc; -/** Offset 0x0288 - Enable DDC setting of DDI Port 4 +/** Offset 0x028C - Enable DDC setting of DDI Port 4 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 DdiPort4Ddc; -/** Offset 0x0289 - Reserved +/** Offset 0x028D - Reserved **/ - UINT8 Reserved8[7]; + UINT8 Reserved11[3]; /** Offset 0x0290 - Temporary MMIO address for GMADR The reference code will use this as Temporary MMIO address space to access GMADR @@ -1074,7 +1086,7 @@ /** Offset 0x029B - Reserved **/ - UINT8 Reserved9; + UINT8 Reserved12; /** Offset 0x029C - SA/Uncore Voltage Override The SA/Uncore voltage override applicable when SA/Uncore voltage mode is in Override @@ -1105,47 +1117,47 @@ /** Offset 0x02A2 - Reserved **/ - UINT8 Reserved10; + UINT8 Reserved13; /** Offset 0x02A3 - Reserved **/ - UINT8 Reserved11; + UINT8 Reserved14; /** Offset 0x02A4 - Reserved **/ - UINT16 Reserved12; + UINT16 Reserved15; /** Offset 0x02A6 - Reserved **/ - UINT16 Reserved13; + UINT16 Reserved16; /** Offset 0x02A8 - Reserved **/ - UINT8 Reserved14[4]; + UINT8 Reserved17[4]; /** Offset 0x02AC - Reserved **/ - UINT8 Reserved15; + UINT8 Reserved18; /** Offset 0x02AD - Reserved **/ - UINT8 Reserved16; + UINT8 Reserved19; /** Offset 0x02AE - Reserved **/ - UINT8 Reserved17; + UINT8 Reserved20; /** Offset 0x02AF - Reserved **/ - UINT8 Reserved18; + UINT8 Reserved21; /** Offset 0x02B0 - Reserved **/ - UINT8 Reserved19; + UINT8 Reserved22; /** Offset 0x02B1 - Reserved **/ - UINT8 Reserved20[96]; + UINT8 Reserved23[96]; /** Offset 0x0311 - Enable Gt CLOS 0(Default)=Disable, 1=Enable @@ -1315,51 +1327,51 @@ /** Offset 0x037B - Reserved **/ - UINT8 Reserved21[8]; + UINT8 Reserved24[8]; /** Offset 0x0383 - Reserved **/ - UINT8 Reserved22[8]; + UINT8 Reserved25[8]; /** Offset 0x038B - Reserved **/ - UINT8 Reserved23; + UINT8 Reserved26; /** Offset 0x038C - Reserved **/ - UINT8 Reserved24; + UINT8 Reserved27; /** Offset 0x038D - Reserved **/ - UINT8 Reserved25; + UINT8 Reserved28; /** Offset 0x038E - Reserved **/ - UINT8 Reserved26[8]; + UINT8 Reserved29[8]; /** Offset 0x0396 - Reserved **/ - UINT8 Reserved27; + UINT8 Reserved30; /** Offset 0x0397 - Reserved **/ - UINT8 Reserved28; + UINT8 Reserved31; /** Offset 0x0398 - Reserved **/ - UINT8 Reserved29[8]; + UINT8 Reserved32[8]; /** Offset 0x03A0 - Reserved **/ - UINT8 Reserved30[8]; + UINT8 Reserved33[8]; /** Offset 0x03A8 - Reserved **/ - UINT8 Reserved31; + UINT8 Reserved34; /** Offset 0x03A9 - Reserved **/ - UINT8 Reserved32[8]; + UINT8 Reserved35[8]; /** Offset 0x03B1 - DMI ASPM Control Configuration:{Combo Set ASPM Control configuration @@ -1516,7 +1528,7 @@ /** Offset 0x03CD - Reserved **/ - UINT8 Reserved33; + UINT8 Reserved36; /** Offset 0x03CE - Ring Downbin Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always @@ -1539,7 +1551,7 @@ /** Offset 0x03D1 - Reserved **/ - UINT8 Reserved34; + UINT8 Reserved37; /** Offset 0x03D2 - Ring voltage override The ring voltage override which is applied to the entire range of cpu ring frequencies. @@ -1585,47 +1597,47 @@ /** Offset 0x03DC - Reserved **/ - UINT8 Reserved35; + UINT8 Reserved38; /** Offset 0x03DD - Reserved **/ - UINT8 Reserved36; + UINT8 Reserved39; /** Offset 0x03DE - Reserved **/ - UINT16 Reserved37; + UINT16 Reserved40; /** Offset 0x03E0 - Reserved **/ - UINT16 Reserved38; + UINT16 Reserved41; /** Offset 0x03E2 - Reserved **/ - UINT16 Reserved39; + UINT16 Reserved42; /** Offset 0x03E4 - Reserved **/ - UINT16 Reserved40[4]; + UINT16 Reserved43[4]; /** Offset 0x03EC - Reserved **/ - UINT8 Reserved41[4]; + UINT8 Reserved44[4]; /** Offset 0x03F0 - Reserved **/ - UINT8 Reserved42; + UINT8 Reserved45; /** Offset 0x03F1 - Reserved **/ - UINT8 Reserved43; + UINT8 Reserved46; /** Offset 0x03F2 - Reserved **/ - UINT8 Reserved44; + UINT8 Reserved47; /** Offset 0x03F3 - Reserved **/ - UINT8 Reserved45; + UINT8 Reserved48; /** Offset 0x03F4 - Core VF Point Offset Mode Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes. @@ -1637,7 +1649,7 @@ /** Offset 0x03F5 - Reserved **/ - UINT8 Reserved46[1]; + UINT8 Reserved49[1]; /** Offset 0x03F6 - Core VF Point Offset Array used to specifies the Core Voltage Offset applied to the each selected VF @@ -1664,15 +1676,15 @@ /** Offset 0x0433 - Reserved **/ - UINT8 Reserved47; + UINT8 Reserved50; /** Offset 0x0434 - Reserved **/ - UINT16 Reserved48[8]; + UINT16 Reserved51[8]; /** Offset 0x0444 - Reserved **/ - UINT8 Reserved49[8]; + UINT8 Reserved52[8]; /** Offset 0x044C - Per Core Max Ratio override Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new @@ -1688,11 +1700,11 @@ /** Offset 0x0455 - Reserved **/ - UINT8 Reserved50[4]; + UINT8 Reserved53[4]; /** Offset 0x0459 - Reserved **/ - UINT8 Reserved51; + UINT8 Reserved54; /** Offset 0x045A - Pvd Ratio Threshold Select PVD Ratio Threshold Value from Range 1 to 40. 0 - Auto/Default. @@ -1714,23 +1726,23 @@ /** Offset 0x045D - Reserved **/ - UINT8 Reserved52; + UINT8 Reserved55; /** Offset 0x045E - Reserved **/ - UINT16 Reserved53[15]; + UINT16 Reserved56[15]; /** Offset 0x047C - Reserved **/ - UINT8 Reserved54[15]; + UINT8 Reserved57[15]; /** Offset 0x048B - Reserved **/ - UINT8 Reserved55[15]; + UINT8 Reserved58[15]; /** Offset 0x049A - Reserved **/ - UINT8 Reserved56; + UINT8 Reserved59; /** Offset 0x049B - BCLK Frequency Source Clock source of BCLK OC frequency, 1:CPU BCLK, 2:PCH BCLK, 3:External CLK @@ -1747,7 +1759,7 @@ /** Offset 0x049D - Reserved **/ - UINT8 Reserved57[3]; + UINT8 Reserved60[3]; /** Offset 0x04A0 - CPU BCLK OC Frequency CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0 @@ -1757,91 +1769,91 @@ /** Offset 0x04A4 - Reserved **/ - UINT32 Reserved58; + UINT32 Reserved61; /** Offset 0x04A8 - Reserved **/ - UINT32 Reserved59; + UINT32 Reserved62; /** Offset 0x04AC - Reserved **/ - UINT8 Reserved60; + UINT8 Reserved63; /** Offset 0x04AD - Reserved **/ - UINT8 Reserved61; + UINT8 Reserved64; /** Offset 0x04AE - Reserved **/ - UINT8 Reserved62; + UINT8 Reserved65; /** Offset 0x04AF - Reserved **/ - UINT8 Reserved63; + UINT8 Reserved66; /** Offset 0x04B0 - Reserved **/ - UINT16 Reserved64; + UINT16 Reserved67; /** Offset 0x04B2 - Reserved **/ - UINT8 Reserved65; + UINT8 Reserved68; /** Offset 0x04B3 - Reserved **/ - UINT8 Reserved66; + UINT8 Reserved69; /** Offset 0x04B4 - Reserved **/ - UINT16 Reserved67; + UINT16 Reserved70; /** Offset 0x04B6 - Reserved **/ - UINT8 Reserved68; + UINT8 Reserved71; /** Offset 0x04B7 - Reserved **/ - UINT8 Reserved69; + UINT8 Reserved72; /** Offset 0x04B8 - Reserved **/ - UINT8 Reserved70; + UINT8 Reserved73; /** Offset 0x04B9 - Reserved **/ - UINT8 Reserved71; + UINT8 Reserved74; /** Offset 0x04BA - Reserved **/ - UINT8 Reserved72; + UINT8 Reserved75; /** Offset 0x04BB - Reserved **/ - UINT8 Reserved73; + UINT8 Reserved76; /** Offset 0x04BC - Reserved **/ - UINT8 Reserved74; + UINT8 Reserved77; /** Offset 0x04BD - Reserved **/ - UINT8 Reserved75[3]; + UINT8 Reserved78[3]; /** Offset 0x04C0 - Reserved **/ - UINT32 Reserved76; + UINT32 Reserved79; /** Offset 0x04C4 - Reserved **/ - UINT8 Reserved77; + UINT8 Reserved80; /** Offset 0x04C5 - Reserved **/ - UINT8 Reserved78; + UINT8 Reserved81; /** Offset 0x04C6 - Reserved **/ - UINT8 Reserved79[6]; + UINT8 Reserved82[6]; /** Offset 0x04CC - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable @@ -1861,7 +1873,7 @@ /** Offset 0x04CF - Reserved **/ - UINT8 Reserved80; + UINT8 Reserved83; /** Offset 0x04D0 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -1925,7 +1937,7 @@ /** Offset 0x0509 - Reserved **/ - UINT8 Reserved81[32]; + UINT8 Reserved84[32]; /** Offset 0x0529 - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. @@ -2112,7 +2124,7 @@ /** Offset 0x0745 - Reserved **/ - UINT8 Reserved82; + UINT8 Reserved85; /** Offset 0x0746 - SMBUS Base Address SMBUS Base Address (IO space). @@ -2133,7 +2145,7 @@ /** Offset 0x075B - Reserved **/ - UINT8 Reserved83[14]; + UINT8 Reserved86[14]; /** Offset 0x0769 - ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc @@ -2142,19 +2154,19 @@ /** Offset 0x077B - Reserved **/ - UINT8 Reserved84[14]; + UINT8 Reserved87[14]; /** Offset 0x0789 - Reserved **/ - UINT8 Reserved85[3]; + UINT8 Reserved88[3]; /** Offset 0x078C - Reserved **/ - UINT32 Reserved86[18]; + UINT32 Reserved89[18]; /** Offset 0x07D4 - Reserved **/ - UINT32 Reserved87; + UINT32 Reserved90; /** Offset 0x07D8 - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 @@ -2216,7 +2228,7 @@ /** Offset 0x07F5 - Reserved **/ - UINT8 Reserved88[3]; + UINT8 Reserved91[3]; /** Offset 0x07F8 - DMIC<N> Data Pin Muxing Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* @@ -2278,7 +2290,7 @@ /** Offset 0x0811 - Reserved **/ - UINT8 Reserved89[3]; + UINT8 Reserved92[3]; /** Offset 0x0814 - Serial Io Uart Debug BaudRate Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, @@ -2306,7 +2318,7 @@ /** Offset 0x081B - Reserved **/ - UINT8 Reserved90; + UINT8 Reserved93; /** Offset 0x081C - Serial Io Uart Debug Mmio Base Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode @@ -2626,7 +2638,7 @@ /** Offset 0x0854 - Reserved **/ - UINT8 Reserved91; + UINT8 Reserved94; /** Offset 0x0855 - Extern Therm Status Enables/Disable Extern Therm Status @@ -2666,7 +2678,7 @@ /** Offset 0x085B - Reserved **/ - UINT8 Reserved92; + UINT8 Reserved95; /** Offset 0x085C - Exit On Failure (MRC) Enables/Disable Exit On Failure (MRC) @@ -2772,11 +2784,11 @@ /** Offset 0x086D - Reserved **/ - UINT8 Reserved93; + UINT8 Reserved96; /** Offset 0x086E - Reserved **/ - UINT8 Reserved94; + UINT8 Reserved97; /** Offset 0x086F - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP @@ -2835,7 +2847,7 @@ /** Offset 0x087E - Reserved **/ - UINT8 Reserved95; + UINT8 Reserved98; /** Offset 0x087F - Idle Energy Mc0Ch0Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) @@ -3045,11 +3057,11 @@ /** Offset 0x08A8 - Reserved **/ - UINT8 Reserved96; + UINT8 Reserved99; /** Offset 0x08A9 - Reserved **/ - UINT8 Reserved97; + UINT8 Reserved100; /** Offset 0x08AA - Rapl Power Floor Ch0 Power budget ,range[255;0],(0= 5.3W Def) @@ -3081,7 +3093,7 @@ /** Offset 0x08AF - Reserved **/ - UINT8 Reserved98; + UINT8 Reserved101; /** Offset 0x08B0 - User Manual Threshold Disabled: Predefined threshold will be used.\n @@ -3155,7 +3167,7 @@ /** Offset 0x08BB - Reserved **/ - UINT8 Reserved99; + UINT8 Reserved102; /** Offset 0x08BC - Post Code Output Port This option configures Post Code Output Port @@ -3182,7 +3194,7 @@ /** Offset 0x08C1 - Reserved **/ - UINT8 Reserved100[3]; + UINT8 Reserved103[3]; /** Offset 0x08C4 - BCLK RFI Frequency Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No @@ -3232,15 +3244,15 @@ /** Offset 0x08DB - Reserved **/ - UINT8 Reserved101; + UINT8 Reserved104; /** Offset 0x08DC - Reserved **/ - UINT8 Reserved102; + UINT8 Reserved105; /** Offset 0x08DD - Reserved **/ - UINT8 Reserved103; + UINT8 Reserved106; /** Offset 0x08DE - REFRESH_PANIC_WM DEPRECATED @@ -3266,39 +3278,39 @@ /** Offset 0x08E2 - Reserved **/ - UINT8 Reserved104; + UINT8 Reserved107; /** Offset 0x08E3 - Reserved **/ - UINT8 Reserved105; + UINT8 Reserved108; /** Offset 0x08E4 - Reserved **/ - UINT8 Reserved106; + UINT8 Reserved109; /** Offset 0x08E5 - Reserved **/ - UINT8 Reserved107; + UINT8 Reserved110; /** Offset 0x08E6 - Reserved **/ - UINT8 Reserved108; + UINT8 Reserved111; /** Offset 0x08E7 - Reserved **/ - UINT8 Reserved109; + UINT8 Reserved112; /** Offset 0x08E8 - Reserved **/ - UINT8 Reserved110; + UINT8 Reserved113; /** Offset 0x08E9 - Reserved **/ - UINT8 Reserved111; + UINT8 Reserved114; /** Offset 0x08EA - Reserved **/ - UINT8 Reserved112; + UINT8 Reserved115; /** Offset 0x08EB - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -3321,7 +3333,7 @@ /** Offset 0x08EE - Reserved **/ - UINT8 Reserved113; + UINT8 Reserved116; /** Offset 0x08EF - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of @@ -3338,7 +3350,7 @@ /** Offset 0x08F1 - Reserved **/ - UINT8 Reserved114[3]; + UINT8 Reserved117[3]; /** Offset 0x08F4 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot @@ -3352,31 +3364,31 @@ /** Offset 0x08F9 - Reserved **/ - UINT8 Reserved115; + UINT8 Reserved118; /** Offset 0x08FA - Reserved **/ - UINT16 Reserved116; + UINT16 Reserved119; /** Offset 0x08FC - Reserved **/ - UINT8 Reserved117; + UINT8 Reserved120; /** Offset 0x08FD - Reserved **/ - UINT8 Reserved118; + UINT8 Reserved121; /** Offset 0x08FE - Reserved **/ - UINT8 Reserved119; + UINT8 Reserved122; /** Offset 0x08FF - Reserved **/ - UINT8 Reserved120[88]; + UINT8 Reserved123[88]; /** Offset 0x0957 - Reserved **/ - UINT8 Reserved121; + UINT8 Reserved124; /** Offset 0x0958 - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable @@ -3392,7 +3404,7 @@ /** Offset 0x095C - Reserved **/ - UINT8 Reserved122[12]; + UINT8 Reserved125[12]; /** Offset 0x0968 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. @@ -3458,7 +3470,7 @@ /** Offset 0x0972 - Reserved **/ - UINT8 Reserved123[2]; + UINT8 Reserved126[2]; /** Offset 0x0974 - Hybrid Graphics GPIO information for PEG 1 Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs @@ -3495,7 +3507,7 @@ /** Offset 0x0A97 - Reserved **/ - UINT8 Reserved124; + UINT8 Reserved127; /** Offset 0x0A98 - SerialIoUartDebugRxPinMux - FSPT Select RX pin muxing for SerialIo UART used for debug @@ -3521,183 +3533,183 @@ /** Offset 0x0AA8 - Reserved **/ - UINT8 Reserved125; + UINT8 Reserved128; /** Offset 0x0AA9 - Reserved **/ - UINT8 Reserved126; + UINT8 Reserved129; /** Offset 0x0AAA - Reserved **/ - UINT16 Reserved127; + UINT16 Reserved130; /** Offset 0x0AAC - Reserved **/ - UINT8 Reserved128[4]; + UINT8 Reserved131[4]; /** Offset 0x0AB0 - Reserved **/ - UINT8 Reserved129; + UINT8 Reserved132; /** Offset 0x0AB1 - Reserved **/ - UINT8 Reserved130; + UINT8 Reserved133; /** Offset 0x0AB2 - Reserved **/ - UINT8 Reserved131[6]; + UINT8 Reserved134[6]; /** Offset 0x0AB8 - Reserved **/ - UINT64 Reserved132; + UINT64 Reserved135; /** Offset 0x0AC0 - Reserved **/ - UINT64 Reserved133; + UINT64 Reserved136; /** Offset 0x0AC8 - Reserved **/ - UINT32 Reserved134; + UINT32 Reserved137; /** Offset 0x0ACC - Reserved **/ - UINT8 Reserved135[8]; + UINT8 Reserved138[8]; /** Offset 0x0AD4 - Reserved **/ - UINT8 Reserved136; + UINT8 Reserved139; /** Offset 0x0AD5 - Reserved **/ - UINT8 Reserved137[3]; + UINT8 Reserved140[3]; /** Offset 0x0AD8 - Reserved **/ - UINT32 Reserved138; + UINT32 Reserved141; /** Offset 0x0ADC - Reserved **/ - UINT32 Reserved139; + UINT32 Reserved142; /** Offset 0x0AE0 - Reserved **/ - UINT16 Reserved140; + UINT16 Reserved143; /** Offset 0x0AE2 - Reserved **/ - UINT16 Reserved141; + UINT16 Reserved144; /** Offset 0x0AE4 - Reserved **/ - UINT16 Reserved142; + UINT16 Reserved145; /** Offset 0x0AE6 - Reserved **/ - UINT8 Reserved143; + UINT8 Reserved146; /** Offset 0x0AE7 - Reserved **/ - UINT8 Reserved144; + UINT8 Reserved147; /** Offset 0x0AE8 - Reserved **/ - UINT8 Reserved145; + UINT8 Reserved148; /** Offset 0x0AE9 - Reserved **/ - UINT8 Reserved146; + UINT8 Reserved149; /** Offset 0x0AEA - Reserved **/ - UINT8 Reserved147; + UINT8 Reserved150; /** Offset 0x0AEB - Reserved **/ - UINT8 Reserved148[5]; + UINT8 Reserved151[5]; /** Offset 0x0AF0 - Reserved **/ - UINT64 Reserved149; + UINT64 Reserved152; /** Offset 0x0AF8 - Reserved **/ - UINT64 Reserved150; + UINT64 Reserved153; /** Offset 0x0B00 - Reserved **/ - UINT32 Reserved151; + UINT32 Reserved154; /** Offset 0x0B04 - Reserved **/ - UINT16 Reserved152; + UINT16 Reserved155; /** Offset 0x0B06 - Reserved **/ - UINT8 Reserved153; + UINT8 Reserved156; /** Offset 0x0B07 - Reserved **/ - UINT8 Reserved154; + UINT8 Reserved157; /** Offset 0x0B08 - Reserved **/ - UINT8 Reserved155; + UINT8 Reserved158; /** Offset 0x0B09 - Reserved **/ - UINT8 Reserved156; + UINT8 Reserved159; /** Offset 0x0B0A - Reserved **/ - UINT8 Reserved157; + UINT8 Reserved160; /** Offset 0x0B0B - Reserved **/ - UINT8 Reserved158; + UINT8 Reserved161; /** Offset 0x0B0C - Reserved **/ - UINT8 Reserved159; + UINT8 Reserved162; /** Offset 0x0B0D - Reserved **/ - UINT8 Reserved160; + UINT8 Reserved163; /** Offset 0x0B0E - Reserved **/ - UINT16 Reserved161; + UINT16 Reserved164; /** Offset 0x0B10 - Reserved **/ - UINT16 Reserved162; + UINT16 Reserved165; /** Offset 0x0B12 - Reserved **/ - UINT16 Reserved163; + UINT16 Reserved166; /** Offset 0x0B14 - Reserved **/ - UINT16 Reserved164; + UINT16 Reserved167; /** Offset 0x0B16 - Reserved **/ - UINT8 Reserved165[8]; + UINT8 Reserved168[8]; /** Offset 0x0B1E - Reserved **/ - UINT8 Reserved166[8]; + UINT8 Reserved169[8]; /** Offset 0x0B26 - Reserved **/ - UINT16 Reserved167; + UINT16 Reserved170; /** Offset 0x0B28 - Reserved **/ - UINT8 Reserved168; + UINT8 Reserved171; /** Offset 0x0B29 - Reserved **/ - UINT8 Reserved169; + UINT8 Reserved172; /** Offset 0x0B2A - LP5 Bank Mode LP5 Bank Mode. 0: Auto, 1: 8 Bank Mode, 2: 16 Bank Mode, 3: BG Mode, default is 0 @@ -3707,23 +3719,27 @@ /** Offset 0x0B2B - Reserved **/ - UINT8 Reserved170; + UINT8 Reserved173; /** Offset 0x0B2C - Reserved **/ - UINT8 Reserved171; + UINT8 Reserved174; /** Offset 0x0B2D - Reserved **/ - UINT8 Reserved172; + UINT8 Reserved175; /** Offset 0x0B2E - Reserved **/ - UINT8 Reserved173[5]; + UINT8 Reserved176; -/** Offset 0x0B33 - Reserved +/** Offset 0x0B2F - Reserved **/ - UINT8 Reserved174[5]; + UINT8 Reserved177[5]; + +/** Offset 0x0B34 - Reserved +**/ + UINT8 Reserved178[4]; } FSP_M_CONFIG; /** Fsp M UPD Configuration @@ -3744,7 +3760,7 @@ /** Offset 0x0B38 **/ - UINT8 UnusedUpdSpace33[6]; + UINT8 Rsvd37[6]; /** Offset 0x0B3E **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h index a05fa35..4960bc53 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h @@ -1721,841 +1721,849 @@ /** Offset 0x06D0 - Reserved **/ - UINT32 Reserved50; + UINT8 Reserved50[3]; + +/** Offset 0x06D3 - Reserved +**/ + UINT8 Reserved51; /** Offset 0x06D4 - Reserved **/ - UINT32 Reserved51; + UINT32 Reserved52; /** Offset 0x06D8 - Reserved **/ - UINT32 Reserved52; + UINT32 Reserved53; /** Offset 0x06DC - Reserved **/ - UINT32 Reserved53; + UINT32 Reserved54; /** Offset 0x06E0 - Reserved **/ - UINT8 Reserved54[11]; + UINT32 Reserved55; -/** Offset 0x06EB - Enable Power Optimizer +/** Offset 0x06E4 - Reserved +**/ + UINT8 Reserved56[11]; + +/** Offset 0x06EF - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. $EN_DIS **/ UINT8 PchPwrOptEnable; -/** Offset 0x06EC - PCH Flash Protection Ranges Write Enble +/** Offset 0x06F0 - PCH Flash Protection Ranges Write Enble Write or erase is blocked by hardware. **/ UINT8 PchWriteProtectionEnable[5]; -/** Offset 0x06F1 - PCH Flash Protection Ranges Read Enble +/** Offset 0x06F5 - PCH Flash Protection Ranges Read Enble Read is blocked by hardware. **/ UINT8 PchReadProtectionEnable[5]; -/** Offset 0x06F6 - PCH Protect Range Limit +/** Offset 0x06FA - PCH Protect Range Limit Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison. **/ UINT16 PchProtectedRangeLimit[5]; -/** Offset 0x0700 - PCH Protect Range Base +/** Offset 0x0704 - PCH Protect Range Base Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. **/ UINT16 PchProtectedRangeBase[5]; -/** Offset 0x070A - Enable Pme +/** Offset 0x070E - Enable Pme Enable Azalia wake-on-ring. $EN_DIS **/ UINT8 PchHdaPme; -/** Offset 0x070B - HD Audio Link Frequency +/** Offset 0x070F - HD Audio Link Frequency HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. 0: 6MHz, 1: 12MHz, 2: 24MHz **/ UINT8 PchHdaLinkFrequency; -/** Offset 0x070C - Enable PCH ISH SPI Cs0 pins assigned +/** Offset 0x0710 - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshSpiCs0Enable[1]; -/** Offset 0x070D - Enable PCH Io Apic Entry 24-119 +/** Offset 0x0711 - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIoApicEntry24_119; -/** Offset 0x070E - PCH Io Apic ID +/** Offset 0x0712 - PCH Io Apic ID This member determines IOAPIC ID. Default is 0x02. **/ UINT8 PchIoApicId; -/** Offset 0x070F - Enable PCH ISH SPI pins assigned +/** Offset 0x0713 - Enable PCH ISH SPI pins assigned Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshSpiEnable[1]; -/** Offset 0x0710 - Enable PCH ISH UART pins assigned +/** Offset 0x0714 - Enable PCH ISH UART pins assigned Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshUartEnable[2]; -/** Offset 0x0712 - Enable PCH ISH I2C pins assigned +/** Offset 0x0716 - Enable PCH ISH I2C pins assigned Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshI2cEnable[3]; -/** Offset 0x0715 - Enable PCH ISH GP pins assigned +/** Offset 0x0719 - Enable PCH ISH GP pins assigned Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshGpEnable[8]; -/** Offset 0x071D - PCH ISH PDT Unlock Msg +/** Offset 0x0721 - PCH ISH PDT Unlock Msg 0: False; 1: True. $EN_DIS **/ UINT8 PchIshPdtUnlock; -/** Offset 0x071E - Enable PCH Lan LTR capabilty of PCH internal LAN +/** Offset 0x0722 - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchLanLtrEnable; -/** Offset 0x071F - Enable LOCKDOWN BIOS LOCK +/** Offset 0x0723 - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection. $EN_DIS **/ UINT8 PchLockDownBiosLock; -/** Offset 0x0720 - PCH Compatibility Revision ID +/** Offset 0x0724 - PCH Compatibility Revision ID This member describes whether or not the CRID feature of PCH should be enabled. $EN_DIS **/ UINT8 PchCrid; -/** Offset 0x0721 - RTC BIOS Interface Lock +/** Offset 0x0725 - RTC BIOS Interface Lock Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed. $EN_DIS **/ UINT8 RtcBiosInterfaceLock; -/** Offset 0x0722 - RTC Cmos Memory Lock +/** Offset 0x0726 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. $EN_DIS **/ UINT8 RtcMemoryLock; -/** Offset 0x0723 - Enable PCIE RP HotPlug +/** Offset 0x0727 - Enable PCIE RP HotPlug Indicate whether the root port is hot plug available. **/ UINT8 PcieRpHotPlug[28]; -/** Offset 0x073F - Enable PCIE RP Pm Sci +/** Offset 0x0743 - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled. **/ UINT8 PcieRpPmSci[28]; -/** Offset 0x075B - Enable PCIE RP Transmitter Half Swing +/** Offset 0x075F - Enable PCIE RP Transmitter Half Swing Indicate whether the Transmitter Half Swing is enabled. **/ UINT8 PcieRpTransmitterHalfSwing[28]; -/** Offset 0x0777 - Enable PCIE RP Clk Req Detect +/** Offset 0x077B - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. **/ UINT8 PcieRpClkReqDetect[28]; -/** Offset 0x0793 - PCIE RP Advanced Error Report +/** Offset 0x0797 - PCIE RP Advanced Error Report Indicate whether the Advanced Error Reporting is enabled. **/ UINT8 PcieRpAdvancedErrorReporting[28]; -/** Offset 0x07AF - PCIE RP Unsupported Request Report +/** Offset 0x07B3 - PCIE RP Unsupported Request Report Indicate whether the Unsupported Request Report is enabled. **/ UINT8 PcieRpUnsupportedRequestReport[28]; -/** Offset 0x07CB - PCIE RP Fatal Error Report +/** Offset 0x07CF - PCIE RP Fatal Error Report Indicate whether the Fatal Error Report is enabled. **/ UINT8 PcieRpFatalErrorReport[28]; -/** Offset 0x07E7 - PCIE RP No Fatal Error Report +/** Offset 0x07EB - PCIE RP No Fatal Error Report Indicate whether the No Fatal Error Report is enabled. **/ UINT8 PcieRpNoFatalErrorReport[28]; -/** Offset 0x0803 - PCIE RP Correctable Error Report +/** Offset 0x0807 - PCIE RP Correctable Error Report Indicate whether the Correctable Error Report is enabled. **/ UINT8 PcieRpCorrectableErrorReport[28]; -/** Offset 0x081F - PCIE RP System Error On Fatal Error +/** Offset 0x0823 - PCIE RP System Error On Fatal Error Indicate whether the System Error on Fatal Error is enabled. **/ UINT8 PcieRpSystemErrorOnFatalError[28]; -/** Offset 0x083B - PCIE RP System Error On Non Fatal Error +/** Offset 0x083F - PCIE RP System Error On Non Fatal Error Indicate whether the System Error on Non Fatal Error is enabled. **/ UINT8 PcieRpSystemErrorOnNonFatalError[28]; -/** Offset 0x0857 - PCIE RP System Error On Correctable Error +/** Offset 0x085B - PCIE RP System Error On Correctable Error Indicate whether the System Error on Correctable Error is enabled. **/ UINT8 PcieRpSystemErrorOnCorrectableError[28]; -/** Offset 0x0873 - PCIE RP Max Payload +/** Offset 0x0877 - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. **/ UINT8 PcieRpMaxPayload[28]; -/** Offset 0x088F - Touch Host Controller Port 0 Assignment +/** Offset 0x0893 - Touch Host Controller Port 0 Assignment Assign THC Port 0 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0 **/ UINT8 ThcPort0Assignment; -/** Offset 0x0890 - Touch Host Controller Port 0 Interrupt Pin Mux +/** Offset 0x0894 - Touch Host Controller Port 0 Interrupt Pin Mux Set THC Port 0 Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values. **/ UINT32 ThcPort0InterruptPinMuxing; -/** Offset 0x0894 - Reserved +/** Offset 0x0898 - Reserved **/ - UINT8 Reserved55; + UINT8 Reserved57; -/** Offset 0x0895 - Touch Host Controller Port 1 Assignment +/** Offset 0x0899 - Touch Host Controller Port 1 Assignment Assign THC Port 1 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1 **/ UINT8 ThcPort1Assignment; -/** Offset 0x0896 - Reserved +/** Offset 0x089A - Reserved **/ - UINT16 Reserved56; + UINT16 Reserved58; -/** Offset 0x0898 - Touch Host Controller Port 1 Interrupt Pin Mux +/** Offset 0x089C - Touch Host Controller Port 1 Interrupt Pin Mux Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_* for possible values. **/ UINT32 ThcPort1InterruptPinMuxing; -/** Offset 0x089C - Reserved +/** Offset 0x08A0 - Reserved **/ - UINT8 Reserved57; + UINT8 Reserved59; -/** Offset 0x089D - PCIE RP Pcie Speed +/** Offset 0x08A1 - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 (see: PCIE_SPEED). **/ UINT8 PcieRpPcieSpeed[28]; -/** Offset 0x08B9 - PCIE RP Physical Slot Number +/** Offset 0x08BD - PCIE RP Physical Slot Number Indicates the slot number for the root port. Default is the value as root port index. **/ UINT8 PcieRpPhysicalSlotNumber[28]; -/** Offset 0x08D5 - PCIE RP Completion Timeout +/** Offset 0x08D9 - PCIE RP Completion Timeout The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. **/ UINT8 PcieRpCompletionTimeout[28]; -/** Offset 0x08F1 - PCIE RP Aspm +/** Offset 0x08F5 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig. **/ UINT8 PcieRpAspm[28]; -/** Offset 0x090D - PCIE RP L1 Substates +/** Offset 0x0911 - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2. **/ UINT8 PcieRpL1Substates[28]; -/** Offset 0x0929 - Reserved +/** Offset 0x092D - Reserved **/ - UINT8 Reserved58[28]; + UINT8 Reserved60[28]; -/** Offset 0x0945 - PCIE RP Ltr Enable +/** Offset 0x0949 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. **/ UINT8 PcieRpLtrEnable[28]; -/** Offset 0x0961 - PCIE RP Ltr Config Lock +/** Offset 0x0965 - PCIE RP Ltr Config Lock 0: Disable; 1: Enable. **/ UINT8 PcieRpLtrConfigLock[28]; -/** Offset 0x097D - PCIe override default settings for EQ +/** Offset 0x0981 - PCIe override default settings for EQ Choose PCIe EQ method $EN_DIS **/ UINT8 PcieEqOverrideDefault; -/** Offset 0x097E - PCIe choose EQ method +/** Offset 0x0982 - PCIe choose EQ method Choose PCIe EQ method 0: HardwareEq, 1: FixedEq **/ UINT8 PcieEqMethod; -/** Offset 0x097F - PCIe choose EQ mode +/** Offset 0x0983 - PCIe choose EQ mode Choose PCIe EQ mode 0: PresetEq, 1: CoefficientEq **/ UINT8 PcieEqMode; -/** Offset 0x0980 - PCIe EQ local transmitter override +/** Offset 0x0984 - PCIe EQ local transmitter override Enable/Disable local transmitter override $EN_DIS **/ UINT8 PcieEqLocalTransmitterOverrideEnable; -/** Offset 0x0981 - PCIe number of valid list entries +/** Offset 0x0985 - PCIe number of valid list entries Select number of presets or coefficients depending on the mode **/ UINT8 PcieEqPh3NumberOfPresetsOrCoefficients; -/** Offset 0x0982 - PCIe pre-cursor coefficient list +/** Offset 0x0986 - PCIe pre-cursor coefficient list Provide a list of pre-cursor coefficients to be used during phase 3 EQ **/ UINT8 PcieEqPh3PreCursorList[10]; -/** Offset 0x098C - PCIe post-cursor coefficient list +/** Offset 0x0990 - PCIe post-cursor coefficient list Provide a list of post-cursor coefficients to be used during phase 3 EQ **/ UINT8 PcieEqPh3PostCursorList[10]; -/** Offset 0x0996 - PCIe preset list +/** Offset 0x099A - PCIe preset list Provide a list of presets to be used during phase 3 EQ **/ UINT8 PcieEqPh3PresetList[11]; -/** Offset 0x09A1 - Reserved +/** Offset 0x09A5 - Reserved **/ - UINT8 Reserved59; + UINT8 Reserved61; -/** Offset 0x09A2 - Reserved +/** Offset 0x09A6 - Reserved **/ - UINT16 Reserved60; + UINT16 Reserved62; -/** Offset 0x09A4 - PCIe EQ phase 1 downstream transmitter port preset +/** Offset 0x09A8 - PCIe EQ phase 1 downstream transmitter port preset Allows to select the downstream port preset value that will be used during phase 1 of equalization **/ UINT32 PcieEqPh1DownstreamPortTransmitterPreset; -/** Offset 0x09A8 - PCIe EQ phase 1 upstream tranmitter port preset +/** Offset 0x09AC - PCIe EQ phase 1 upstream tranmitter port preset Allows to select the upstream port preset value that will be used during phase 1 of equalization **/ UINT32 PcieEqPh1UpstreamPortTransmitterPreset; -/** Offset 0x09AC - PCIe EQ phase 2 local transmitter override preset +/** Offset 0x09B0 - PCIe EQ phase 2 local transmitter override preset Allows to select the value of the preset used during phase 2 local transmitter override **/ UINT8 PcieEqPh2LocalTransmitterOverridePreset; -/** Offset 0x09AD - PCIE Enable Peer Memory Write +/** Offset 0x09B1 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. $EN_DIS **/ UINT8 PcieEnablePeerMemoryWrite[28]; -/** Offset 0x09C9 - PCIE Compliance Test Mode +/** Offset 0x09CD - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board. $EN_DIS **/ UINT8 PcieComplianceTestMode; -/** Offset 0x09CA - PCIE Rp Function Swap +/** Offset 0x09CE - PCIE Rp Function Swap DEPRECATED. Allows BIOS to use root port function number swapping when root port of function 0 is disabled. $EN_DIS **/ UINT8 PcieRpFunctionSwap; -/** Offset 0x09CB - Enable/Disable PEG GEN3 Static EQ Phase1 programming +/** Offset 0x09CF - Enable/Disable PEG GEN3 Static EQ Phase1 programming Program Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming $EN_DIS **/ UINT8 CpuPcieGen3ProgramStaticEq; -/** Offset 0x09CC - Enable/Disable GEN4 Static EQ Phase1 programming +/** Offset 0x09D0 - Enable/Disable GEN4 Static EQ Phase1 programming Program Gen4 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming $EN_DIS **/ UINT8 CpuPcieGen4ProgramStaticEq; -/** Offset 0x09CD - PCH Pm PME_B0_S5_DIS +/** Offset 0x09D1 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. $EN_DIS **/ UINT8 PchPmPmeB0S5Dis; -/** Offset 0x09CE - PCIE IMR +/** Offset 0x09D2 - PCIE IMR Enables Isolated Memory Region for PCIe. $EN_DIS **/ UINT8 PcieRpImrEnabled; -/** Offset 0x09CF - PCIE IMR port number +/** Offset 0x09D3 - PCIE IMR port number Selects PCIE root port number for IMR feature. **/ UINT8 PcieRpImrSelection; -/** Offset 0x09D0 - PCH Pm Wol Enable Override +/** Offset 0x09D4 - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. $EN_DIS **/ UINT8 PchPmWolEnableOverride; -/** Offset 0x09D1 - PCH Pm Pcie Wake From DeepSx +/** Offset 0x09D5 - PCH Pm Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx. $EN_DIS **/ UINT8 PchPmPcieWakeFromDeepSx; -/** Offset 0x09D2 - PCH Pm WoW lan Enable +/** Offset 0x09D6 - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. $EN_DIS **/ UINT8 PchPmWoWlanEnable; -/** Offset 0x09D3 - PCH Pm WoW lan DeepSx Enable +/** Offset 0x09D7 - PCH Pm WoW lan DeepSx Enable Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. $EN_DIS **/ UINT8 PchPmWoWlanDeepSxEnable; -/** Offset 0x09D4 - PCH Pm Lan Wake From DeepSx +/** Offset 0x09D8 - PCH Pm Lan Wake From DeepSx Determine if enable LAN to wake from deep Sx. $EN_DIS **/ UINT8 PchPmLanWakeFromDeepSx; -/** Offset 0x09D5 - PCH Pm Deep Sx Pol +/** Offset 0x09D9 - PCH Pm Deep Sx Pol Deep Sx Policy. $EN_DIS **/ UINT8 PchPmDeepSxPol; -/** Offset 0x09D6 - PCH Pm Slp S3 Min Assert +/** Offset 0x09DA - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. **/ UINT8 PchPmSlpS3MinAssert; -/** Offset 0x09D7 - PCH Pm Slp S4 Min Assert +/** Offset 0x09DB - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. **/ UINT8 PchPmSlpS4MinAssert; -/** Offset 0x09D8 - PCH Pm Slp Sus Min Assert +/** Offset 0x09DC - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. **/ UINT8 PchPmSlpSusMinAssert; -/** Offset 0x09D9 - PCH Pm Slp A Min Assert +/** Offset 0x09DD - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. **/ UINT8 PchPmSlpAMinAssert; -/** Offset 0x09DA - USB Overcurrent Override for VISA +/** Offset 0x09DE - USB Overcurrent Override for VISA This option overrides USB Over Current enablement state that USB OC will be disabled after enabling this option. Enable when VISA pin is muxed with USB OC $EN_DIS **/ UINT8 PchEnableDbcObs; -/** Offset 0x09DB - PCH Pm Slp Strch Sus Up +/** Offset 0x09DF - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up. $EN_DIS **/ UINT8 PchPmSlpStrchSusUp; -/** Offset 0x09DC - PCH Pm Slp Lan Low Dc +/** Offset 0x09E0 - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power. $EN_DIS **/ UINT8 PchPmSlpLanLowDc; -/** Offset 0x09DD - PCH Pm Pwr Btn Override Period +/** Offset 0x09E1 - PCH Pm Pwr Btn Override Period PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. **/ UINT8 PchPmPwrBtnOverridePeriod; -/** Offset 0x09DE - PCH Pm Disable Dsx Ac Present Pulldown +/** Offset 0x09E2 - PCH Pm Disable Dsx Ac Present Pulldown When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. $EN_DIS **/ UINT8 PchPmDisableDsxAcPresentPulldown; -/** Offset 0x09DF - PCH Pm Disable Native Power Button +/** Offset 0x09E3 - PCH Pm Disable Native Power Button Power button native mode disable. $EN_DIS **/ UINT8 PchPmDisableNativePowerButton; -/** Offset 0x09E0 - PCH Pm ME_WAKE_STS +/** Offset 0x09E4 - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmMeWakeSts; -/** Offset 0x09E1 - PCH Pm WOL_OVR_WK_STS +/** Offset 0x09E5 - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmWolOvrWkSts; -/** Offset 0x09E2 - PCH Pm Reset Power Cycle Duration +/** Offset 0x09E6 - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ... **/ UINT8 PchPmPwrCycDur; -/** Offset 0x09E3 - PCH Pm Pcie Pll Ssc +/** Offset 0x09E7 - PCH Pm Pcie Pll Ssc Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No BIOS override. **/ UINT8 PchPmPciePllSsc; -/** Offset 0x09E4 - PCH Legacy IO Low Latency Enable +/** Offset 0x09E8 - PCH Legacy IO Low Latency Enable Set to enable low latency of legacy IO. 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchLegacyIoLowLatency; -/** Offset 0x09E5 - PCH Sata Pwr Opt Enable +/** Offset 0x09E9 - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. $EN_DIS **/ UINT8 SataPwrOptEnable; -/** Offset 0x09E6 - PCH Sata eSATA Speed Limit +/** Offset 0x09EA - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. $EN_DIS **/ UINT8 EsataSpeedLimit; -/** Offset 0x09E7 - PCH Sata Speed Limit +/** Offset 0x09EB - PCH Sata Speed Limit Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. **/ UINT8 SataSpeedLimit; -/** Offset 0x09E8 - Enable SATA Port HotPlug +/** Offset 0x09EC - Enable SATA Port HotPlug Enable SATA Port HotPlug. **/ UINT8 SataPortsHotPlug[8]; -/** Offset 0x09F0 - Enable SATA Port Interlock Sw +/** Offset 0x09F4 - Enable SATA Port Interlock Sw Enable SATA Port Interlock Sw. **/ UINT8 SataPortsInterlockSw[8]; -/** Offset 0x09F8 - Enable SATA Port External +/** Offset 0x09FC - Enable SATA Port External Enable SATA Port External. **/ UINT8 SataPortsExternal[8]; -/** Offset 0x0A00 - Enable SATA Port SpinUp +/** Offset 0x0A04 - Enable SATA Port SpinUp Enable the COMRESET initialization Sequence to the device. **/ UINT8 SataPortsSpinUp[8]; -/** Offset 0x0A08 - Enable SATA Port Solid State Drive +/** Offset 0x0A0C - Enable SATA Port Solid State Drive 0: HDD; 1: SSD. **/ UINT8 SataPortsSolidStateDrive[8]; -/** Offset 0x0A10 - Enable SATA Port Enable Dito Config +/** Offset 0x0A14 - Enable SATA Port Enable Dito Config Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). **/ UINT8 SataPortsEnableDitoConfig[8]; -/** Offset 0x0A18 - Enable SATA Port DmVal +/** Offset 0x0A1C - Enable SATA Port DmVal DITO multiplier. Default is 15. **/ UINT8 SataPortsDmVal[8]; -/** Offset 0x0A20 - Enable SATA Port DmVal +/** Offset 0x0A24 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. **/ UINT16 SataPortsDitoVal[8]; -/** Offset 0x0A30 - Enable SATA Port ZpOdd +/** Offset 0x0A34 - Enable SATA Port ZpOdd Support zero power ODD. **/ UINT8 SataPortsZpOdd[8]; -/** Offset 0x0A38 - PCH Sata Rst Raid Alternate Id +/** Offset 0x0A3C - PCH Sata Rst Raid Alternate Id Enable RAID Alternate ID. $EN_DIS **/ UINT8 SataRstRaidDeviceId; -/** Offset 0x0A39 - PCH Sata Rst Pcie Storage Remap enable +/** Offset 0x0A3D - PCH Sata Rst Pcie Storage Remap enable Enable Intel RST for PCIe Storage remapping. **/ UINT8 SataRstPcieEnable[3]; -/** Offset 0x0A3C - PCH Sata Rst Pcie Storage Port +/** Offset 0x0A40 - PCH Sata Rst Pcie Storage Port Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). **/ UINT8 SataRstPcieStoragePort[3]; -/** Offset 0x0A3F - PCH Sata Rst Pcie Device Reset Delay +/** Offset 0x0A43 - PCH Sata Rst Pcie Device Reset Delay PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms **/ UINT8 SataRstPcieDeviceResetDelay[3]; -/** Offset 0x0A42 - UFS enable/disable +/** Offset 0x0A46 - UFS enable/disable PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms $EN_DIS **/ UINT8 UfsEnable[2]; -/** Offset 0x0A44 - IEH Mode +/** Offset 0x0A48 - IEH Mode Integrated Error Handler Mode, 0: Bypass, 1: Enable 0: Bypass, 1:Enable **/ UINT8 IehMode; -/** Offset 0x0A45 - Reserved +/** Offset 0x0A49 - Reserved **/ - UINT8 Reserved61; + UINT8 Reserved63; -/** Offset 0x0A46 - Thermal Throttling Custimized T0Level Value +/** Offset 0x0A4A - Thermal Throttling Custimized T0Level Value Custimized T0Level value. **/ UINT16 PchT0Level; -/** Offset 0x0A48 - Thermal Throttling Custimized T1Level Value +/** Offset 0x0A4C - Thermal Throttling Custimized T1Level Value Custimized T1Level value. **/ UINT16 PchT1Level; -/** Offset 0x0A4A - Thermal Throttling Custimized T2Level Value +/** Offset 0x0A4E - Thermal Throttling Custimized T2Level Value Custimized T2Level value. **/ UINT16 PchT2Level; -/** Offset 0x0A4C - Enable The Thermal Throttle +/** Offset 0x0A50 - Enable The Thermal Throttle Enable the thermal throttle function. $EN_DIS **/ UINT8 PchTTEnable; -/** Offset 0x0A4D - PMSync State 13 +/** Offset 0x0A51 - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. $EN_DIS **/ UINT8 PchTTState13Enable; -/** Offset 0x0A4E - Thermal Throttle Lock +/** Offset 0x0A52 - Thermal Throttle Lock Thermal Throttle Lock. $EN_DIS **/ UINT8 PchTTLock; -/** Offset 0x0A4F - Thermal Throttling Suggested Setting +/** Offset 0x0A53 - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting. $EN_DIS **/ UINT8 TTSuggestedSetting; -/** Offset 0x0A50 - Enable PCH Cross Throttling +/** Offset 0x0A54 - Enable PCH Cross Throttling Enable/Disable PCH Cross Throttling $EN_DIS **/ UINT8 TTCrossThrottling; -/** Offset 0x0A51 - DMI Thermal Sensor Autonomous Width Enable +/** Offset 0x0A55 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable. $EN_DIS **/ UINT8 PchDmiTsawEn; -/** Offset 0x0A52 - DMI Thermal Sensor Suggested Setting +/** Offset 0x0A56 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative values. $EN_DIS **/ UINT8 DmiSuggestedSetting; -/** Offset 0x0A53 - Thermal Sensor 0 Target Width +/** Offset 0x0A57 - Thermal Sensor 0 Target Width Thermal Sensor 0 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS0TW; -/** Offset 0x0A54 - Thermal Sensor 1 Target Width +/** Offset 0x0A58 - Thermal Sensor 1 Target Width Thermal Sensor 1 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS1TW; -/** Offset 0x0A55 - Thermal Sensor 2 Target Width +/** Offset 0x0A59 - Thermal Sensor 2 Target Width Thermal Sensor 2 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS2TW; -/** Offset 0x0A56 - Thermal Sensor 3 Target Width +/** Offset 0x0A5A - Thermal Sensor 3 Target Width Thermal Sensor 3 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS3TW; -/** Offset 0x0A57 - Port 0 T1 Multipler +/** Offset 0x0A5B - Port 0 T1 Multipler Port 0 T1 Multipler. **/ UINT8 SataP0T1M; -/** Offset 0x0A58 - Port 0 T2 Multipler +/** Offset 0x0A5C - Port 0 T2 Multipler Port 0 T2 Multipler. **/ UINT8 SataP0T2M; -/** Offset 0x0A59 - Port 0 T3 Multipler +/** Offset 0x0A5D - Port 0 T3 Multipler Port 0 T3 Multipler. **/ UINT8 SataP0T3M; -/** Offset 0x0A5A - Port 0 Tdispatch +/** Offset 0x0A5E - Port 0 Tdispatch Port 0 Tdispatch. **/ UINT8 SataP0TDisp; -/** Offset 0x0A5B - Port 1 T1 Multipler +/** Offset 0x0A5F - Port 1 T1 Multipler Port 1 T1 Multipler. **/ UINT8 SataP1T1M; -/** Offset 0x0A5C - Port 1 T2 Multipler +/** Offset 0x0A60 - Port 1 T2 Multipler Port 1 T2 Multipler. **/ UINT8 SataP1T2M; -/** Offset 0x0A5D - Port 1 T3 Multipler +/** Offset 0x0A61 - Port 1 T3 Multipler Port 1 T3 Multipler. **/ UINT8 SataP1T3M; -/** Offset 0x0A5E - Port 1 Tdispatch +/** Offset 0x0A62 - Port 1 Tdispatch Port 1 Tdispatch. **/ UINT8 SataP1TDisp; -/** Offset 0x0A5F - Port 0 Tinactive +/** Offset 0x0A63 - Port 0 Tinactive Port 0 Tinactive. **/ UINT8 SataP0Tinact; -/** Offset 0x0A60 - Port 0 Alternate Fast Init Tdispatch +/** Offset 0x0A64 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch. $EN_DIS **/ UINT8 SataP0TDispFinit; -/** Offset 0x0A61 - Port 1 Tinactive +/** Offset 0x0A65 - Port 1 Tinactive Port 1 Tinactive. **/ UINT8 SataP1Tinact; -/** Offset 0x0A62 - Port 1 Alternate Fast Init Tdispatch +/** Offset 0x0A66 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch. $EN_DIS **/ UINT8 SataP1TDispFinit; -/** Offset 0x0A63 - Sata Thermal Throttling Suggested Setting +/** Offset 0x0A67 - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting. $EN_DIS **/ UINT8 SataThermalSuggestedSetting; -/** Offset 0x0A64 - Enable Memory Thermal Throttling +/** Offset 0x0A68 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. $EN_DIS **/ UINT8 PchMemoryThrottlingEnable; -/** Offset 0x0A65 - Memory Thermal Throttling +/** Offset 0x0A69 - Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryPmsyncEnable[2]; -/** Offset 0x0A67 - Enable Memory Thermal Throttling +/** Offset 0x0A6B - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryC0TransmitEnable[2]; -/** Offset 0x0A69 - Enable Memory Thermal Throttling +/** Offset 0x0A6D - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryPinSelection[2]; -/** Offset 0x0A6B - Reserved +/** Offset 0x0A6F - Reserved **/ - UINT8 Reserved62; + UINT8 Reserved64; -/** Offset 0x0A6C - Thermal Device Temperature +/** Offset 0x0A70 - Thermal Device Temperature Decides the temperature. **/ UINT16 PchTemperatureHotLevel; -/** Offset 0x0A6E - USB2 Port Over Current Pin +/** Offset 0x0A72 - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x0A7E - USB3 Port Over Current Pin +/** Offset 0x0A82 - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x0A88 - Enable xHCI LTR override +/** Offset 0x0A8C - Enable xHCI LTR override Enables override of recommended LTR values for xHCI $EN_DIS **/ UINT8 PchUsbLtrOverrideEnable; -/** Offset 0x0A89 - Reserved +/** Offset 0x0A8D - Reserved **/ - UINT8 Reserved63[2]; + UINT8 Reserved65[2]; -/** Offset 0x0A8B - Reserved +/** Offset 0x0A8F - Reserved **/ - UINT8 Reserved64; + UINT8 Reserved66; -/** Offset 0x0A8C - xHCI High Idle Time LTR override +/** Offset 0x0A90 - xHCI High Idle Time LTR override Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting **/ UINT32 PchUsbLtrHighIdleTimeOverride; -/** Offset 0x0A90 - xHCI Medium Idle Time LTR override +/** Offset 0x0A94 - xHCI Medium Idle Time LTR override Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting **/ UINT32 PchUsbLtrMediumIdleTimeOverride; -/** Offset 0x0A94 - xHCI Low Idle Time LTR override +/** Offset 0x0A98 - xHCI Low Idle Time LTR override Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting **/ UINT32 PchUsbLtrLowIdleTimeOverride; -/** Offset 0x0A98 - Enable 8254 Static Clock Gating +/** Offset 0x0A9C - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer. Also enable this while S0ix is enabled. @@ -2563,7 +2571,7 @@ **/ UINT8 Enable8254ClockGating; -/** Offset 0x0A99 - Enable 8254 Static Clock Gating On S3 +/** Offset 0x0A9D - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming. @@ -2571,7 +2579,7 @@ **/ UINT8 Enable8254ClockGatingOnS3; -/** Offset 0x0A9A - Enable TCO timer. +/** Offset 0x0A9E - Enable TCO timer. When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS. @@ -2579,113 +2587,113 @@ **/ UINT8 EnableTcoTimer; -/** Offset 0x0A9B - Hybrid Storage Detection and Configuration Mode +/** Offset 0x0A9F - Hybrid Storage Detection and Configuration Mode Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. Default is 0: Disabled 0: Disabled, 1: Dynamic Configuration **/ UINT8 HybridStorageMode; -/** Offset 0x0A9C - Reserved -**/ - UINT8 Reserved65; - -/** Offset 0x0A9D - Reserved -**/ - UINT8 Reserved66; - -/** Offset 0x0A9E - Reserved +/** Offset 0x0AA0 - Reserved **/ UINT8 Reserved67; -/** Offset 0x0A9F - Reserved +/** Offset 0x0AA1 - Reserved **/ - UINT8 Reserved68[1]; + UINT8 Reserved68; -/** Offset 0x0AA0 - BgpdtHash[4] +/** Offset 0x0AA2 - Reserved +**/ + UINT8 Reserved69; + +/** Offset 0x0AA3 - Reserved +**/ + UINT8 Reserved70[5]; + +/** Offset 0x0AA8 - BgpdtHash[4] BgpdtHash values **/ UINT64 BgpdtHash[4]; -/** Offset 0x0AC0 - BiosGuardAttr +/** Offset 0x0AC8 - BiosGuardAttr BiosGuardAttr default values **/ UINT32 BiosGuardAttr; -/** Offset 0x0AC4 - Reserved +/** Offset 0x0ACC - Reserved **/ - UINT8 Reserved69[4]; + UINT8 Reserved71[4]; -/** Offset 0x0AC8 - BiosGuardModulePtr +/** Offset 0x0AD0 - BiosGuardModulePtr BiosGuardModulePtr default values **/ UINT64 BiosGuardModulePtr; -/** Offset 0x0AD0 - SendEcCmd +/** Offset 0x0AD8 - SendEcCmd SendEcCmd function pointer. \n @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode **/ UINT64 SendEcCmd; -/** Offset 0x0AD8 - EcCmdProvisionEav +/** Offset 0x0AE0 - EcCmdProvisionEav Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC **/ UINT8 EcCmdProvisionEav; -/** Offset 0x0AD9 - EcCmdLock +/** Offset 0x0AE1 - EcCmdLock EcCmdLock default values. Locks Ephemeral Authorization Value sent previously **/ UINT8 EcCmdLock; -/** Offset 0x0ADA - Skip Ssid Programming. +/** Offset 0x0AE2 - Skip Ssid Programming. When set to TRUE, silicon code will not do any SSID programming and platform code needs to handle that by itself properly. $EN_DIS **/ UINT8 SiSkipSsidProgramming; -/** Offset 0x0ADB - Reserved +/** Offset 0x0AE3 - Reserved **/ - UINT8 Reserved70; + UINT8 Reserved72; -/** Offset 0x0ADC - Change Default SVID +/** Offset 0x0AE4 - Change Default SVID Change the default SVID used in FSP to programming internal devices. This is only valid when SkipSsidProgramming is FALSE. **/ UINT16 SiCustomizedSvid; -/** Offset 0x0ADE - Change Default SSID +/** Offset 0x0AE6 - Change Default SSID Change the default SSID used in FSP to programming internal devices. This is only valid when SkipSsidProgramming is FALSE. **/ UINT16 SiCustomizedSsid; -/** Offset 0x0AE0 - SVID SDID table Poniter. +/** Offset 0x0AE8 - SVID SDID table Poniter. The address of the table of SVID SDID to customize each SVID SDID entry. This is only valid when SkipSsidProgramming is FALSE. **/ UINT32 SiSsidTablePtr; -/** Offset 0x0AE4 - Number of ssid table. +/** Offset 0x0AEC - Number of ssid table. SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. This is only valid when SkipSsidProgramming is FALSE. **/ UINT16 SiNumberOfSsidTableEntry; -/** Offset 0x0AE6 - USB2 Port Reset Message Enable +/** Offset 0x0AEE - USB2 Port Reset Message Enable 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must be enable for USB2 Port those are paired with CPU XHCI Port **/ UINT8 PortResetMessageEnable[16]; -/** Offset 0x0AF6 - SATA RST Interrupt Mode +/** Offset 0x0AFE - SATA RST Interrupt Mode Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. 0:Msix, 1:Msi, 2:Legacy **/ UINT8 SataRstInterrupt; -/** Offset 0x0AF7 - ME Unconfig on RTC clear +/** Offset 0x0AFF - ME Unconfig on RTC clear 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. 2: Cmos is clear, status unkonwn. 3: Reserved 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos @@ -2693,13 +2701,13 @@ **/ UINT8 MeUnconfigOnRtcClear; -/** Offset 0x0AF8 - Enforce Enhanced Debug Mode +/** Offset 0x0B00 - Enforce Enhanced Debug Mode Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable $EN_DIS **/ UINT8 EnforceEDebugMode; -/** Offset 0x0AF9 - Enable PS_ON. +/** Offset 0x0B01 - Enable PS_ON. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled. @@ -2707,170 +2715,170 @@ **/ UINT8 PsOnEnable; -/** Offset 0x0AFA - Pmc Cpu C10 Gate Pin Enable +/** Offset 0x0B02 - Pmc Cpu C10 Gate Pin Enable Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin. $EN_DIS **/ UINT8 PmcCpuC10GatePinEnable; -/** Offset 0x0AFB - Pch Dmi Aspm Ctrl +/** Offset 0x0B03 - Pch Dmi Aspm Ctrl ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmL1 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto **/ UINT8 PchDmiAspmCtrl; -/** Offset 0x0AFC - PchDmiCwbEnable +/** Offset 0x0B04 - PchDmiCwbEnable Central Write Buffer feature configurable and enabled by default $EN_DIS **/ UINT8 PchDmiCwbEnable; -/** Offset 0x0AFD - OS IDLE Mode Enable +/** Offset 0x0B05 - OS IDLE Mode Enable Enable/Disable OS Idle Mode $EN_DIS **/ UINT8 PmcOsIdleEnable; -/** Offset 0x0AFE - S0ix Auto-Demotion +/** Offset 0x0B06 - S0ix Auto-Demotion Enable/Disable the Low Power Mode Auto-Demotion Host Control feature. $EN_DIS **/ UINT8 PchS0ixAutoDemotion; -/** Offset 0x0AFF - Latch Events C10 Exit +/** Offset 0x0B07 - Latch Events C10 Exit When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are captured on C10 exit (instead of C10 entry which is default) $EN_DIS **/ UINT8 PchPmLatchEventsC10Exit; -/** Offset 0x0B00 - Reserved -**/ - UINT8 Reserved71; - -/** Offset 0x0B01 - Reserved -**/ - UINT8 Reserved72; - -/** Offset 0x0B02 - Reserved +/** Offset 0x0B08 - Reserved **/ UINT8 Reserved73; -/** Offset 0x0B03 - Reserved +/** Offset 0x0B09 - Reserved **/ UINT8 Reserved74; -/** Offset 0x0B04 - Reserved +/** Offset 0x0B0A - Reserved **/ UINT8 Reserved75; -/** Offset 0x0B05 - Reserved +/** Offset 0x0B0B - Reserved **/ UINT8 Reserved76; -/** Offset 0x0B06 - Reserved +/** Offset 0x0B0C - Reserved **/ - UINT8 Reserved77[2]; + UINT8 Reserved77; -/** Offset 0x0B08 - Reserved +/** Offset 0x0B0D - Reserved **/ - UINT32 Reserved78; + UINT8 Reserved78; -/** Offset 0x0B0C - PCIE Eq Ph3 Lane Param Cm +/** Offset 0x0B0E - Reserved +**/ + UINT8 Reserved79[2]; + +/** Offset 0x0B10 - Reserved +**/ + UINT32 Reserved80; + +/** Offset 0x0B14 - PCIE Eq Ph3 Lane Param Cm CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1. **/ UINT8 CpuPcieEqPh3LaneParamCm[32]; -/** Offset 0x0B2C - PCIE Eq Ph3 Lane Param Cp +/** Offset 0x0B34 - PCIE Eq Ph3 Lane Param Cp CPU_PCIE_EQ_LANE_PARAM. Coefficient C+1. **/ UINT8 CpuPcieEqPh3LaneParamCp[32]; -/** Offset 0x0B4C - Gen3 Root port preset values per lane +/** Offset 0x0B54 - Gen3 Root port preset values per lane Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 8 is default for each lane **/ UINT8 CpuPcieGen3RootPortPreset[20]; -/** Offset 0x0B60 - Pcie Gen4 Root port preset values per lane +/** Offset 0x0B68 - Pcie Gen4 Root port preset values per lane Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 8 is default for each lane **/ UINT8 CpuPcieGen4RootPortPreset[20]; -/** Offset 0x0B74 - Pcie Gen3 End port preset values per lane +/** Offset 0x0B7C - Pcie Gen3 End port preset values per lane Used for programming Pcie Gen3 preset values per lane. Range: 0-9, 7 is default for each lane **/ UINT8 CpuPcieGen3EndPointPreset[20]; -/** Offset 0x0B88 - Pcie Gen4 End port preset values per lane +/** Offset 0x0B90 - Pcie Gen4 End port preset values per lane Used for programming Pcie Gen4 preset values per lane. Range: 0-9, 7 is default for each lane **/ UINT8 CpuPcieGen4EndPointPreset[20]; -/** Offset 0x0B9C - Pcie Gen3 End port Hint values per lane +/** Offset 0x0BA4 - Pcie Gen3 End port Hint values per lane Used for programming Pcie Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane **/ UINT8 CpuPcieGen3EndPointHint[20]; -/** Offset 0x0BB0 - Pcie Gen4 End port Hint values per lane +/** Offset 0x0BB8 - Pcie Gen4 End port Hint values per lane Used for programming Pcie Gen4 Hint values per lane. Range: 0-6, 2 is default for each lane **/ UINT8 CpuPcieGen4EndPointHint[20]; -/** Offset 0x0BC4 - CPU PCIe Fia Programming +/** Offset 0x0BCC - CPU PCIe Fia Programming Load Fia configuration if enable. 0: Disable; 1: Enable(Default). $EN_DIS **/ UINT8 CpuPcieFiaProgramming; -/** Offset 0x0BC5 - CPU PCIe RootPort Clock Gating +/** Offset 0x0BCD - CPU PCIe RootPort Clock Gating Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable(Default). $EN_DIS **/ UINT8 CpuPcieClockGating[4]; -/** Offset 0x0BC9 - CPU PCIe RootPort Power Gating +/** Offset 0x0BD1 - CPU PCIe RootPort Power Gating Describes whether the PCI Express Power Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable(Default). $EN_DIS **/ UINT8 CpuPciePowerGating[4]; -/** Offset 0x0BCD - PCIE Compliance Test Mode +/** Offset 0x0BD5 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board. $EN_DIS **/ UINT8 CpuPcieComplianceTestMode; -/** Offset 0x0BCE - PCIE Enable Peer Memory Write +/** Offset 0x0BD6 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. $EN_DIS **/ UINT8 CpuPcieEnablePeerMemoryWrite; -/** Offset 0x0BCF - PCIE Rp Function Swap +/** Offset 0x0BD7 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root port of function 0 is disabled. $EN_DIS **/ UINT8 CpuPcieRpFunctionSwap; -/** Offset 0x0BD0 - PCI Express Slot Selection +/** Offset 0x0BD8 - PCI Express Slot Selection Select the PCIe M2 or CEMx4 slot.0: CEMx4 slot; 1: M2 slot(Default). $EN_DIS **/ UINT8 CpuPcieSlotSelection; -/** Offset 0x0BD1 - Reserved +/** Offset 0x0BD9 - Reserved **/ - UINT8 Reserved79[3]; + UINT8 Reserved81[3]; -/** Offset 0x0BD4 - CPU PCIE device override table pointer +/** Offset 0x0BDC - CPU PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. This is a pointer points to a 32bit address. And it's only used in PostMem phase. Please refer to CPU_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId @@ -2878,233 +2886,233 @@ **/ UINT32 CpuPcieDeviceOverrideTablePtr; -/** Offset 0x0BD8 - Enable PCIE RP HotPlug +/** Offset 0x0BE0 - Enable PCIE RP HotPlug Indicate whether the root port is hot plug available. **/ UINT8 CpuPcieRpHotPlug[4]; -/** Offset 0x0BDC - Enable PCIE RP Pm Sci +/** Offset 0x0BE4 - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled. **/ UINT8 CpuPcieRpPmSci[4]; -/** Offset 0x0BE0 - Enable PCIE RP Transmitter Half Swing +/** Offset 0x0BE8 - Enable PCIE RP Transmitter Half Swing Indicate whether the Transmitter Half Swing is enabled. **/ UINT8 CpuPcieRpTransmitterHalfSwing[4]; -/** Offset 0x0BE4 - PCIE RP Access Control Services Extended Capability +/** Offset 0x0BEC - PCIE RP Access Control Services Extended Capability Enable/Disable PCIE RP Access Control Services Extended Capability **/ UINT8 CpuPcieRpAcsEnabled[4]; -/** Offset 0x0BE8 - PCIE RP Clock Power Management +/** Offset 0x0BF0 - PCIE RP Clock Power Management Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism **/ UINT8 CpuPcieRpEnableCpm[4]; -/** Offset 0x0BEC - PCIE RP Advanced Error Report +/** Offset 0x0BF4 - PCIE RP Advanced Error Report Indicate whether the Advanced Error Reporting is enabled. **/ UINT8 CpuPcieRpAdvancedErrorReporting[4]; -/** Offset 0x0BF0 - PCIE RP Unsupported Request Report +/** Offset 0x0BF8 - PCIE RP Unsupported Request Report Indicate whether the Unsupported Request Report is enabled. **/ UINT8 CpuPcieRpUnsupportedRequestReport[4]; -/** Offset 0x0BF4 - PCIE RP Fatal Error Report +/** Offset 0x0BFC - PCIE RP Fatal Error Report Indicate whether the Fatal Error Report is enabled. **/ UINT8 CpuPcieRpFatalErrorReport[4]; -/** Offset 0x0BF8 - PCIE RP No Fatal Error Report +/** Offset 0x0C00 - PCIE RP No Fatal Error Report Indicate whether the No Fatal Error Report is enabled. **/ UINT8 CpuPcieRpNoFatalErrorReport[4]; -/** Offset 0x0BFC - PCIE RP Correctable Error Report +/** Offset 0x0C04 - PCIE RP Correctable Error Report Indicate whether the Correctable Error Report is enabled. **/ UINT8 CpuPcieRpCorrectableErrorReport[4]; -/** Offset 0x0C00 - PCIE RP System Error On Fatal Error +/** Offset 0x0C08 - PCIE RP System Error On Fatal Error Indicate whether the System Error on Fatal Error is enabled. **/ UINT8 CpuPcieRpSystemErrorOnFatalError[4]; -/** Offset 0x0C04 - PCIE RP System Error On Non Fatal Error +/** Offset 0x0C0C - PCIE RP System Error On Non Fatal Error Indicate whether the System Error on Non Fatal Error is enabled. **/ UINT8 CpuPcieRpSystemErrorOnNonFatalError[4]; -/** Offset 0x0C08 - PCIE RP System Error On Correctable Error +/** Offset 0x0C10 - PCIE RP System Error On Correctable Error Indicate whether the System Error on Correctable Error is enabled. **/ UINT8 CpuPcieRpSystemErrorOnCorrectableError[4]; -/** Offset 0x0C0C - PCIE RP Max Payload +/** Offset 0x0C14 - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum CPU_PCIE_MAX_PAYLOAD. **/ UINT8 CpuPcieRpMaxPayload[4]; -/** Offset 0x0C10 - DPC for PCIE RP Mask +/** Offset 0x0C18 - DPC for PCIE RP Mask Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT8 CpuPcieRpDpcEnabled[4]; -/** Offset 0x0C14 - DPC Extensions PCIE RP Mask +/** Offset 0x0C1C - DPC Extensions PCIE RP Mask Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT8 CpuPcieRpDpcExtensionsEnabled[4]; -/** Offset 0x0C18 - CPU PCIe root port connection type +/** Offset 0x0C20 - CPU PCIe root port connection type 0: built-in device, 1:slot **/ UINT8 CpuPcieRpSlotImplemented[4]; -/** Offset 0x0C1C - PCIE RP Gen3 Equalization Phase Method +/** Offset 0x0C24 - PCIE RP Gen3 Equalization Phase Method PCIe Gen3 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; 1: hardware equalization; 4: Fixed Coeficients. **/ UINT8 CpuPcieRpGen3EqPh3Method[4]; -/** Offset 0x0C20 - PCIE RP Gen4 Equalization Phase Method +/** Offset 0x0C28 - PCIE RP Gen4 Equalization Phase Method PCIe Gen4 Eq Ph3 Method (see CPU_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; 1: hardware equalization; 4: Fixed Coeficients. **/ UINT8 CpuPcieRpGen4EqPh3Method[4]; -/** Offset 0x0C24 - PCIE RP Physical Slot Number +/** Offset 0x0C2C - PCIE RP Physical Slot Number Indicates the slot number for the root port. Default is the value as root port index. **/ UINT8 CpuPcieRpPhysicalSlotNumber[4]; -/** Offset 0x0C28 - PCIE RP Aspm +/** Offset 0x0C30 - PCIE RP Aspm The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL).0: Disable; 1: CpuPcieAspmL0s; 2: CpuPcieAspmL1; 3:CpuPcieAspmL0sL1(Default) **/ UINT8 CpuPcieRpAspm[4]; -/** Offset 0x0C2C - PCIE RP L1 Substates +/** Offset 0x0C34 - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). Default is CpuPcieL1SubstatesL1_1_2. **/ UINT8 CpuPcieRpL1Substates[4]; -/** Offset 0x0C30 - PCIE RP Ltr Enable +/** Offset 0x0C38 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. **/ UINT8 CpuPcieRpLtrEnable[4]; -/** Offset 0x0C34 - PCIE RP Ltr Config Lock +/** Offset 0x0C3C - PCIE RP Ltr Config Lock 0: Disable; 1: Enable. **/ UINT8 CpuPcieRpLtrConfigLock[4]; -/** Offset 0x0C38 - PTM for PCIE RP Mask +/** Offset 0x0C40 - PTM for PCIE RP Mask Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT8 CpuPcieRpPtmEnabled[4]; -/** Offset 0x0C3C - PCIE RP Detect Timeout Ms +/** Offset 0x0C44 - PCIE RP Detect Timeout Ms The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port. **/ UINT16 CpuPcieRpDetectTimeoutMs[4]; -/** Offset 0x0C44 - Multi-VC for PCIE RP Mask +/** Offset 0x0C4C - Multi-VC for PCIE RP Mask Enable/disable Multiple Virtual Channel for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT8 CpuPcieRpMultiVcEnabled[4]; -/** Offset 0x0C48 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 +/** Offset 0x0C50 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate3UniqTranEnable[10]; -/** Offset 0x0C52 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 +/** Offset 0x0C5A - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate3UniqTran[10]; -/** Offset 0x0C5C - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 +/** Offset 0x0C64 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate2UniqTranEnable[10]; -/** Offset 0x0C66 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 +/** Offset 0x0C6E - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate2UniqTran[10]; -/** Offset 0x0C70 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 +/** Offset 0x0C78 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate1UniqTranEnable[10]; -/** Offset 0x0C7A - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 +/** Offset 0x0C82 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate1UniqTran[10]; -/** Offset 0x0C84 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 +/** Offset 0x0C8C - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate0UniqTranEnable[10]; -/** Offset 0x0C8E - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 +/** Offset 0x0C96 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate0UniqTran[10]; -/** Offset 0x0C98 - Skip PAM regsiter lock +/** Offset 0x0CA0 - Skip PAM regsiter lock Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC $EN_DIS **/ UINT8 SkipPamLock; -/** Offset 0x0C99 - EDRAM Test Mode +/** Offset 0x0CA1 - EDRAM Test Mode Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode **/ UINT8 EdramTestMode; -/** Offset 0x0C9A - Enable/Disable IGFX RenderStandby +/** Offset 0x0CA2 - Enable/Disable IGFX RenderStandby Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby $EN_DIS **/ UINT8 RenderStandby; -/** Offset 0x0C9B - Enable/Disable IGFX PmSupport +/** Offset 0x0CA3 - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS **/ UINT8 PmSupport; -/** Offset 0x0C9C - Enable/Disable CdynmaxClamp +/** Offset 0x0CA4 - Enable/Disable CdynmaxClamp Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp $EN_DIS **/ UINT8 CdynmaxClampEnable; -/** Offset 0x0C9D - GT Frequency Limit +/** Offset 0x0CA5 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, @@ -3118,121 +3126,121 @@ **/ UINT8 GtFreqMax; -/** Offset 0x0C9E - Disable Turbo GT +/** Offset 0x0CA6 - Disable Turbo GT 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency $EN_DIS **/ UINT8 DisableTurboGt; -/** Offset 0x0C9F - Enable/Disable CdClock Init +/** Offset 0x0CA7 - Enable/Disable CdClock Init Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full CD clock if not initialized by Gfx PEIM $EN_DIS **/ UINT8 SkipCdClockInit; -/** Offset 0x0CA0 - Enable RC1p frequency request to PMA (provided all other conditions are met) +/** Offset 0x0CA8 - Enable RC1p frequency request to PMA (provided all other conditions are met) 0(Default)=Disable, 1=Enable $EN_DIS **/ UINT8 RC1pFreqEnable; -/** Offset 0x0CA1 - Enable TSN Multi-VC +/** Offset 0x0CA9 - Enable TSN Multi-VC Enable/disable Multi Virtual Channels(VC) in TSN. $EN_DIS **/ UINT8 PchTsnMultiVcEnable; -/** Offset 0x0CA2 - Reserved +/** Offset 0x0CAA - Reserved **/ - UINT8 Reserved80[2]; + UINT8 Reserved82[2]; -/** Offset 0x0CA4 - LogoPixelHeight Address +/** Offset 0x0CAC - LogoPixelHeight Address Address of LogoPixelHeight **/ UINT32 LogoPixelHeight; -/** Offset 0x0CA8 - LogoPixelWidth Address +/** Offset 0x0CB0 - LogoPixelWidth Address Address of LogoPixelWidth **/ UINT32 LogoPixelWidth; -/** Offset 0x0CAC - Reserved +/** Offset 0x0CB4 - Reserved **/ - UINT8 Reserved81; + UINT8 Reserved83; -/** Offset 0x0CAD - Reserved +/** Offset 0x0CB5 - Reserved **/ - UINT8 Reserved82; + UINT8 Reserved84; -/** Offset 0x0CAE - Reserved +/** Offset 0x0CB6 - Reserved **/ - UINT8 Reserved83[3]; + UINT8 Reserved85[3]; -/** Offset 0x0CB1 - RSR feature +/** Offset 0x0CB9 - RSR feature Enable or Disable RSR feature; 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableRsr; -/** Offset 0x0CB2 - Reserved +/** Offset 0x0CBA - Reserved **/ - UINT8 Reserved84[4]; + UINT8 Reserved86[4]; -/** Offset 0x0CB6 - Enable or Disable HWP +/** Offset 0x0CBE - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved $EN_DIS **/ UINT8 Hwp; -/** Offset 0x0CB7 - Hardware Duty Cycle Control +/** Offset 0x0CBF - Hardware Duty Cycle Control Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved $EN_DIS **/ UINT8 HdcControl; -/** Offset 0x0CB8 - Package Long duration turbo mode time +/** Offset 0x0CC0 - Package Long duration turbo mode time Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 **/ UINT8 PowerLimit1Time; -/** Offset 0x0CB9 - Short Duration Turbo Mode +/** Offset 0x0CC1 - Short Duration Turbo Mode Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable $EN_DIS **/ UINT8 PowerLimit2; -/** Offset 0x0CBA - Turbo settings Lock +/** Offset 0x0CC2 - Turbo settings Lock Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable $EN_DIS **/ UINT8 TurboPowerLimitLock; -/** Offset 0x0CBB - Package PL3 time window +/** Offset 0x0CC3 - Package PL3 time window Package PL3 time window range for this policy from 0 to 64ms **/ UINT8 PowerLimit3Time; -/** Offset 0x0CBC - Package PL3 Duty Cycle +/** Offset 0x0CC4 - Package PL3 Duty Cycle Package PL3 Duty Cycle; Valid Range is 0 to 100 **/ UINT8 PowerLimit3DutyCycle; -/** Offset 0x0CBD - Package PL3 Lock +/** Offset 0x0CC5 - Package PL3 Lock Package PL3 Lock Enable/Disable; 0: Disable ; 1:Enable $EN_DIS **/ UINT8 PowerLimit3Lock; -/** Offset 0x0CBE - Package PL4 Lock +/** Offset 0x0CC6 - Package PL4 Lock Package PL4 Lock Enable/Disable; 0: Disable ; 1:Enable $EN_DIS **/ UINT8 PowerLimit4Lock; -/** Offset 0x0CBF - TCC Activation Offset +/** Offset 0x0CC7 - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For SKL Y SKU, the recommended default for this policy is @@ -3240,7 +3248,7 @@ **/ UINT8 TccActivationOffset; -/** Offset 0x0CC0 - Tcc Offset Clamp Enable/Disable +/** Offset 0x0CC8 - Tcc Offset Clamp Enable/Disable Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For SKL Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled. @@ -3248,318 +3256,318 @@ **/ UINT8 TccOffsetClamp; -/** Offset 0x0CC1 - Tcc Offset Lock +/** Offset 0x0CC9 - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled. $EN_DIS **/ UINT8 TccOffsetLock; -/** Offset 0x0CC2 - Custom Ratio State Entries +/** Offset 0x0CCA - Custom Ratio State Entries The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states. At least 2 states must be present **/ UINT8 NumberOfEntries; -/** Offset 0x0CC3 - Custom Short term Power Limit time window +/** Offset 0x0CCB - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128 **/ UINT8 Custom1PowerLimit1Time; -/** Offset 0x0CC4 - Custom Turbo Activation Ratio +/** Offset 0x0CCC - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 **/ UINT8 Custom1TurboActivationRatio; -/** Offset 0x0CC5 - Custom Config Tdp Control +/** Offset 0x0CCD - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom1ConfigTdpControl; -/** Offset 0x0CC6 - Custom Short term Power Limit time window +/** Offset 0x0CCE - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128 **/ UINT8 Custom2PowerLimit1Time; -/** Offset 0x0CC7 - Custom Turbo Activation Ratio +/** Offset 0x0CCF - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 **/ UINT8 Custom2TurboActivationRatio; -/** Offset 0x0CC8 - Custom Config Tdp Control +/** Offset 0x0CD0 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom2ConfigTdpControl; -/** Offset 0x0CC9 - Custom Short term Power Limit time window +/** Offset 0x0CD1 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128 **/ UINT8 Custom3PowerLimit1Time; -/** Offset 0x0CCA - Custom Turbo Activation Ratio +/** Offset 0x0CD2 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 **/ UINT8 Custom3TurboActivationRatio; -/** Offset 0x0CCB - Custom Config Tdp Control +/** Offset 0x0CD3 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom3ConfigTdpControl; -/** Offset 0x0CCC - ConfigTdp mode settings Lock +/** Offset 0x0CD4 - ConfigTdp mode settings Lock Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ConfigTdpLock; -/** Offset 0x0CCD - Load Configurable TDP SSDT +/** Offset 0x0CD5 - Load Configurable TDP SSDT Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ConfigTdpBios; -/** Offset 0x0CCE - PL1 Enable value +/** Offset 0x0CD6 - PL1 Enable value PL1 Enable value to limit average platform power. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PsysPowerLimit1; -/** Offset 0x0CCF - PL1 timewindow +/** Offset 0x0CD7 - PL1 timewindow PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 **/ UINT8 PsysPowerLimit1Time; -/** Offset 0x0CD0 - PL2 Enable Value +/** Offset 0x0CD8 - PL2 Enable Value PL2 Enable activates the PL2 value to limit average platform power.0: Disable; 1: Enable. $EN_DIS **/ UINT8 PsysPowerLimit2; -/** Offset 0x0CD1 - Enable or Disable MLC Streamer Prefetcher +/** Offset 0x0CD9 - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MlcStreamerPrefetcher; -/** Offset 0x0CD2 - Enable or Disable MLC Spatial Prefetcher +/** Offset 0x0CDA - Enable or Disable MLC Spatial Prefetcher Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable $EN_DIS **/ UINT8 MlcSpatialPrefetcher; -/** Offset 0x0CD3 - Enable or Disable Monitor /MWAIT instructions +/** Offset 0x0CDB - Enable or Disable Monitor /MWAIT instructions Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MonitorMwaitEnable; -/** Offset 0x0CD4 - Enable or Disable initialization of machine check registers +/** Offset 0x0CDC - Enable or Disable initialization of machine check registers Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MachineCheckEnable; -/** Offset 0x0CD5 - AP Idle Manner of waiting for SIPI +/** Offset 0x0CDD - AP Idle Manner of waiting for SIPI AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. 1: HALT loop, 2: MWAIT loop, 3: RUN loop **/ UINT8 ApIdleManner; -/** Offset 0x0CD6 - Control on Processor Trace output scheme +/** Offset 0x0CDE - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. 0: Single Range Output, 1: ToPA Output **/ UINT8 ProcessorTraceOutputScheme; -/** Offset 0x0CD7 - Enable or Disable Processor Trace feature +/** Offset 0x0CDF - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcessorTraceEnable; -/** Offset 0x0CD8 - Enable or Disable Intel SpeedStep Technology +/** Offset 0x0CE0 - Enable or Disable Intel SpeedStep Technology Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable $EN_DIS **/ UINT8 Eist; -/** Offset 0x0CD9 - Enable or Disable Energy Efficient P-state +/** Offset 0x0CE1 - Enable or Disable Energy Efficient P-state Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; 1: Enable $EN_DIS **/ UINT8 EnergyEfficientPState; -/** Offset 0x0CDA - Enable or Disable Energy Efficient Turbo +/** Offset 0x0CE2 - Enable or Disable Energy Efficient Turbo Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnergyEfficientTurbo; -/** Offset 0x0CDB - Enable or Disable T states +/** Offset 0x0CE3 - Enable or Disable T states Enable or Disable T states; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 TStates; -/** Offset 0x0CDC - Enable or Disable Bi-Directional PROCHOT# +/** Offset 0x0CE4 - Enable or Disable Bi-Directional PROCHOT# Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable $EN_DIS **/ UINT8 BiProcHot; -/** Offset 0x0CDD - Enable or Disable PROCHOT# signal being driven externally +/** Offset 0x0CE5 - Enable or Disable PROCHOT# signal being driven externally Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DisableProcHotOut; -/** Offset 0x0CDE - Enable or Disable PROCHOT# Response +/** Offset 0x0CE6 - Enable or Disable PROCHOT# Response Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcHotResponse; -/** Offset 0x0CDF - Enable or Disable VR Thermal Alert +/** Offset 0x0CE7 - Enable or Disable VR Thermal Alert Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DisableVrThermalAlert; -/** Offset 0x0CE0 - Enable or Disable Thermal Reporting +/** Offset 0x0CE8 - Enable or Disable Thermal Reporting Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 EnableAllThermalFunctions; -/** Offset 0x0CE1 - Enable or Disable Thermal Monitor +/** Offset 0x0CE9 - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ThermalMonitor; -/** Offset 0x0CE2 - Enable or Disable CPU power states (C-states) +/** Offset 0x0CEA - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable $EN_DIS **/ UINT8 Cx; -/** Offset 0x0CE3 - Configure C-State Configuration Lock +/** Offset 0x0CEB - Configure C-State Configuration Lock Configure C-State Configuration Lock; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PmgCstCfgCtrlLock; -/** Offset 0x0CE4 - Enable or Disable Enhanced C-states +/** Offset 0x0CEC - Enable or Disable Enhanced C-states Enable or Disable Enhanced C-states. 0: Disable; 1: Enable $EN_DIS **/ UINT8 C1e; -/** Offset 0x0CE5 - Enable or Disable Package Cstate Demotion +/** Offset 0x0CED - Enable or Disable Package Cstate Demotion Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateDemotion; -/** Offset 0x0CE6 - Enable or Disable Package Cstate UnDemotion +/** Offset 0x0CEE - Enable or Disable Package Cstate UnDemotion Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateUnDemotion; -/** Offset 0x0CE7 - Enable or Disable CState-Pre wake +/** Offset 0x0CEF - Enable or Disable CState-Pre wake Enable or Disable CState-Pre wake. 0: Disable; 1: Enable $EN_DIS **/ UINT8 CStatePreWake; -/** Offset 0x0CE8 - Enable or Disable TimedMwait Support. +/** Offset 0x0CF0 - Enable or Disable TimedMwait Support. Enable or Disable TimedMwait Support. 0: Disable; 1: Enable $EN_DIS **/ UINT8 TimedMwait; -/** Offset 0x0CE9 - Enable or Disable IO to MWAIT redirection +/** Offset 0x0CF1 - Enable or Disable IO to MWAIT redirection Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 CstCfgCtrIoMwaitRedirection; -/** Offset 0x0CEA - Set the Max Pkg Cstate +/** Offset 0x0CF2 - Set the Max Pkg Cstate Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto **/ UINT8 PkgCStateLimit; -/** Offset 0x0CEB - TimeUnit for C-State Latency Control0 +/** Offset 0x0CF3 - TimeUnit for C-State Latency Control0 TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl0TimeUnit; -/** Offset 0x0CEC - TimeUnit for C-State Latency Control1 +/** Offset 0x0CF4 - TimeUnit for C-State Latency Control1 TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl1TimeUnit; -/** Offset 0x0CED - TimeUnit for C-State Latency Control2 +/** Offset 0x0CF5 - TimeUnit for C-State Latency Control2 TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl2TimeUnit; -/** Offset 0x0CEE - TimeUnit for C-State Latency Control3 +/** Offset 0x0CF6 - TimeUnit for C-State Latency Control3 TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl3TimeUnit; -/** Offset 0x0CEF - TimeUnit for C-State Latency Control4 +/** Offset 0x0CF7 - TimeUnit for C-State Latency Control4 Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl4TimeUnit; -/** Offset 0x0CF0 - TimeUnit for C-State Latency Control5 +/** Offset 0x0CF8 - TimeUnit for C-State Latency Control5 TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl5TimeUnit; -/** Offset 0x0CF1 - Interrupt Redirection Mode Select +/** Offset 0x0CF9 - Interrupt Redirection Mode Select Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7: No change. **/ UINT8 PpmIrmSetting; -/** Offset 0x0CF2 - Lock prochot configuration +/** Offset 0x0CFA - Lock prochot configuration Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ProcHotLock; -/** Offset 0x0CF3 - Configuration for boot TDP selection +/** Offset 0x0CFB - Configuration for boot TDP selection Deprecated. Move to premem. **/ UINT8 ConfigTdpLevel; -/** Offset 0x0CF4 - Max P-State Ratio +/** Offset 0x0CFC - Max P-State Ratio Max P-State Ratio, Valid Range 0 to 0x7F **/ UINT8 MaxRatio; -/** Offset 0x0CF5 - P-state ratios for custom P-state table +/** Offset 0x0CFD - P-state ratios for custom P-state table P-state ratios for custom P-state table. NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F **/ UINT8 StateRatio[40]; -/** Offset 0x0D1D - P-state ratios for max 16 version of custom P-state table +/** Offset 0x0D25 - P-state ratios for max 16 version of custom P-state table P-state ratios for max 16 version of custom P-state table. This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and @@ -3568,129 +3576,129 @@ **/ UINT8 StateRatioMax16[16]; -/** Offset 0x0D2D - Reserved +/** Offset 0x0D35 - Reserved **/ - UINT8 Reserved85; + UINT8 Reserved87; -/** Offset 0x0D2E - Platform Power Pmax +/** Offset 0x0D36 - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W **/ UINT16 PsysPmax; -/** Offset 0x0D30 - Interrupt Response Time Limit of C-State LatencyContol1 +/** Offset 0x0D38 - Interrupt Response Time Limit of C-State LatencyContol1 Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl1Irtl; -/** Offset 0x0D32 - Interrupt Response Time Limit of C-State LatencyContol2 +/** Offset 0x0D3A - Interrupt Response Time Limit of C-State LatencyContol2 Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl2Irtl; -/** Offset 0x0D34 - Interrupt Response Time Limit of C-State LatencyContol3 +/** Offset 0x0D3C - Interrupt Response Time Limit of C-State LatencyContol3 Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl3Irtl; -/** Offset 0x0D36 - Interrupt Response Time Limit of C-State LatencyContol4 +/** Offset 0x0D3E - Interrupt Response Time Limit of C-State LatencyContol4 Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl4Irtl; -/** Offset 0x0D38 - Interrupt Response Time Limit of C-State LatencyContol5 +/** Offset 0x0D40 - Interrupt Response Time Limit of C-State LatencyContol5 Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF. 0 is Auto. **/ UINT16 CstateLatencyControl5Irtl; -/** Offset 0x0D3A - Reserved +/** Offset 0x0D42 - Reserved **/ - UINT8 Reserved86[2]; + UINT8 Reserved88[2]; -/** Offset 0x0D3C - Package Long duration turbo mode power limit +/** Offset 0x0D44 - Package Long duration turbo mode power limit Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit1; -/** Offset 0x0D40 - Package Short duration turbo mode power limit +/** Offset 0x0D48 - Package Short duration turbo mode power limit Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit2Power; -/** Offset 0x0D44 - Package PL3 power limit +/** Offset 0x0D4C - Package PL3 power limit Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit3; -/** Offset 0x0D48 - Package PL4 power limit +/** Offset 0x0D50 - Package PL4 power limit Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit4; -/** Offset 0x0D4C - Tcc Offset Time Window for RATL +/** Offset 0x0D54 - Tcc Offset Time Window for RATL Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 TccOffsetTimeWindowForRatl; -/** Offset 0x0D50 - Short term Power Limit value for custom cTDP level 1 +/** Offset 0x0D58 - Short term Power Limit value for custom cTDP level 1 Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom1PowerLimit1; -/** Offset 0x0D54 - Long term Power Limit value for custom cTDP level 1 +/** Offset 0x0D5C - Long term Power Limit value for custom cTDP level 1 Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom1PowerLimit2; -/** Offset 0x0D58 - Short term Power Limit value for custom cTDP level 2 +/** Offset 0x0D60 - Short term Power Limit value for custom cTDP level 2 Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom2PowerLimit1; -/** Offset 0x0D5C - Long term Power Limit value for custom cTDP level 2 +/** Offset 0x0D64 - Long term Power Limit value for custom cTDP level 2 Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom2PowerLimit2; -/** Offset 0x0D60 - Short term Power Limit value for custom cTDP level 3 +/** Offset 0x0D68 - Short term Power Limit value for custom cTDP level 3 Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom3PowerLimit1; -/** Offset 0x0D64 - Long term Power Limit value for custom cTDP level 3 +/** Offset 0x0D6C - Long term Power Limit value for custom cTDP level 3 Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom3PowerLimit2; -/** Offset 0x0D68 - Platform PL1 power +/** Offset 0x0D70 - Platform PL1 power Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PsysPowerLimit1Power; -/** Offset 0x0D6C - Platform PL2 power +/** Offset 0x0D74 - Platform PL2 power Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PsysPowerLimit2Power; -/** Offset 0x0D70 - Race To Halt +/** Offset 0x0D78 - Race To Halt Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)Disable; 1: Enable @@ -3698,327 +3706,319 @@ **/ UINT8 RaceToHalt; -/** Offset 0x0D71 - Set Three Strike Counter Disable +/** Offset 0x0D79 - Set Three Strike Counter Disable False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True. 0: False, 1: True **/ UINT8 ThreeStrikeCounterDisable; -/** Offset 0x0D72 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT +/** Offset 0x0D7A - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 HwpInterruptControl; -/** Offset 0x0D73 - Reserved +/** Offset 0x0D7B - Reserved **/ - UINT8 Reserved87[4]; + UINT8 Reserved89[4]; -/** Offset 0x0D77 - Intel Turbo Boost Max Technology 3.0 +/** Offset 0x0D7F - Intel Turbo Boost Max Technology 3.0 Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled $EN_DIS **/ UINT8 EnableItbm; -/** Offset 0x0D78 - Enable or Disable C1 Cstate Demotion +/** Offset 0x0D80 - Enable or Disable C1 Cstate Demotion Enable or Disable C1 Cstate Demotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateAutoDemotion; -/** Offset 0x0D79 - Enable or Disable C1 Cstate UnDemotion +/** Offset 0x0D81 - Enable or Disable C1 Cstate UnDemotion Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateUnDemotion; -/** Offset 0x0D7A - Minimum Ring ratio limit override +/** Offset 0x0D82 - Minimum Ring ratio limit override Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MinRingRatioLimit; -/** Offset 0x0D7B - Maximum Ring ratio limit override +/** Offset 0x0D83 - Maximum Ring ratio limit override Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MaxRingRatioLimit; -/** Offset 0x0D7C - Enable or Disable Per Core P State OS control +/** Offset 0x0D84 - Enable or Disable Per Core P State OS control Enable or Disable Per Core P State OS control. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnablePerCorePState; -/** Offset 0x0D7D - Enable or Disable HwP Autonomous Per Core P State OS control +/** Offset 0x0D85 - Enable or Disable HwP Autonomous Per Core P State OS control Enable or Disable HwP Autonomous Per Core P State OS control. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableHwpAutoPerCorePstate; -/** Offset 0x0D7E - Enable or Disable HwP Autonomous EPP Grouping +/** Offset 0x0D86 - Enable or Disable HwP Autonomous EPP Grouping Enable or Disable HwP Autonomous EPP Grouping. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableHwpAutoEppGrouping; -/** Offset 0x0D7F - Enable or Disable EPB override over PECI +/** Offset 0x0D87 - Enable or Disable EPB override over PECI Enable or Disable EPB override over PECI. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableEpbPeciOverride; -/** Offset 0x0D80 - Enable or Disable Fast MSR for IA32_HWP_REQUEST +/** Offset 0x0D88 - Enable or Disable Fast MSR for IA32_HWP_REQUEST Enable or Disable Fast MSR for IA32_HWP_REQUEST. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableFastMsrHwpReq; -/** Offset 0x0D81 - Enable Configurable TDP +/** Offset 0x0D89 - Enable Configurable TDP Applies TDP initialization settings based on non-cTDP or cTDP.; 0: Applies to non-cTDP; 1: Applies to cTDP $EN_DIS **/ UINT8 ApplyConfigTdp; -/** Offset 0x0D82 - Reserved +/** Offset 0x0D8A - Reserved **/ - UINT8 Reserved88; + UINT8 Reserved90; -/** Offset 0x0D83 - Dual Tau Boost +/** Offset 0x0D8B - Dual Tau Boost Enable, Disable Dual Tau Boost feature. This is only applicable for Desktop; 0: Disable; 1: Enable $EN_DIS **/ UINT8 DualTauBoost; -/** Offset 0x0D84 - Reserved -**/ - UINT8 Reserved89; - -/** Offset 0x0D85 - Reserved -**/ - UINT8 Reserved90; - -/** Offset 0x0D86 - Reserved +/** Offset 0x0D8C - Reserved **/ UINT8 Reserved91; -/** Offset 0x0D87 - Reserved +/** Offset 0x0D8D - Reserved **/ - UINT8 Reserved92[13]; + UINT8 Reserved92; -/** Offset 0x0D94 - Reserved +/** Offset 0x0D8E - Reserved **/ - UINT8 Reserved93[16]; + UINT8 Reserved93; -/** Offset 0x0DA4 - End of Post message +/** Offset 0x0D8F - Reserved +**/ + UINT8 Reserved94[13]; + +/** Offset 0x0D9C - Reserved +**/ + UINT8 Reserved95[16]; + +/** Offset 0x0DAC - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved **/ UINT8 EndOfPostMessage; -/** Offset 0x0DA5 - D0I3 Setting for HECI Disable +/** Offset 0x0DAD - D0I3 Setting for HECI Disable Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices $EN_DIS **/ UINT8 DisableD0I3SettingForHeci; -/** Offset 0x0DA6 - Mctp Broadcast Cycle +/** Offset 0x0DAE - Mctp Broadcast Cycle Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MctpBroadcastCycle; -/** Offset 0x0DA7 - Enable LOCKDOWN SMI +/** Offset 0x0DAF - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. $EN_DIS **/ UINT8 PchLockDownGlobalSmi; -/** Offset 0x0DA8 - Enable LOCKDOWN BIOS Interface +/** Offset 0x0DB0 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. $EN_DIS **/ UINT8 PchLockDownBiosInterface; -/** Offset 0x0DA9 - Unlock all GPIO pads +/** Offset 0x0DB1 - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x0DAA - PCH Unlock SideBand access +/** Offset 0x0DB2 - PCH Unlock SideBand access The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. $EN_DIS **/ UINT8 PchSbAccessUnlock; -/** Offset 0x0DAB - Reserved +/** Offset 0x0DB3 - Reserved **/ - UINT8 Reserved94[1]; + UINT8 Reserved96[1]; -/** Offset 0x0DAC - PCIE RP Ltr Max Snoop Latency +/** Offset 0x0DB4 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ UINT16 PcieRpLtrMaxSnoopLatency[28]; -/** Offset 0x0DE4 - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x0DEC - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ UINT16 PcieRpLtrMaxNoSnoopLatency[28]; -/** Offset 0x0E1C - PCIE RP Snoop Latency Override Mode +/** Offset 0x0E24 - PCIE RP Snoop Latency Override Mode Latency Tolerance Reporting, Snoop Latency Override Mode. **/ UINT8 PcieRpSnoopLatencyOverrideMode[28]; -/** Offset 0x0E38 - PCIE RP Snoop Latency Override Multiplier +/** Offset 0x0E40 - PCIE RP Snoop Latency Override Multiplier Latency Tolerance Reporting, Snoop Latency Override Multiplier. **/ UINT8 PcieRpSnoopLatencyOverrideMultiplier[28]; -/** Offset 0x0E54 - PCIE RP Snoop Latency Override Value +/** Offset 0x0E5C - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value. **/ UINT16 PcieRpSnoopLatencyOverrideValue[28]; -/** Offset 0x0E8C - PCIE RP Non Snoop Latency Override Mode +/** Offset 0x0E94 - PCIE RP Non Snoop Latency Override Mode Latency Tolerance Reporting, Non-Snoop Latency Override Mode. **/ UINT8 PcieRpNonSnoopLatencyOverrideMode[28]; -/** Offset 0x0EA8 - PCIE RP Non Snoop Latency Override Multiplier +/** Offset 0x0EB0 - PCIE RP Non Snoop Latency Override Multiplier Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. **/ UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[28]; -/** Offset 0x0EC4 - PCIE RP Non Snoop Latency Override Value +/** Offset 0x0ECC - PCIE RP Non Snoop Latency Override Value Latency Tolerance Reporting, Non-Snoop Latency Override Value. **/ UINT16 PcieRpNonSnoopLatencyOverrideValue[28]; -/** Offset 0x0EFC - PCIE RP Slot Power Limit Scale +/** Offset 0x0F04 - PCIE RP Slot Power Limit Scale Specifies scale used for slot power limit value. Leave as 0 to set to default. **/ UINT8 PcieRpSlotPowerLimitScale[28]; -/** Offset 0x0F18 - PCIE RP Slot Power Limit Value +/** Offset 0x0F20 - PCIE RP Slot Power Limit Value Specifies upper limit on power supplie by slot. Leave as 0 to set to default. **/ UINT16 PcieRpSlotPowerLimitValue[28]; -/** Offset 0x0F50 - PCIE RP Enable Port8xh Decode +/** Offset 0x0F58 - PCIE RP Enable Port8xh Decode This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PcieEnablePort8xhDecode; -/** Offset 0x0F51 - PCIE Port8xh Decode Port Index +/** Offset 0x0F59 - PCIE Port8xh Decode Port Index The Index of PCIe Port that is selected for Port8xh Decode (0 Based). **/ UINT8 PchPciePort8xhDecodePortIndex; -/** Offset 0x0F52 - PCH Energy Reporting +/** Offset 0x0F5A - PCH Energy Reporting Disable/Enable PCH to CPU energy report feature. $EN_DIS **/ UINT8 PchPmDisableEnergyReport; -/** Offset 0x0F53 - PCH Sata Test Mode +/** Offset 0x0F5B - PCH Sata Test Mode Allow entrance to the PCH SATA test modes. $EN_DIS **/ UINT8 SataTestMode; -/** Offset 0x0F54 - PCH USB OverCurrent mapping lock enable +/** Offset 0x0F5C - PCH USB OverCurrent mapping lock enable If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. $EN_DIS **/ UINT8 PchXhciOcLock; -/** Offset 0x0F55 - Low Power Mode Enable/Disable config mask +/** Offset 0x0F5D - Low Power Mode Enable/Disable config mask Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4. **/ UINT8 PmcLpmS0ixSubStateEnableMask; -/** Offset 0x0F56 - PCIE RP Ltr Max Snoop Latency +/** Offset 0x0F5E - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ UINT16 CpuPcieRpLtrMaxSnoopLatency[4]; -/** Offset 0x0F5E - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x0F66 - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ UINT16 CpuPcieRpLtrMaxNoSnoopLatency[4]; -/** Offset 0x0F66 - PCIE RP Snoop Latency Override Mode +/** Offset 0x0F6E - PCIE RP Snoop Latency Override Mode Latency Tolerance Reporting, Snoop Latency Override Mode. **/ UINT8 CpuPcieRpSnoopLatencyOverrideMode[4]; -/** Offset 0x0F6A - PCIE RP Snoop Latency Override Multiplier +/** Offset 0x0F72 - PCIE RP Snoop Latency Override Multiplier Latency Tolerance Reporting, Snoop Latency Override Multiplier. **/ UINT8 CpuPcieRpSnoopLatencyOverrideMultiplier[4]; -/** Offset 0x0F6E - PCIE RP Snoop Latency Override Value +/** Offset 0x0F76 - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value. **/ UINT16 CpuPcieRpSnoopLatencyOverrideValue[4]; -/** Offset 0x0F76 - PCIE RP Non Snoop Latency Override Mode +/** Offset 0x0F7E - PCIE RP Non Snoop Latency Override Mode Latency Tolerance Reporting, Non-Snoop Latency Override Mode. **/ UINT8 CpuPcieRpNonSnoopLatencyOverrideMode[4]; -/** Offset 0x0F7A - PCIE RP Non Snoop Latency Override Multiplier +/** Offset 0x0F82 - PCIE RP Non Snoop Latency Override Multiplier Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. **/ UINT8 CpuPcieRpNonSnoopLatencyOverrideMultiplier[4]; -/** Offset 0x0F7E - PCIE RP Non Snoop Latency Override Value +/** Offset 0x0F86 - PCIE RP Non Snoop Latency Override Value Latency Tolerance Reporting, Non-Snoop Latency Override Value. **/ UINT16 CpuPcieRpNonSnoopLatencyOverrideValue[4]; -/** Offset 0x0F86 - PCIE RP Upstream Port Transmiter Preset +/** Offset 0x0F8E - PCIE RP Upstream Port Transmiter Preset Used during Gen3 Link Equalization. Used for all lanes. Default is 7. **/ UINT8 CpuPcieRpGen3Uptp[4]; -/** Offset 0x0F8A - PCIE RP Downstream Port Transmiter Preset +/** Offset 0x0F92 - PCIE RP Downstream Port Transmiter Preset Used during Gen3 Link Equalization. Used for all lanes. Default is 7. **/ UINT8 CpuPcieRpGen3Dptp[4]; -/** Offset 0x0F8E - PCIE RP Upstream Port Transmiter Preset +/** Offset 0x0F96 - PCIE RP Upstream Port Transmiter Preset Used during Gen4 Link Equalization. Used for all lanes. Default is 8. **/ UINT8 CpuPcieRpGen4Uptp[4]; -/** Offset 0x0F92 - PCIE RP Downstream Port Transmiter Preset +/** Offset 0x0F9A - PCIE RP Downstream Port Transmiter Preset Used during Gen4 Link Equalization. Used for all lanes. Default is 9. **/ UINT8 CpuPcieRpGen4Dptp[4]; -/** Offset 0x0F96 - Reserved -**/ - UINT8 Reserved95[4]; - -/** Offset 0x0F9A - Reserved -**/ - UINT8 Reserved96[4]; - /** Offset 0x0F9E - Reserved **/ UINT8 Reserved97[4]; @@ -4027,150 +4027,158 @@ **/ UINT8 Reserved98[4]; -/** Offset 0x0FA6 - FOMS Control Policy +/** Offset 0x0FA6 - Reserved +**/ + UINT8 Reserved99[4]; + +/** Offset 0x0FAA - Reserved +**/ + UINT8 Reserved100[4]; + +/** Offset 0x0FAE - FOMS Control Policy Choose the Foms Control Policy, Default = 0 0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms **/ UINT8 CpuPcieFomsCp[4]; -/** Offset 0x0FAA - PMC C10 dynamic threshold dajustment enable +/** Offset 0x0FB2 - PMC C10 dynamic threshold dajustment enable Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs $EN_DIS **/ UINT8 PmcC10DynamicThresholdAdjustment; -/** Offset 0x0FAB - P2P mode for PCIE RP +/** Offset 0x0FB3 - P2P mode for PCIE RP Enable/disable peer to peer mode for PCIE Root Ports. 0: Disable, 1: Enable. 0: Disable, 1: Enable **/ UINT8 CpuPcieRpPeerToPeerMode[4]; -/** Offset 0x0FAF - Reserved -**/ - UINT8 Reserved99[8]; - /** Offset 0x0FB7 - Reserved **/ - UINT8 Reserved100[8]; - -/** Offset 0x0FBF - Reserved -**/ UINT8 Reserved101[8]; -/** Offset 0x0FC7 - Reserved +/** Offset 0x0FBF - Reserved **/ UINT8 Reserved102[8]; +/** Offset 0x0FC7 - Reserved +**/ + UINT8 Reserved103[8]; + /** Offset 0x0FCF - Reserved **/ - UINT8 Reserved103; + UINT8 Reserved104[8]; -/** Offset 0x0FD0 - FspEventHandler +/** Offset 0x0FD7 - Reserved +**/ + UINT8 Reserved105; + +/** Offset 0x0FD8 - FspEventHandler Optional pointer to the boot loader's implementation of FSP_EVENT_HANDLER. **/ UINT32 FspEventHandler; -/** Offset 0x0FD4 - Enable VMD Global Mapping +/** Offset 0x0FDC - Enable VMD Global Mapping Enable/disable to VMD controller.0: Disable; 1: Enable(Default) $EN_DIS **/ UINT8 VmdGlobalMapping; -/** Offset 0x0FD5 - Reserved +/** Offset 0x0FDD - Reserved **/ - UINT8 Reserved104[4]; + UINT8 Reserved106[4]; -/** Offset 0x0FD9 - Reserved -**/ - UINT8 Reserved105; - -/** Offset 0x0FDA - Reserved -**/ - UINT8 Reserved106; - -/** Offset 0x0FDB - Reserved +/** Offset 0x0FE1 - Reserved **/ UINT8 Reserved107; -/** Offset 0x0FDC - Reserved +/** Offset 0x0FE2 - Reserved **/ - UINT32 Reserved108; + UINT8 Reserved108; -/** Offset 0x0FE0 - Reserved +/** Offset 0x0FE3 - Reserved **/ - UINT32 Reserved109; + UINT8 Reserved109; /** Offset 0x0FE4 - Reserved **/ - UINT32 Reserved110[2]; + UINT32 Reserved110; + +/** Offset 0x0FE8 - Reserved +**/ + UINT32 Reserved111; /** Offset 0x0FEC - Reserved **/ - UINT32 Reserved111[2]; + UINT32 Reserved112[2]; /** Offset 0x0FF4 - Reserved **/ - UINT32 Reserved112[2]; + UINT32 Reserved113[2]; /** Offset 0x0FFC - Reserved **/ - UINT32 Reserved113[2]; + UINT32 Reserved114[2]; /** Offset 0x1004 - Reserved **/ - UINT32 Reserved114[2]; + UINT32 Reserved115[2]; /** Offset 0x100C - Reserved **/ - UINT32 Reserved115[2]; + UINT32 Reserved116[2]; /** Offset 0x1014 - Reserved **/ - UINT32 Reserved116[2]; + UINT32 Reserved117[2]; /** Offset 0x101C - Reserved **/ - UINT32 Reserved117[2]; + UINT32 Reserved118[2]; /** Offset 0x1024 - Reserved **/ - UINT32 Reserved118[2]; + UINT32 Reserved119[2]; /** Offset 0x102C - Reserved **/ - UINT32 Reserved119[2]; + UINT32 Reserved120[2]; /** Offset 0x1034 - Reserved **/ - UINT32 Reserved120[2]; + UINT32 Reserved121[2]; /** Offset 0x103C - Reserved **/ - UINT32 Reserved121[2]; + UINT32 Reserved122[2]; /** Offset 0x1044 - Reserved **/ - UINT32 Reserved122[2]; + UINT32 Reserved123[2]; /** Offset 0x104C - Reserved **/ - UINT8 Reserved123[4]; + UINT32 Reserved124[2]; -/** Offset 0x1050 - Reserved +/** Offset 0x1054 - Reserved **/ - UINT64 Reserved124; + UINT8 Reserved125[4]; /** Offset 0x1058 - Reserved **/ - UINT32 Reserved125; + UINT64 Reserved126; -/** Offset 0x105C - Reserved +/** Offset 0x1060 - Reserved **/ - UINT8 Reserved126[2]; + UINT32 Reserved127; -/** Offset 0x105E - Reserved +/** Offset 0x1064 - Reserved **/ - UINT8 Reserved127[2]; + UINT8 Reserved128[2]; + +/** Offset 0x1066 - Reserved +**/ + UINT8 Reserved129[2]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -4189,11 +4197,11 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x1060 +/** Offset 0x1068 **/ - UINT8 UnusedUpdSpace41[6]; + UINT8 Rsvd44[6]; -/** Offset 0x1066 +/** Offset 0x106E **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/68495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If486867477c88ad3e2ec5041ef94a0c364f5dfd6 Gerrit-Change-Number: 68495 Gerrit-PatchSet: 3 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XL] Change in coreboot[master]: vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3361.07
by Nick Vaccaro (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Bora Guvendik, Zhixing Ma, Selma Bensaid. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68495 ) Change subject: vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3361.07 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If486867477c88ad3e2ec5041ef94a0c364f5dfd6 Gerrit-Change-Number: 68495 Gerrit-PatchSet: 2 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 20:44:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/amd/chausie/ec.c: Enable WLAN
by Fred Reitberger (Code Review) 07 Nov '22

07 Nov '22

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69319 ) Change subject: mb/amd/chausie/ec.c: Enable WLAN ...................................................................... mb/amd/chausie/ec.c: Enable WLAN Enable WLAN power and deassert the various radio disables. TEST=boot chausie Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I2d21905001fa776c0d5c864d83dcd697e3febe0a --- M src/mainboard/amd/chausie/ec.c 1 file changed, 30 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/69319/1 diff --git a/src/mainboard/amd/chausie/ec.c b/src/mainboard/amd/chausie/ec.c index 78465fa..f1e5284 100644 --- a/src/mainboard/amd/chausie/ec.c +++ b/src/mainboard/amd/chausie/ec.c @@ -18,14 +18,23 @@ #define EC_GPIO_A_ADDR 0xAA #define EC_GPIO_WWAN_PWREN BIT(3) +#define EC_GPIO_WLAN_PWREN BIT(4) #define EC_GPIO_M2_SSD0_PWREN BIT(6) #define EC_GPIO_LOM_PWREN BIT(7) +#define EC_GPIO_B_ADDR 0xAB +#define EC_GPIO_WL_RADIO_DIS BIT(0) +#define EC_GPIO_BT_RADIO_DIS BIT(2) +#define EC_GPIO_GNSS_RADIO_DIS_N BIT(5) +#define EC_GPIO_MAIN_RADIO_DIS_N BIT(6) +#define EC_GPIO_WWAN_POWER_OFF_N BIT(7) + #define EC_GPIO_C_ADDR 0xAC #define EC_GPIO_DT_N_WLAN_SW BIT(1) #define EC_GPIO_MP2_SEL BIT(2) #define EC_GPIO_WWAN_N_LOM_SW BIT(3) + #define EC_SW02_ADDR 0xB7 #define EC_SW02_MS BIT(7) @@ -46,9 +55,15 @@ ec_write(EC_GPIO_8_ADDR, tmp); tmp = ec_read(EC_GPIO_A_ADDR); - tmp |= EC_GPIO_M2_SSD0_PWREN | EC_GPIO_LOM_PWREN | EC_GPIO_WWAN_PWREN; + tmp |= EC_GPIO_M2_SSD0_PWREN | EC_GPIO_LOM_PWREN; + tmp |= EC_GPIO_WLAN_PWREN | EC_GPIO_WWAN_PWREN; ec_write(EC_GPIO_A_ADDR, tmp); + tmp = ec_read(EC_GPIO_B_ADDR); + tmp |= EC_GPIO_GNSS_RADIO_DIS_N | EC_GPIO_MAIN_RADIO_DIS_N; + tmp |= EC_GPIO_WWAN_POWER_OFF_N; + ec_write(EC_GPIO_B_ADDR, tmp); + tmp = ec_read(EC_GPIO_C_ADDR); tmp |= EC_GPIO_WWAN_N_LOM_SW | EC_GPIO_MP2_SEL | EC_GPIO_DT_N_WLAN_SW; ec_write(EC_GPIO_C_ADDR, tmp); -- To view, visit https://review.coreboot.org/c/coreboot/+/69319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d21905001fa776c0d5c864d83dcd697e3febe0a Gerrit-Change-Number: 69319 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2022