coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[XL] Change in coreboot[master]: vendorcode/amd/agesa/fam15tn: Drop unused platform
by 9elements QA (Code Review) 07 Nov '22

07 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69125 ) Change subject: vendorcode/amd/agesa/fam15tn: Drop unused platform ...................................................................... Patch Set 7: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134215 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134214 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/134213 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/134212 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/134211 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134210 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/134209 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/134208 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/134207 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/134206 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/134205 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/134204 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134203 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/134202 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/134201 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/134200 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I749cf33fad12bb9bc5cd5d682df2652107d60a0f Gerrit-Change-Number: 69125 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 20:14:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/morgana: Add 32M support
by Fred Reitberger (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Bao Zheng, Jason Glenesk, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69150 ) Change subject: soc/amd/morgana: Add 32M support ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69150/comment/c6042f91_337ffbe4 PS1, Line 24: If coreboot need to access bottom 16M, which in fact doesn't seem to > 'implimented' may be misspelled - perhaps 'implemented'? Please fix. https://review.coreboot.org/c/coreboot/+/69150/comment/612dacf0_77c669df PS1, Line 27: The bit 15 of soft fuse decides which (top or bottom) 16M is mapped to should this be bit 14? File src/soc/amd/morgana/Makefile.inc: https://review.coreboot.org/c/coreboot/+/69150/comment/cd235266_0d528560 PS1, Line 118: PSP_SOFTFUSE_BITS += 15 should this be bit 14? -- To view, visit https://review.coreboot.org/c/coreboot/+/69150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0b5a75f828033b29c378bed9a939b23d7f19140 Gerrit-Change-Number: 69150 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 07 Nov 2022 19:05:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: vendorcode/amd/agesa/fam14: Remove dropped platform
by 9elements QA (Code Review) 07 Nov '22

07 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69124 ) Change subject: vendorcode/amd/agesa/fam14: Remove dropped platform ...................................................................... Patch Set 6: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134199 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134198 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/134197 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/134196 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/134195 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134194 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/134193 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/134192 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/134191 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/134190 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/134189 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/134188 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134187 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/134186 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/134185 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/134184 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dd3ce763418ff767acd0c55be26a998df77081b Gerrit-Change-Number: 69124 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 19:02:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [WIP] Payloads: Add memtest86+ v6 to the build
by Martin L Roth (Code Review) 07 Nov '22

07 Nov '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69277 ) Change subject: [WIP] Payloads: Add memtest86+ v6 to the build ...................................................................... [WIP] Payloads: Add memtest86+ v6 to the build Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ie0eedc25fcf37b925b072ca809c019a599a20392 --- M payloads/external/Memtest86Plus/Kconfig.secondary M payloads/external/Memtest86Plus/Makefile 2 files changed, 62 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/69277/1 diff --git a/payloads/external/Memtest86Plus/Kconfig.secondary b/payloads/external/Memtest86Plus/Kconfig.secondary index 7c4da9e..2852867a 100644 --- a/payloads/external/Memtest86Plus/Kconfig.secondary +++ b/payloads/external/Memtest86Plus/Kconfig.secondary @@ -1,30 +1,44 @@ if MEMTEST_SECONDARY_PAYLOAD +comment "Memtest86+" + choice - prompt "Memtest86+ version" - default MEMTEST_STABLE + prompt "Memtest86+ 5/6" depends on MEMTEST_SECONDARY_PAYLOAD -config MEMTEST_STABLE - bool "Stable" - help - Stable Memtest86+ version. +config MEMTEST86PLUS_V5 + bool "Memtest86+ V5" - For reproducible builds, this option must be selected. -config MEMTEST_MASTER - bool "Master" +config MEMTEST86PLUS_V6 + bool "Memtest86+ V6" + +endchoice + +choice + prompt "Memtest86+ revision" + depends on MEMTEST_SECONDARY_PAYLOAD + +config MEMTEST_5_STABLE + bool "Memtest86+ Stable" + depends on MEMTEST86PLUS_V5 help - Newest Memtest86+ version. + Stable Memtest86+ 5 version from coreboot.org + +config MEMTEST_MASTER + bool "Memtest86+ Master" + help + Newest Memtest86+ version This option will fetch the newest version of the Memtest86+ code, updating as new changes are committed. This makes the build non-reproducible, as it can fetch different code each time. + config MEMTEST_REVISION - bool "git revision" + bool "Memtest86+ git revision" help Select this option if you have a specific commit or branch that you want to use as the revision from which to - build Memtest86+. This makes the build + build Memtest86+. Using a branch version may the build non-reproducible, as it can fetch different code each time. You will be able to specify the name of a branch or a commit id @@ -33,9 +47,10 @@ endchoice config MEMTEST_REVISION_ID - string "Insert a commit's SHA-1 or a branch name" + string "Insert a Memtest86+ 5 or 6 commit's SHA-1 or a branch name" depends on MEMTEST_REVISION - default "origin/master" + default "origin/main" if MEMTEST86PLUS_V6 + default "origin/master" if MEMTEST86PLUS_V5 help The commit's SHA-1 or branch name of the revision to use. diff --git a/payloads/external/Memtest86Plus/Makefile b/payloads/external/Memtest86Plus/Makefile index 3853cb9..e205149 100644 --- a/payloads/external/Memtest86Plus/Makefile +++ b/payloads/external/Memtest86Plus/Makefile @@ -1,25 +1,38 @@ ## SPDX-License-Identifier: GPL-2.0-only -TAG-$(CONFIG_MEMTEST_MASTER)=origin/master -NAME-$(CONFIG_MEMTEST_MASTER)=Master -TAG-$(CONFIG_MEMTEST_STABLE)=0bd34c22604660e4283316331f3e7bf8a3863753 -NAME-$(CONFIG_MEMTEST_STABLE)=Stable -TAG-$(CONFIG_MEMTEST_REVISION)=$(CONFIG_MEMTEST_REVISION_ID) - project_name=Memtest86+ project_dir=$(CURDIR)/memtest86plus -project_git_repo=https://review.coreboot.org/memtest86plus.git + +ifeq ($(MEMTEST86PLUS_V6),y) + project_git_repo=https://github.com/memtest86plus/memtest86plus.git + TAG-$(CONFIG_MEMTEST_MASTER)=origin/main + NAME-$(CONFIG_MEMTEST_MASTER)=Main + TAG-$(CONFIG_MEMTEST_REVISION)=$(CONFIG_MEMTEST_REVISION_ID) +else + project_git_repo=https://review.coreboot.org/memtest86plus.git + TAG-$(CONFIG_MEMTEST_MASTER)=origin/master + NAME-$(CONFIG_MEMTEST_MASTER)=Master + TAG-$(CONFIG_MEMTEST_STABLE)=0bd34c22604660e4283316331f3e7bf8a3863753 + NAME-$(CONFIG_MEMTEST_STABLE)=Stable + TAG-$(CONFIG_MEMTEST_REVISION)=$(CONFIG_MEMTEST_REVISION_ID) +endif + all: build -$(project_dir): +check_version: + if [ ! "$$(cd $(project_dir) git config remote.origin.url)" = "$(project_git_repo)" ]; then \ + rm -rf $(project_dir); \ + fi + +$(project_dir): check_version echo " Cloning $(project_name) from Git" git clone $(project_git_repo) $(project_dir) fetch: $(project_dir) ifeq ($(TAG-y),) echo "Error: The specified tag is invalid" -ifeq ($(CONFIG_MEMTEST_REVISION),y) +ifeq ($(CONFIG_MEMTEST_5_REVISION)$(CONFIG_MEMTEST_6_REVISION),y) echo "Error: There is no revision specified for $(project_name)" false endif @@ -50,4 +63,4 @@ print-repo-info: echo "$(project_git_repo) $(project_dir)" -.PHONY: all build checkout clean distclean fetch print-repo-info +.PHONY: all build checkout check_version clean distclean fetch print-repo-info -- To view, visit https://review.coreboot.org/c/coreboot/+/69277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0eedc25fcf37b925b072ca809c019a599a20392 Gerrit-Change-Number: 69277 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[XL] Change in coreboot[master]: {cpu/nb}/amd/family14: Remove platform
by 9elements QA (Code Review) 07 Nov '22

07 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69115 ) Change subject: {cpu/nb}/amd/family14: Remove platform ...................................................................... Patch Set 7: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 1 / 15 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134167 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134166 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/134165 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/134164 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/134163 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134162 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/134161 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/134160 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/134159 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/134158 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/134157 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134155 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/134154 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/134153 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/134152 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaac0a32e71d208b66fd2c4e26f5349abc921d4f Gerrit-Change-Number: 69115 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 18:07:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage
by Shelley Chen (Code Review) 07 Nov '22

07 Nov '22

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67673 ) Change subject: soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage ...................................................................... soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage As AOP takes 500 msec delay to get up, moving aop load and reset to romstage improves the performance. BUG=b:218406702 TEST=reboot from AP console (on CRD3) prior to fix (from cbmem dump): 1000:depthcharge start 1,139,809 (152,679) after fix (from cbmem dump): 1000:depthcharge start 1,041,109 (46,353) Signed-off-by: Sudheer Kumar Amrabadi <samrabad(a)codeaurora.org> Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67673 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/herobrine/romstage.c M src/soc/qualcomm/sc7280/Makefile.inc M src/soc/qualcomm/sc7280/memlayout.ld M src/soc/qualcomm/sc7280/soc.c 4 files changed, 29 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c index 24d0e28..43b72de 100644 --- a/src/mainboard/google/herobrine/romstage.c +++ b/src/mainboard/google/herobrine/romstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/stages.h> +#include <soc/aop_common.h> #include <soc/cpucp.h> #include <soc/qclib_common.h> #include <soc/shrm.h> @@ -25,6 +26,7 @@ cpucp_prepare(); /* QCLib: DDR init & train */ qclib_load_and_run(); + aop_fw_load_reset(); prepare_usb(); /* This rail needs to be stable by the time we take the FPMCU out of reset in ramstage, so already turn it on here. This needs to happen diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index 6280068..bd0afe4 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -36,6 +36,7 @@ romstage-y += mmu.c romstage-y += ../common/usb/usb.c romstage-y += carve_out.c +romstage-y += ../common/aop_load_reset.c romstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c ################################################################################ @@ -46,7 +47,6 @@ ramstage-y += ../common/usb/usb.c ramstage-y += ../common/usb/snps_usb_phy.c ramstage-y += ../common/usb/qmpv4_usb_phy.c -ramstage-y += ../common/aop_load_reset.c ramstage-y += cpucp_load_reset.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/edp_aux.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/edp_ctrl.c diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld index 0d8dafb..bf5272e 100644 --- a/src/soc/qualcomm/sc7280/memlayout.ld +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -34,8 +34,7 @@ REGION(pbl_timestamps, 0x14800000, 84K, 4K) WATCHDOG_TOMBSTONE(0x14818FFC, 4) BOOTBLOCK(0x14819000, 40K) - PRERAM_CBFS_CACHE(0x14823000, 70K) - PRERAM_CBMEM_CONSOLE(0x14834800, 32K) + PRERAM_CBFS_CACHE(0x14823000, 102K) TIMESTAMP(0x1483C800, 1K) TTB(0x1483D000, 56K) STACK(0x1484B000, 16K) @@ -49,7 +48,8 @@ REGION(pmic, 0x14866000, 96K, 4K) REGION(ddr_training, 0x1487E000, 32K, 4K) REGION(qclib, 0x14886000, 800K, 4K) - BSRAM_END(0x14950000) + PRERAM_CBMEM_CONSOLE(0x14950000, 32K) + BSRAM_END(0x14958000) DRAM_START(0x80000000) /* Various hardware/software subsystems make use of this area */ diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c index 02194a2..265a694 100644 --- a/src/soc/qualcomm/sc7280/soc.c +++ b/src/soc/qualcomm/sc7280/soc.c @@ -4,7 +4,6 @@ #include <soc/mmu.h> #include <soc/mmu_common.h> #include <soc/symbols_common.h> -#include <soc/aop_common.h> #include <soc/cpucp.h> #include <soc/pcie.h> @@ -32,7 +31,6 @@ static void soc_init(struct device *dev) { - aop_fw_load_reset(); cpucp_fw_load_reset(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/67673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4 Gerrit-Change-Number: 67673 Gerrit-PatchSet: 23 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: T.Michael Turney <tmiketurney(a)gmail.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage
by Shelley Chen (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Venkat Thogaru, Sudheer Amrabadi, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67673 ) Change subject: soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage ...................................................................... Patch Set 22: (2 comments) Patchset: PS18: > Hi Shelley, I can see with memlayout change of pmic, qclib memories, we were seeing issue. Done PS18: > I'm not seeing the 110ms boot time savings on herobrine, but it does seem to save something. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/67673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4 Gerrit-Change-Number: 67673 Gerrit-PatchSet: 22 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: T.Michael Turney <tmiketurney(a)gmail.com> Gerrit-Attention: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 07 Nov 2022 18:06:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage
by Shelley Chen (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Venkat Thogaru, Sudheer Amrabadi, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67673 ) Change subject: soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage ...................................................................... Patch Set 22: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4 Gerrit-Change-Number: 67673 Gerrit-PatchSet: 22 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: T.Michael Turney <tmiketurney(a)gmail.com> Gerrit-Attention: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 07 Nov 2022 18:05:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Update DPTC setting for EVT-SMT
by Isaac Lee (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Paul Menzel, Jon Murphy, Nelson Ye, Chris Wang, Martin Roth, Karthik Ramasubramanian. Isaac Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68742 ) Change subject: mb/google/skyrim/var/winterhold: Update DPTC setting for EVT-SMT ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Hi Tim, Karthik, Raul and Martin, could you take a look? Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/68742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4aa90304e1e7bda7d580de2582129191e9eb0e76 Gerrit-Change-Number: 68742 Gerrit-PatchSet: 4 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Isaac Lee <isaaclee(a)google.com> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 17:45:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Add fingerprint SPI
by Tarun Tuli (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Eran Mitrani, Subrata Banik, Kapil Porwal, Eric Lai. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66992 ) Change subject: mb/google/rex: Add fingerprint SPI ...................................................................... Patch Set 19: Code-Review+2 (1 comment) File src/mainboard/google/rex/variants/rex0/gpio.c: https://review.coreboot.org/c/coreboot/+/66992/comment/35265b5f_d269805b PS14, Line 439: /* GPP_B11 : [] ==> EN_FP_PWR */ : PAD_CFG_GPO(GPP_B11, 0, DEEP), > Not sure, but followed the same procedure as in https://review.coreboot. […] To be complete, I'd like us to measure (with oscilloscope) and record the timings so we can reference this again (e.g. prove that we are not violating the spec). 1) Period Power is OFF to FPMCU during a reboot 2) Timing between Power being applied to reset being de-asserted -- To view, visit https://review.coreboot.org/c/coreboot/+/66992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e6be24e72a8232ae2c958a01cf8ea9a272d7365 Gerrit-Change-Number: 66992 Gerrit-PatchSet: 19 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 17:36:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Eran Mitrani <mitrani(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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