coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[M] Change in coreboot[master]: include/cpu/msr.h: transform into an union
by Arthur Heymans (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Arthur Heymans. Hello Marc Jones, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68572 to look at the new patch set (#3). Change subject: include/cpu/msr.h: transform into an union ...................................................................... include/cpu/msr.h: transform into an union This makes it easier to get the content of an msr into a full 64bit variable. Change-Id: I1b026cd3807fd68d805051a74b3d31fcde1c5626 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mtrr/earlymtrr.c M src/include/cpu/x86/msr.h M src/include/cpu/x86/msr_access.h M src/soc/intel/common/block/sgx/sgx.c 4 files changed, 39 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/68572/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b026cd3807fd68d805051a74b3d31fcde1c5626 Gerrit-Change-Number: 68572 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: mb/google/brya/var/gladios: Include GL9750 driver support
by Kevin Chiu (Code Review) 10 Nov '22

10 Nov '22

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69436 ) Change subject: mb/google/brya/var/gladios: Include GL9750 driver support ...................................................................... mb/google/brya/var/gladios: Include GL9750 driver support BUG=b:239513596 TEST=emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Change-Id: I7411e10348c36786000c6918b9b154b7329f3cd0 --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/69436/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 2102961..94aa197 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -299,6 +299,7 @@ bool "-> Gladios" select BOARD_GOOGLE_BASEBOARD_BRASK select SOC_INTEL_RAPTORLAKE + select DRIVERS_GENESYSLOGIC_GL9750 config BOARD_GOOGLE_MARASOV bool "-> Marasov" -- To view, visit https://review.coreboot.org/c/coreboot/+/69436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7411e10348c36786000c6918b9b154b7329f3cd0 Gerrit-Change-Number: 69436 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: configs: Build test STB features on google skyrim
by Fred Reitberger (Code Review) 10 Nov '22

10 Nov '22

Fred Reitberger has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68928 ) Change subject: configs: Build test STB features on google skyrim ...................................................................... configs: Build test STB features on google skyrim - Update the google_skyrim.with_binaries to test printing the STB entries. - Add a new saved config to test building without video, building using an x86 verstage, and STB_SPILL_TO_DRAM Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Idddcf2441b91b79575e5dfed1cc56d207234205b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68928 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Jon Murphy <jpmurphy(a)google.com> --- A configs/config.google_skyrim.no_video M configs/config.google_skyrim.with_binaries 2 files changed, 46 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jon Murphy: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/configs/config.google_skyrim.no_video b/configs/config.google_skyrim.no_video new file mode 100644 index 0000000..f36a3ff --- /dev/null +++ b/configs/config.google_skyrim.no_video @@ -0,0 +1,25 @@ +CONFIG_USE_AMD_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_AMD_FWM_POSITION_INDEX=4 +CONFIG_VBOOT=y +CONFIG_VBOOT_SLOTS_RW_A=y +# CONFIG_DRIVERS_INTEL_WIFI is not set +CONFIG_BOARD_GOOGLE_SKYRIM=y +CONFIG_VBOOT_FWID_MODEL="Google_$(CONFIG_MAINBOARD_PART_NUMBER)" +CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_ASYNC_FILE_LOADING=y +# CONFIG_ACPI_BERT is not set +# CONFIG_ACPI_SSDT_PSD_INDEPENDENT is not set +CONFIG_ENABLE_STB_SPILL_TO_DRAM=y +CONFIG_AMD_STB_SIZE_IN_MB=3 +CONFIG_NO_GFX_INIT=y +CONFIG_VPD=y +CONFIG_CBFS_MCACHE_RW_PERCENTAGE=50 +CONFIG_GBB_FLAG_DEV_SCREEN_SHORT_DELAY=y +CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y +CONFIG_VBOOT_KEYBLOCK_VERSION=1 +CONFIG_VBOOT_KEYBLOCK_PREAMBLE_FLAGS=0x0 +CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y +CONFIG_POST_IO_PORT=0x80 +# CONFIG VBOOT_STARTS_BEFORE_BOOTBLOCK is not set diff --git a/configs/config.google_skyrim.with_binaries b/configs/config.google_skyrim.with_binaries index d0227af..530ace4 100644 --- a/configs/config.google_skyrim.with_binaries +++ b/configs/config.google_skyrim.with_binaries @@ -27,3 +27,5 @@ CONFIG_DISPLAY_FSP_HEADER=y CONFIG_FATAL_ASSERTS=y CONFIG_DEBUG_SMI=y +CONFIG_WRITE_STB_BUFFER_TO_CONSOLE=y +CONFIG_ADD_POSTCODES_TO_STB=y -- To view, visit https://review.coreboot.org/c/coreboot/+/68928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idddcf2441b91b79575e5dfed1cc56d207234205b Gerrit-Change-Number: 68928 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Fred Reitberger <fred.reitberger(a)amd.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: util/amdfwtool: Remove duplicate ALIGN and ARRAY_SIZE definition
by Elyes Haouas (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Arthur Heymans, Martin Roth, Karthik Ramasubramanian, Felix Held. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69439 ) Change subject: util/amdfwtool: Remove duplicate ALIGN and ARRAY_SIZE definition ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabff06fa47a1badb0ce9815261117916664f3e03 Gerrit-Change-Number: 69439 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 10 Nov 2022 12:47:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: util/amdfwtool: Remove duplicate ALIGN and ARRAY_SIZE definition
by Elyes Haouas (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Arthur Heymans, Martin Roth, Karthik Ramasubramanian, Felix Held. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69439 ) Change subject: util/amdfwtool: Remove duplicate ALIGN and ARRAY_SIZE definition ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Please sée https://review.coreboot.org/c/coreboot/+/68376 -- To view, visit https://review.coreboot.org/c/coreboot/+/69439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabff06fa47a1badb0ce9815261117916664f3e03 Gerrit-Change-Number: 69439 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 10 Nov 2022 12:44:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: cpu/x86: Set thread local storage in C code
by build bot (Jenkins) (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Raul Rangel. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69435 ) Change subject: cpu/x86: Set thread local storage in C code ...................................................................... Patch Set 2: (1 comment) File src/cpu/x86/mp_init.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163197): https://review.coreboot.org/c/coreboot/+/69435/comment/b48458f9_3f256b7b PS2, Line 179: static void asmlinkage ap_init(unsigned int index) storage class 'asmlinkage' should be located before type 'void' -- To view, visit https://review.coreboot.org/c/coreboot/+/69435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19d3285daf97798a2d28408b5601ad991e29e718 Gerrit-Change-Number: 69435 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Thu, 10 Nov 2022 12:42:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: cpu/x86: Set thread local storage in C code
by Arthur Heymans (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Raul Rangel. Hello Raul Rangel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69435 to look at the new patch set (#2). Change subject: cpu/x86: Set thread local storage in C code ...................................................................... cpu/x86: Set thread local storage in C code Doing this in C code is way easier to understand. Also the thread local storage is now in .bss instead of the AP stack. This makes it more robust against stack overflows, as APs stacks overflow in each other. TESTED: work on qemu. Change-Id: I19d3285daf97798a2d28408b5601ad991e29e718 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/c_start.S M src/arch/x86/cpu.c M src/arch/x86/include/arch/cpu.h D src/cpu/x86/cpu_info.S.inc M src/cpu/x86/mp_init.c M src/cpu/x86/sipi_vector.S 6 files changed, 71 insertions(+), 109 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/69435/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19d3285daf97798a2d28408b5601ad991e29e718 Gerrit-Change-Number: 69435 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: cpu/x86: Set thread local storage in C code
by build bot (Jenkins) (Code Review) 10 Nov '22

10 Nov '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69435 ) Change subject: cpu/x86: Set thread local storage in C code ...................................................................... Patch Set 1: (1 comment) File src/cpu/x86/mp_init.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163196): https://review.coreboot.org/c/coreboot/+/69435/comment/517f05f1_a5413a29 PS1, Line 179: static void asmlinkage ap_init(unsigned int index) storage class 'asmlinkage' should be located before type 'void' -- To view, visit https://review.coreboot.org/c/coreboot/+/69435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19d3285daf97798a2d28408b5601ad991e29e718 Gerrit-Change-Number: 69435 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Nov 2022 12:39:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: cpu/x86: Set thread local storage in C code
by Arthur Heymans (Code Review) 10 Nov '22

10 Nov '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69435 ) Change subject: cpu/x86: Set thread local storage in C code ...................................................................... cpu/x86: Set thread local storage in C code Doing this in C code is way easier to understand. Also the thread local storage is now in .bss instead of the AP stack. This makes it more robust against stack overflows, as APs stacks overflow in each other. TESTED: work on qemu. Change-Id: I19d3285daf97798a2d28408b5601ad991e29e718 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/c_start.S M src/arch/x86/cpu.c M src/arch/x86/include/arch/cpu.h D src/cpu/x86/cpu_info.S.inc M src/cpu/x86/mp_init.c M src/cpu/x86/sipi_vector.S 6 files changed, 72 insertions(+), 110 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/69435/1 diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 02a9b89..5b7052e 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cpu/x86/cpu_info.S.inc> #include <cpu/x86/post_code.h> #include <arch/ram_segs.h> @@ -78,21 +77,6 @@ movl $_estack, %esp andl $(~(CONFIG_STACK_SIZE-1)), %esp - push_cpu_info - - /* Allocate the per_cpu_segment_data on the stack */ - push_per_cpu_segment_data - - /* - * Update the BSP's per_cpu_segment_descriptor to point to the - * per_cpu_segment_data that was allocated on the stack. - */ - set_segment_descriptor_base $per_cpu_segment_descriptors, %esp - - mov $per_cpu_segment_selector, %eax - movl (%eax), %eax - mov %eax, %gs - /* * Now we are finished. Memory is up, data is copied and * bss is cleared. Now we call the main routine and diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index f4cb83a..56ee1ec 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -6,6 +6,7 @@ #include <cpu/cpu.h> #include <post.h> #include <string.h> +#include <cpu/x86/gdt.h> #include <cpu/x86/mp.h> #include <cpu/x86/lapic.h> #include <cpu/x86/tsc.h> @@ -340,3 +341,41 @@ } return -1; } + +/* cpu_info() looks at address 0 at the base of %gs for a pointer to struct cpu_info */ +static struct cpu_info *cpu_infos_ptr[CONFIG_MAX_CPUS]; +static struct cpu_info cpu_infos[CONFIG_MAX_CPUS]; + +enum cb_err set_cpu_info(unsigned int index, struct device *cpu) +{ + if (index >= ARRAY_SIZE(cpu_infos)) + return CB_ERR; + + if (!cpu) + return CB_ERR; + + const struct cpu_info info = { .cpu = cpu, .index = index}; + cpu_infos[index] = info; + cpu_infos_ptr[index] = &cpu_infos[index]; + + struct segment_descriptor { + uint16_t segment_limit_0_15; + uint16_t base_address_0_15; + uint8_t base_address_16_23; + uint8_t attrs[2]; + uint8_t base_address_24_31; + } *segment_descriptor = (void *)&per_cpu_segment_descriptors; + + segment_descriptor[index].base_address_0_15 = (uintptr_t)&cpu_infos_ptr[index]; + segment_descriptor[index].base_address_16_23 = ((uintptr_t)&cpu_infos_ptr[index] >> 16); + segment_descriptor[index].base_address_24_31 = ((uintptr_t)&cpu_infos_ptr[index] >> 24); + + const unsigned int cpu_segment = per_cpu_segment_selector + (index << 3); + + __asm__ __volatile__ ("mov %0, %%gs\n" + : + : "r" (cpu_segment) + : ); + + return CB_SUCCESS; +} diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 0087a79..c7c6b4e 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -147,11 +147,13 @@ struct cpu_info *cpu_info; }; +enum cb_err set_cpu_info(unsigned int index, struct device *cpu); + static inline struct cpu_info *cpu_info(void) { struct cpu_info *ci = NULL; - __asm__("mov %%gs:%c[offset], %[ci]" + __asm__ __volatile__("mov %%gs:%c[offset], %[ci]" : [ci] "=r" (ci) : [offset] "i" (offsetof(struct per_cpu_segment_data, cpu_info)) ); diff --git a/src/cpu/x86/cpu_info.S.inc b/src/cpu/x86/cpu_info.S.inc deleted file mode 100644 index 6dca920..0000000 --- a/src/cpu/x86/cpu_info.S.inc +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * Pushes a 32-bit register onto the stack. - * - * There are two possible code sections where this code can be included: - * .code32 and .code64 - * - * Doing a `push %eax` while in a .code64 section will result in a compiler - * error. This macro manually pushes the 32-bit register onto the stack so we - * can share the code between 32 and 64 bit builds. - */ -.macro pushr reg:req -#if ENV_X86_64 - movl $0, -4(%esp) - movl \reg, -8(%esp) - sub $8, %esp -#else - push \reg -#endif -.endm - -/* Push struct cpu_info */ -.macro push_cpu_info index=$0 - pushr \index /* index (size_t) */ - pushr $0 /* *cpu */ -.endm - -/* Push struct per_cpu_segment_data */ -.macro push_per_cpu_segment_data cpu_info_pointer=%esp - pushr \cpu_info_pointer /* *cpu_info */ -.endm - -/* - * Sets the base address in the segment descriptor array. - * - * A segment descriptor has the following structure: - * struct { - * uint16_t segment_limit_0_15; - * uint16_t base_address_0_15; - * uint8_t base_address_16_23; - * uint8_t attrs[2]; - * uint8_t base_address_24_31; - * }; - * - * @desc_array: Address of the descriptor table - * @base: Address to set in the descriptor - * @desc_index: Index of the descriptor in the table. Defaults to 0. Must be a - * register if specified. - * - * Clobbers %eax, %ebx. - */ -.macro set_segment_descriptor_base desc_array:req, base:req, desc_index - mov \base, %eax - - mov \desc_array, %ebx - -.ifb \desc_index - movw %ax, 2(%ebx) - shr $16, %eax - movb %al, 4(%ebx) - shr $8, %eax - movb %al, 7(%ebx) -.else - movw %ax, 2(%ebx, \desc_index, 8) - shr $16, %eax - movb %al, 4(%ebx, \desc_index, 8) - shr $8, %eax - movb %al, 7(%ebx, \desc_index, 8) -.endif - -.endm diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 0e4a571..67ea6f4 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -176,20 +176,19 @@ /* By the time APs call ap_init() caching has been setup, and microcode has * been loaded. */ -static void asmlinkage ap_init(void) +static void asmlinkage ap_init(unsigned int index) { - struct cpu_info *info = cpu_info(); - /* Ensure the local APIC is enabled */ enable_lapic(); setup_lapic_interrupts(); struct device *dev = g_cpu_bus->children; - for (unsigned int i = info->index; i > 0; i--) + for (unsigned int i = index; i > 0; i--) dev = dev->sibling; - info->cpu = dev; + set_cpu_info(index, dev); + struct cpu_info *info = cpu_info(); cpu_add_map_entry(info->index); /* Fix up APIC id with reality. */ @@ -199,7 +198,7 @@ printk(BIOS_INFO, "AP: slot %zu apic_id %x, MCU rev: 0x%08x\n", info->index, info->cpu->path.apic.apic_id, get_current_microcode_rev()); else - printk(BIOS_INFO, "AP: slot %zu apic_id %x\n", info->index, + printk(BIOS_INFO, "AP: slot %u apic_id %x\n", index, info->cpu->path.apic.apic_id); /* Walk the flight plan */ @@ -540,6 +539,7 @@ } /* Find the device structure for the boot CPU. */ + set_cpu_info(0, bsp); info = cpu_info(); info->cpu = bsp; info->cpu->name = processor_name; diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index b8cac96..2a19404 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cpu/x86/cpu_info.S.inc> #include <cpu/x86/cr.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/msr.h> @@ -104,19 +103,8 @@ subl %eax, %edx mov %edx, %esp - push_cpu_info index=%ecx - push_per_cpu_segment_data - - /* - * Update the AP's per_cpu_segment_descriptor to point to the - * per_cpu_segment_data that was allocated on the stack. - */ - set_segment_descriptor_base per_cpu_segment_descriptors, %esp, %ecx - - mov %ecx, %eax - shl $3, %eax /* The index is << 3 in the segment selector */ - add per_cpu_segment_selector, %eax - mov %eax, %gs + /* Save CPU number for calling the AP entry */ + push %ecx /* * The following code only needs to run on Intel platforms and thus the caller @@ -230,15 +218,20 @@ mov %eax, %cr4 #endif + pop %ebx /* Retrieve cpu index */ andl $0xfffffff0, %esp /* ensure stack alignment */ #if ENV_X86_64 /* entry64.inc preserves ebx. */ #include <cpu/x86/64bit/entry64.inc> - + mov %rbx, %rdi movabs c_handler, %eax call *%rax #else + push $0 + push $0 + push $0 + push %ebx mov c_handler, %eax call *%eax #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/69435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19d3285daf97798a2d28408b5601ad991e29e718 Gerrit-Change-Number: 69435 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: mb/google/geralt: Fix incorrect timestamps in the eventlog
by Rex-BC Chen (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, Yidi Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69432 ) Change subject: mb/google/geralt: Fix incorrect timestamps in the eventlog ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69432/comment/e04691ca_a2474bb8 PS2, Line 12: BUG=b:233720142 : TEST=check the timestamp field in /var/log/eventlog.txt move above change-id -- To view, visit https://review.coreboot.org/c/coreboot/+/69432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddad102dc8d60de01a691d330deb8247e99c616a Gerrit-Change-Number: 69432 Gerrit-PatchSet: 2 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 12:01:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2022