coreboot-gerrit November 2022

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[L] Change in coreboot[master]: security/tpm: resolve conflicts in TSS implementations
by Yu-Ping Wu (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Michał Żygowski, Frans Hendriks, Matt DeVillier, Christian Walter, Krystian Hebel, Fred Reitberger, Sergii Dmytruk, Felix Held. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69160 ) Change subject: security/tpm: resolve conflicts in TSS implementations ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69160/comment/71af5d16_c1d4620b PS4, Line 8: I suppose the goal is compile both TPM1 and TPM2 code at the same time (CB:69162). Could you explain why we need to do that, or why that is considered better? -- To view, visit https://review.coreboot.org/c/coreboot/+/69160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0ea5a917c46ada9fc3274f17240e12bca98db6a Gerrit-Change-Number: 69160 Gerrit-PatchSet: 4 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 10 Nov 2022 08:28:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: sb/intel/i82801dx/lpc.c: Use {read,write}_pmbase32
by Elyes Haouas (Code Review) 10 Nov '22

10 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69441 ) Change subject: sb/intel/i82801dx/lpc.c: Use {read,write}_pmbase32 ...................................................................... sb/intel/i82801dx/lpc.c: Use {read,write}_pmbase32 Change-Id: I36c7731f5201d4507b0b1ce792e5d907c07c70cd Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801dx/lpc.c 1 file changed, 14 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/69441/1 diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 6f5adc694..c6cd9cd 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -12,6 +12,7 @@ #include <pc80/i8259.h> #include <pc80/isa-dma.h> #include <pc80/mc146818rtc.h> +#include <southbridge/intel/common/pmbase.h> #include <types.h> #include "chip.h" @@ -84,7 +85,7 @@ static void i82801dx_power_options(struct device *dev) { u8 reg8; - u16 reg16, pmbase; + u16 reg16, u32 reg32; const char *state; @@ -145,14 +146,12 @@ reg16 |= (1 << 5); // CPUSLP_EN Desktop only pci_write_config16(dev, GEN_PMCON_1, reg16); - pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - /* Set up power management block and determine sleep mode */ - reg32 = inl(pmbase + 0x04); // PM1_CNT + reg32 = read_pmbase32(PM1_CNT); reg32 &= ~(7 << 10); // SLP_TYP reg32 |= (1 << 0); // SCI_EN - outl(reg32, pmbase + 0x04); + write_pmbase32(PM1_CNT, reg32); } static void gpio_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/69441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36c7731f5201d4507b0b1ce792e5d907c07c70cd Gerrit-Change-Number: 69441 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: sb/intel/i82801dx: Clean up includes
by Elyes Haouas (Code Review) 10 Nov '22

10 Nov '22

Elyes Haouas has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/69440 ) Change subject: sb/intel/i82801dx: Clean up includes ...................................................................... sb/intel/i82801dx: Clean up includes Change-Id: Ib8bfafe9b359856ccfb11a70ab5a6c1ffd453c54 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801dx/ac97.c M src/southbridge/intel/i82801dx/i82801dx.c M src/southbridge/intel/i82801dx/ide.c M src/southbridge/intel/i82801dx/lpc.c 4 files changed, 22 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/69440/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8bfafe9b359856ccfb11a70ab5a6c1ffd453c54 Gerrit-Change-Number: 69440 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: src/drivers/usb: Add support for Bluetooth PPAG
by Meera Ravindranath (Code Review) 10 Nov '22

10 Nov '22

Meera Ravindranath has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/69431 ) Change subject: src/drivers/usb: Add support for Bluetooth PPAG ...................................................................... src/drivers/usb: Add support for Bluetooth PPAG Add support for BT PPAG ACPI bios configuration table as per 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev7_1. BUG=b:232915103 TEST=Build,boot the platform and check if the below structure is is visible in the SSDT dump Name (PPAG, Package (0x02) { 0x00000001, Package (0x02) { 0x00000012, 0x00000000 } }) Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: Ie264edf188532fe6c260275edaa694cf3b3605d3 --- M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/usb_acpi.c 2 files changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/69431/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie264edf188532fe6c260275edaa694cf3b3605d3 Gerrit-Change-Number: 69431 Gerrit-PatchSet: 2 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: src/drivers/usb: Add support for Bluetooth PPAG
by Meera Ravindranath (Code Review) 10 Nov '22

10 Nov '22

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69431 ) Change subject: src/drivers/usb: Add support for Bluetooth PPAG ...................................................................... src/drivers/usb: Add support for Bluetooth PPAG Add support for BT PPAG ACPI bios configuration table as per 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev7_1. BUG=b:232915103 TEST=Build,boot the platform and check if the below structure is is visible in the SSDT dump Name (PPAG, Package (0x02) { 0x00000001, Package (0x02) { 0x00000012, 0x00000000 } }) Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: Ie264edf188532fe6c260275edaa694cf3b3605d3 --- M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/usb_acpi.c 2 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/69431/1 diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index 4adffcf..3d3bd0d 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -60,6 +60,9 @@ /* Delay to be inserted after device is disabled. */ unsigned int enable_off_delay_ms; + /* BT PPAG */ + bool bt_ppag_config; + unsigned int bt_ppag_mode; /* * Define a GPIO that shows the privacy status of the USB device. * E.g. On a camera: if it is one, it is recording black frames. diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index f72129c..dfd88e2 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -8,6 +8,9 @@ #include <device/path.h> #include "chip.h" +#define DOMAIN_TYPE_BT 0x12 +#define PPAG_REVISION 1 + static bool usb_acpi_add_gpios_to_crs(struct drivers_usb_acpi_config *cfg) { if (cfg->privacy_gpio.pin_count) @@ -51,11 +54,34 @@ acpigen_write_name_string("_DDN", config->desc); acpigen_write_upc(config->type); + /* + * Name ("PPAG", Package () { + * Revision, + * Package () { + * Domain Type, // 0x12: BT Core + * PPAG Mode, // Defines the mode of ANT_gain control to be used + * } + * }) + */ + + if (config->bt_ppag_config == true) { + acpigen_write_name("PPAG"); + acpigen_write_package(2); + acpigen_write_dword(PPAG_REVISION); + acpigen_write_package(2); + acpigen_write_dword(DOMAIN_TYPE_BT); + acpigen_write_dword(config->bt_ppag_mode); + + acpigen_write_package_end(); + acpigen_write_package_end(); + } + if (usb_acpi_get_pld(dev, &pld)) acpigen_write_pld(&pld); else printk(BIOS_ERR, "Error retrieving PLD for %s\n", path); + /* Resources */ if (usb_acpi_add_gpios_to_crs(config) == true) { struct acpi_dp *dsd; -- To view, visit https://review.coreboot.org/c/coreboot/+/69431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie264edf188532fe6c260275edaa694cf3b3605d3 Gerrit-Change-Number: 69431 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: Revert "crossgcc: Upgrade IASL from 20211217 to 20220331"
by Elyes Haouas (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Martin L Roth, Arthur Heymans, Felix Held. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64103 ) Change subject: Revert "crossgcc: Upgrade IASL from 20211217 to 20220331" ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Please review https://review.coreboot.org/c/coreboot/+/68936 and https://review.coreboot.org/c/coreboot/+/68929 when you have time. IASL 20221020 should fix the issue https://github.com/acpica/acpica/issues/774 -- To view, visit https://review.coreboot.org/c/coreboot/+/64103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c1b30585fdfab046a40d1721276d0fa40457a10 Gerrit-Change-Number: 64103 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 10 Nov 2022 08:06:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/phy/m88e1512: Provide functionality to customize LED status
by Mario Scheithauer (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69386 ) Change subject: drivers/phy/m88e1512: Provide functionality to customize LED status ...................................................................... Patch Set 7: (1 comment) File src/drivers/phy/m88e1512/chip.h: https://review.coreboot.org/c/coreboot/+/69386/comment/ac8a0132_fa36a914 PS6, Line 10: INTn is brought out LED[2] > INTn can be routed to LED[2] pin removed in this patch -- To view, visit https://review.coreboot.org/c/coreboot/+/69386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia71c43f4286f9201f03cb759252ebb405ab81904 Gerrit-Change-Number: 69386 Gerrit-PatchSet: 7 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 07:58:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/phy/m88e1512: Provide functionality to customize LED status
by Mario Scheithauer (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69386 ) Change subject: drivers/phy/m88e1512: Provide functionality to customize LED status ...................................................................... Patch Set 7: (1 comment) File src/drivers/phy/m88e1512/m88e1512.c: https://review.coreboot.org/c/coreboot/+/69386/comment/28c6a427_4278c1a0 PS6, Line 34: /* Set INTn output to be brought out on LED[2]. */ : page_reg = mdio_ops->read(parent, dev->path.pnp.device, : LED_TIMER_CTRL_REG); : setbits16(&page_reg, (config->irq_led_2_enable << 7)); : mdio_ops->write(parent, dev->path.pnp.device, LED_TIMER_CTRL_REG, : page_reg); > This should be a separate setting as we need to keep cases in mind where a board can have connected […] Ack. I will make a separate commit for this. -- To view, visit https://review.coreboot.org/c/coreboot/+/69386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia71c43f4286f9201f03cb759252ebb405ab81904 Gerrit-Change-Number: 69386 Gerrit-PatchSet: 7 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 07:56:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/phy/m88e1512: Provide functionality to customize LED status
by build bot (Jenkins) (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Mario Scheithauer. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69386 ) Change subject: drivers/phy/m88e1512: Provide functionality to customize LED status ...................................................................... Patch Set 7: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163172): https://review.coreboot.org/c/coreboot/+/69386/comment/58714b98_7e372ba3 PS7, Line 14: https://web.archive.org/web/20221109080111/https://www.marvell.com/content/… Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia71c43f4286f9201f03cb759252ebb405ab81904 Gerrit-Change-Number: 69386 Gerrit-PatchSet: 7 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 07:53:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driver
by Mario Scheithauer (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Werner Zeh. Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69387 to look at the new patch set (#8). Change subject: mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driver ...................................................................... mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driver This mainboard has three Marvel PHYs connected to the internal SOC GbE controllers. The default LED status after HW reset of this PHYs shows a different mode than what is needed. LED[2] is not connected on this mainboard. This patch sets the following LED status: LED[0] - 7 = On - 1000 Mbps Link, Off - Else LED[1] - 1 = On - Link, Blink - Activity, Off - No Link LED[2] - not connected TEST=Try different register values to verify LED feature. Change-Id: I51d817bc720bf787279777f503efdc17dbb1274d Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 2 files changed, 56 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/69387/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/69387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51d817bc720bf787279777f503efdc17dbb1274d Gerrit-Change-Number: 69387 Gerrit-PatchSet: 8 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2022