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Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69432 )
Change subject: mainboard/google/geralt: Fix incorrect timestamps in the eventlog
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
please also rebase your local branch to latest coreboot tot
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Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters
......................................................................
Patch Set 22:
(1 comment)
File src/soc/amd/mendocino/root_complex.c:
https://review.coreboot.org/c/coreboot/+/68649/comment/9303d429_cd0c4172
PS16, Line 393: #else
> > I assume below behavior is your suggestion? […]
Update the code change after consulting AMD
1. Use #if (CONFIG(FEATURE_DYNAMIC_DPTC)) to include tables B through F.
2. Default Table A and no battery table use the Enhance DPTC_INPUT.
3. Support Enhance DPTC_INPUT structure directly, don't support old DPTC_INPUTS structure.
4. The update code change and design need to be verified by AMD and Google.
Hi AMD,
Since many default and low/now battery entries duplicated, do we need to expand the parameters for low/now battery in chip.h?
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Attention is currently required from: Tarun Tuli, Reka Norman, Shou-Chieh Hsu.
Hello Tarun Tuli, Reka Norman, Shou-Chieh Hsu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69430
to look at the new patch set (#2).
Change subject: mb/google/nissa/pujjo: Modify touch screen hid to ELAN901C
......................................................................
mb/google/nissa/pujjo: Modify touch screen hid to ELAN901C
Modify touch screen hid for Pujjo board.
BUG=b:258586760
TEST=Use the value to boot on Pujjo successfully.
Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com>
Change-Id: Ia3b374de8cba2125c478814a1890a4b6831715b9
---
M src/mainboard/google/brya/variants/pujjo/overridetree.cb
1 file changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/69430/2
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69386 )
Change subject: drivers/phy/m88e1512: Provide functionality to customize LED status
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163187):
https://review.coreboot.org/c/coreboot/+/69386/comment/85ac454b_de07398c
PS8, Line 14: https://web.archive.org/web/20221109080111/https://www.marvell.com/content/…
Possible unwrapped commit description (prefer a maximum 72 chars per line)
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Change subject: mb/siemens/mc_ehl2: Enable Marvell PHY interrupt
......................................................................
mb/siemens/mc_ehl2: Enable Marvell PHY interrupt
On this mainboard Marvell PHY INTn is routed to LED[2] pin.
Change-Id: I28a78afdcf0599bb998f906ce8056a0586e24f33
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
1 file changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/69434/1
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
index b61ea52..46eedbf 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
@@ -194,6 +194,8 @@
register "led_0_ctrl" = "7"
# LED[1]: On - Link, Blink - Activity, Off - No Link
register "led_1_ctrl" = "1"
+ # INTn is routed to LED[2] pin
+ register "enable_int" = "true"
device pnp 0.0 on end # PHY address
end
end
@@ -205,6 +207,8 @@
register "led_0_ctrl" = "7"
# LED[1]: On - Link, Blink - Activity, Off - No Link
register "led_1_ctrl" = "1"
+ # INTn is routed to LED[2] pin
+ register "enable_int" = "true"
device pnp 0.1 on end # PHY address
end
end
@@ -219,6 +223,8 @@
register "led_0_ctrl" = "7"
# LED[1]: On - Link, Blink - Activity, Off - No Link
register "led_1_ctrl" = "1"
+ # INTn is routed to LED[2] pin
+ register "enable_int" = "true"
device pnp 1.1 on end # PHY address
end
end
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