coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[S] Change in coreboot[master]: sb/intel/i82801dx/lpc.c: Use {read,write}_pmbase32
by Elyes Haouas (Code Review) 10 Nov '22

10 Nov '22

Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69441 ) Change subject: sb/intel/i82801dx/lpc.c: Use {read,write}_pmbase32 ...................................................................... Patch Set 1: (1 comment) File src/southbridge/intel/i82801dx/lpc.c: https://review.coreboot.org/c/coreboot/+/69441/comment/e6628125_12ffb705 PS1, Line 148: pmbase = pci_read_config16(dev, 0x40) & 0xfffe; Humm, southbridge/intel/common/pmbase.c uses : pci_read_config16(PCI_DEV(0, 0x1f, 0), PMBASE) & 0xfffc; -- To view, visit https://review.coreboot.org/c/coreboot/+/69441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36c7731f5201d4507b0b1ce792e5d907c07c70cd Gerrit-Change-Number: 69441 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 10 Nov 2022 09:20:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: Disable stylus GPIO pins based on fw_config
by 9elements QA (Code Review) 10 Nov '22

10 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69138 ) Change subject: mb/google/nissa/var/craask: Disable stylus GPIO pins based on fw_config ...................................................................... Patch Set 5: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135494 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135493 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/135492 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/135491 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/135490 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135489 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/135488 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/135487 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/135486 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/135485 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/135484 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/135483 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135482 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/135481 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/135480 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/135479 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e3a2583187c8a8e2616a5272b5a7a61debe982b Gerrit-Change-Number: 69138 Gerrit-PatchSet: 5 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Cathy Chen <cathy_chen(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 09:12:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mainboard/google/geralt: Fix incorrect timestamps in the eventlog
by Liju-Clr Chen (Code Review) 10 Nov '22

10 Nov '22

Liju-Clr Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69432 ) Change subject: mainboard/google/geralt: Fix incorrect timestamps in the eventlog ...................................................................... mainboard/google/geralt: Fix incorrect timestamps in the eventlog Timestamp '2000-00-00 00:00:00' is considered as the invalid format. Enable RTC to fix incorrect timestamp format in the eventlog. BUG=b:233720142 TEST=check the timestamp field in /var/log/eventlog.txt Change-Id: Iddad102dc8d60de01a691d330deb8247e99c616a Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com> --- M src/mainboard/google/geralt/Kconfig M src/soc/mediatek/mt8188/Makefile.inc 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/69432/1 diff --git a/src/mainboard/google/geralt/Kconfig b/src/mainboard/google/geralt/Kconfig index a911cb8..40a0f89 100644 --- a/src/mainboard/google/geralt/Kconfig +++ b/src/mainboard/google/geralt/Kconfig @@ -30,6 +30,7 @@ select TPM_GOOGLE_TI50 if VBOOT select MAINBOARD_HAS_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER + select RTC config MAINBOARD_DIR string diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc index 52fc861..13fea31 100644 --- a/src/soc/mediatek/mt8188/Makefile.inc +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -47,6 +47,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c ramstage-y += ../common/pmif_spi.c pmif_spi.c +ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c ramstage-y += soc.c ramstage-y += ../common/spm.c spm.c ramstage-y += ../common/sspm.c -- To view, visit https://review.coreboot.org/c/coreboot/+/69432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddad102dc8d60de01a691d330deb8247e99c616a Gerrit-Change-Number: 69432 Gerrit-PatchSet: 1 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: security/tpm: make tis_probe() return tpm_family
by Krystian Hebel (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Michał Żygowski, Christian Walter, Julius Werner, Sergii Dmytruk. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69159 ) Change subject: security/tpm: make tis_probe() return tpm_family ...................................................................... Patch Set 1: (1 comment) File src/drivers/i2c/tpm/tpm.c: https://review.coreboot.org/c/coreboot/+/69159/comment/c4b64421_dd2a5640 PS1, Line 461: *tpm_family = 1; > Are you sure this is guaranteed? I thought I recall that 9645 can be 2. […] TPM 2.0 for I2C does exist and it should be detected in the same way as for SPI/LPC. That being said, those tests aren't complete because they only test TIS version. Full check, regardless of bus, should be something like: ``` if (TPM_INTF_CAPABILITY.InterfaceVersion == 0) tpm_family = 1 // (TIS <= 1.21, not used by TPM 2.0 devices) else // (TIS 1.3, used both by TPM 1.2 and 2.0) if (TPM_STS.tpmFamily == 0) tpm_family = 1 else tpm_family = 2 ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/69159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5006e0cdfef76ff79ce9e1cf280fcd5515ae01b0 Gerrit-Change-Number: 69159 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 08:42:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/x86/mp_init.c: Keep track of initial lapic ID inside device_path
by Arthur Heymans (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Arthur Heymans, Angel Pons, Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64342 ) Change subject: cpu/x86/mp_init.c: Keep track of initial lapic ID inside device_path ...................................................................... Patch Set 12: (1 comment) Patchset: PS12: Hmm with CPUINFO_V2 we might be able to be bit smarter about things. I don't think FSP is trashing %gs so we can still use the thread local storage. Currently the cpu_info() is pushed on the stack but we might as well put it in an array. -- To view, visit https://review.coreboot.org/c/coreboot/+/64342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d9f8d23c0b0e5c142f6907593428d8509e4e7bb Gerrit-Change-Number: 64342 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 08:41:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/intel/haswell: Move chip_ops to cpu cluster
by Arthur Heymans (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Arthur Heymans, Raul Rangel, Tristan Corrick, Tim Wawrzynczak, Angel Pons, Alexander Couzens, Patrick Rudolph. Arthur Heymans has uploaded a new patch set (#12) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/59314 ) Change subject: cpu/intel/haswell: Move chip_ops to cpu cluster ...................................................................... cpu/intel/haswell: Move chip_ops to cpu cluster The cpu cluster is always present and it's the proper device to contain the settings that need to be applied to all cpus. This makes it possible to remove the fake lapic from devicetrees. Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/chip.h M src/cpu/intel/haswell/haswell_init.c M src/mainboard/asrock/b85m_pro4/devicetree.cb M src/mainboard/asrock/h81m-hds/devicetree.cb M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/google/slippy/devicetree.cb M src/mainboard/hp/folio_9480m/devicetree.cb M src/mainboard/intel/baskingridge/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb M src/mainboard/lenovo/haswell/variants/w541/devicetree.cb M src/mainboard/msi/h81m-p33/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/supermicro/x10slm-f/devicetree.cb M src/northbridge/intel/haswell/northbridge.c M src/soc/intel/broadwell/northbridge.c 21 files changed, 72 insertions(+), 138 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/59314/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/59314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786 Gerrit-Change-Number: 59314 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: sb/intel/common/spi: Fix building for 64bit
by Elyes Haouas (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Arthur Heymans. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69389 ) Change subject: sb/intel/common/spi: Fix building for 64bit ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File src/southbridge/intel/common/spi.c: https://review.coreboot.org/c/coreboot/+/69389/comment/601dcd15_3d5a148e PS3, Line 161: I'd remove this white space. -- To view, visit https://review.coreboot.org/c/coreboot/+/69389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bcb6dbf286438115c854d618eaa2da21c81400d Gerrit-Change-Number: 69389 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 10 Nov 2022 08:34:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to device...
by Arthur Heymans (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Felix Held. Hello build bot (Jenkins), Raul Rangel, Jonathon Hall, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69301 to look at the new patch set (#4). Change subject: soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetree ...................................................................... soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetree Change-Id: I77a333827552741453d8b575f2a8009b3e1bf8f1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/soc/intel/broadwell/northbridge.c 5 files changed, 20 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/69301/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77a333827552741453d8b575f2a8009b3e1bf8f1 Gerrit-Change-Number: 69301 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to device...
by Arthur Heymans (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69301 ) Change subject: soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetree ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/auron/variants/buddy/overridetree.cb: PS3: > hmm, why are the cpu ops needed here, but not the domain ops? same question for the next variant It's an override tree. Ops should not be needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/69301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77a333827552741453d8b575f2a8009b3e1bf8f1 Gerrit-Change-Number: 69301 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 10 Nov 2022 08:31:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: Modify DPTF related settings
by 9elements QA (Code Review) 10 Nov '22

10 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68523 ) Change subject: mb/google/nissa/var/craask: Modify DPTF related settings ...................................................................... Patch Set 8: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135478 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135477 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/135476 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/135475 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/135474 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135473 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/135472 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/135471 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/135470 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/135469 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/135468 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/135467 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135466 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/135465 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/135464 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/135463 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/68523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88c8c4e6798ec5bc2930dd713e8c8b2c543cfaf9 Gerrit-Change-Number: 68523 Gerrit-PatchSet: 8 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Cathy Chen <cathy_chen(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 08:29:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2022