coreboot-gerrit November 2022

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[M] Change in coreboot[master]: cpu/intel: Fix clearing MTRR for clang 64bit
by Arthur Heymans (Code Review) 10 Nov '22

10 Nov '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69388 to look at the new patch set (#3). Change subject: cpu/intel: Fix clearing MTRR for clang 64bit ...................................................................... cpu/intel: Fix clearing MTRR for clang 64bit Clang generates R_X86_64_32S symbols that get truncated. TESTED: - prodrive/hermes boots with GCC and clang - MTRR are properly cleared (tested by filling in both MTRR_FIX_64K_00000 and MTRR_FIX_4K_F8000 before clearing) Change-Id: I6a5139f7029b6f35b44377f105dded06f6d9cbf9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/soc/intel/common/block/cpu/car/cache_as_ram.S 4 files changed, 41 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/69388/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a5139f7029b6f35b44377f105dded06f6d9cbf9 Gerrit-Change-Number: 69388 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: arch/x86/memmove: Add 64bit version
by Arthur Heymans (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69231 to look at the new patch set (#9). Change subject: arch/x86/memmove: Add 64bit version ...................................................................... arch/x86/memmove: Add 64bit version The 64bit handles 64bit input variables properly. TESTED: Both qemu and real hardware can use LZ4 properly which use this code. Change-Id: Ib43ec19df97194d6b1c18bfacb5fe8211ba0ffe5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Makefile.inc R src/arch/x86/memmove_32.c A src/arch/x86/memmove_64.S 3 files changed, 226 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/69231/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/69231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib43ec19df97194d6b1c18bfacb5fe8211ba0ffe5 Gerrit-Change-Number: 69231 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: sb/intel/common/spi: Fix building for 64bit
by build bot (Jenkins) (Code Review) 10 Nov '22

10 Nov '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69389 ) Change subject: sb/intel/common/spi: Fix building for 64bit ...................................................................... Patch Set 2: Verified+1 (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163157): https://review.coreboot.org/c/coreboot/+/69389/comment/3c09982a_24b46133 PS2, Line 8: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bcb6dbf286438115c854d618eaa2da21c81400d Gerrit-Change-Number: 69389 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Nov 2022 07:35:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: amdfwtool: Set the base address of AMDFW as relative
by Bao Zheng (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Zheng Bao, Fred Reitberger, Felix Held. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/69429 to review the following change. Change subject: amdfwtool: Set the base address of AMDFW as relative ...................................................................... amdfwtool: Set the base address of AMDFW as relative Change-Id: If6fd5b21be90ac37618c484506db9b8a1e350ea2 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/amd/mandolin/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/morgana/Kconfig M src/soc/amd/morgana/Makefile.inc M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc M src/southbridge/amd/pi/hudson/Makefile.inc M util/amdfwtool/amdfwtool.c 13 files changed, 187 insertions(+), 173 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/69429/1 diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index bfb4cae..c949219 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -70,7 +70,7 @@ config AMD_FWM_POSITION_INDEX int - default 4 if BOARD_AMD_MANDOLIN + default 5 if BOARD_AMD_MANDOLIN default 4 if BOARD_AMD_CEREME help TODO: might need to be adapted for better placement of files in cbfs diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index b8209f8..20a2988 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -319,34 +319,29 @@ config AMD_FWM_POSITION_INDEX int "Firmware Directory Table location (0 to 5)" range 0 5 - default 0 if BOARD_ROMSIZE_KB_512 - default 1 if BOARD_ROMSIZE_KB_1024 - default 2 if BOARD_ROMSIZE_KB_2048 - default 3 if BOARD_ROMSIZE_KB_4096 - default 4 if BOARD_ROMSIZE_KB_8192 - default 5 if BOARD_ROMSIZE_KB_16384 + default 5 help - Typically this is calculated by the ROM size, but there may - be situations where you want to put the firmware directory - table in a different location. - 0: 512 KB - 0xFFFA0000 - 1: 1 MB - 0xFFF20000 - 2: 2 MB - 0xFFE20000 - 3: 4 MB - 0xFFC20000 - 4: 8 MB - 0xFF820000 - 5: 16 MB - 0xFF020000 + The PSP on-chip firmware scans the following offsets for the first + instance of the Embedded Firmware Structure in the 16M SPI address + window. + 0: 0xFA0000 + 1: 0xF20000 + 2: 0xE20000 + 3: 0xC20000 + 4: 0x820000 + 5: 0x20000 -comment "AMD Firmware Directory Table set to location for 512KB ROM" +comment "AMD Firmware Directory Table set to location 0xFA0000" depends on AMD_FWM_POSITION_INDEX = 0 -comment "AMD Firmware Directory Table set to location for 1MB ROM" +comment "AMD Firmware Directory Table set to location 0xF20000" depends on AMD_FWM_POSITION_INDEX = 1 -comment "AMD Firmware Directory Table set to location for 2MB ROM" +comment "AMD Firmware Directory Table set to location 0xE20000" depends on AMD_FWM_POSITION_INDEX = 2 -comment "AMD Firmware Directory Table set to location for 4MB ROM" +comment "AMD Firmware Directory Table set to location 0xC20000" depends on AMD_FWM_POSITION_INDEX = 3 -comment "AMD Firmware Directory Table set to location for 8MB ROM" +comment "AMD Firmware Directory Table set to location 0x820000" depends on AMD_FWM_POSITION_INDEX = 4 -comment "AMD Firmware Directory Table set to location for 16MB ROM" +comment "AMD Firmware Directory Table set to location 0x20000" depends on AMD_FWM_POSITION_INDEX = 5 config AMDFW_CONFIG_FILE diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 508ea1d..c191667 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -66,22 +66,29 @@ $(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) -CEZANNE_FWM_POSITION=$(call int-add, \ - $(call int-subtract, 0xffffffff \ +CEZANNE_FWM_POSITION_REL=$(call int-add, \ + $(call int-subtract, 0xffffff \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) +CEZANNE_FWM_POSITION_PHY=$(call int-add, \ + $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) \ + $(CEZANNE_FWM_POSITION_REL) 1) # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes # Building the cbfs image will fail if the offset isn't large enough AMD_FW_AB_POSITION := 0x40 -CEZANNE_FW_A_POSITION=$(call int-add, \ +CEZANNE_FW_A_POSITION=$(call int-subtract, \ + $(call int-add, \ $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(AMD_FW_AB_POSITION)) \ + $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) -CEZANNE_FW_B_POSITION=$(call int-add, \ +CEZANNE_FW_B_POSITION=$(call int-subtract, \ + $(call int-add, \ $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(AMD_FW_AB_POSITION)) \ + $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) # # PSP Directory Table items # @@ -239,7 +246,7 @@ $(OPT_APOB_NV_BASE) \ $(OPT_VERSTAGE_FILE) \ $(OPT_VERSTAGE_SIG_FILE) \ - --location $(shell printf "%#x" $(CEZANNE_FWM_POSITION)) \ + --location $(shell printf "%#x" $(CEZANNE_FWM_POSITION_REL)) \ --multilevel \ --output $@ @@ -276,7 +283,7 @@ cbfs-files-y += apu/amdfw apu/amdfw-file := $(obj)/amdfw.rom -apu/amdfw-position := $(CEZANNE_FWM_POSITION) +apu/amdfw-position := $(CEZANNE_FWM_POSITION_PHY) apu/amdfw-type := raw ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index d31b29dd..ed8d5bb 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -327,34 +327,29 @@ config AMD_FWM_POSITION_INDEX int "Firmware Directory Table location (0 to 5)" range 0 5 - default 0 if BOARD_ROMSIZE_KB_512 - default 1 if BOARD_ROMSIZE_KB_1024 - default 2 if BOARD_ROMSIZE_KB_2048 - default 3 if BOARD_ROMSIZE_KB_4096 - default 4 if BOARD_ROMSIZE_KB_8192 - default 5 if BOARD_ROMSIZE_KB_16384 + default 5 help - Typically this is calculated by the ROM size, but there may - be situations where you want to put the firmware directory - table in a different location. - 0: 512 KB - 0xFFFA0000 - 1: 1 MB - 0xFFF20000 - 2: 2 MB - 0xFFE20000 - 3: 4 MB - 0xFFC20000 - 4: 8 MB - 0xFF820000 - 5: 16 MB - 0xFF020000 + The PSP on-chip firmware scans the following offsets for the first + instance of the Embedded Firmware Structure in the 16M SPI address + window. + 0: 0xFA0000 + 1: 0xF20000 + 2: 0xE20000 + 3: 0xC20000 + 4: 0x820000 + 5: 0x20000 -comment "AMD Firmware Directory Table set to location for 512KB ROM" +comment "AMD Firmware Directory Table set to location 0xFA0000" depends on AMD_FWM_POSITION_INDEX = 0 -comment "AMD Firmware Directory Table set to location for 1MB ROM" +comment "AMD Firmware Directory Table set to location 0xF20000" depends on AMD_FWM_POSITION_INDEX = 1 -comment "AMD Firmware Directory Table set to location for 2MB ROM" +comment "AMD Firmware Directory Table set to location 0xE20000" depends on AMD_FWM_POSITION_INDEX = 2 -comment "AMD Firmware Directory Table set to location for 4MB ROM" +comment "AMD Firmware Directory Table set to location 0xC20000" depends on AMD_FWM_POSITION_INDEX = 3 -comment "AMD Firmware Directory Table set to location for 8MB ROM" +comment "AMD Firmware Directory Table set to location 0x820000" depends on AMD_FWM_POSITION_INDEX = 4 -comment "AMD Firmware Directory Table set to location for 16MB ROM" +comment "AMD Firmware Directory Table set to location 0x20000" depends on AMD_FWM_POSITION_INDEX = 5 config AMDFW_CONFIG_FILE diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index 8f3425d..c0a3409 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -68,22 +68,30 @@ $(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) -MENDOCINO_FWM_POSITION=$(call int-add, \ - $(call int-subtract, 0xffffffff \ +MENDOCINO_FWM_POSITION_REL=$(call int-add, \ + $(call int-subtract, 0xffffff \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) +MENDOCINO_FWM_POSITION_PHY=$(call int-add, \ + $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) \ + $(MENDOCINO_FWM_POSITION_REL) 1) + # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes # Building the cbfs image will fail if the offset isn't large enough AMD_FW_AB_POSITION := 0x40 -MENDOCINO_FW_A_POSITION=$(call int-add, \ +MENDOCINO_FW_A_POSITION=$(call int-subtract, \ + $(call int-add, \ $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(AMD_FW_AB_POSITION)) \ + $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) -MENDOCINO_FW_B_POSITION=$(call int-add, \ +MENDOCINO_FW_B_POSITION=$(call int-subtract, \ + $(call int-add, \ $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(AMD_FW_AB_POSITION)) \ + $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) # # PSP Directory Table items # @@ -258,7 +266,7 @@ $(OPT_VERSTAGE_FILE) \ $(OPT_VERSTAGE_SIG_FILE) \ $(OPT_SPL_TABLE_FILE) \ - --location $(shell printf "%#x" $(MENDOCINO_FWM_POSITION)) \ + --location $(shell printf "%#x" $(MENDOCINO_FWM_POSITION_REL)) \ --output $@ $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) @@ -298,7 +306,7 @@ cbfs-files-y += apu/amdfw apu/amdfw-file := $(obj)/amdfw.rom -apu/amdfw-position := $(MENDOCINO_FWM_POSITION) +apu/amdfw-position := $(MENDOCINO_FWM_POSITION_PHY) apu/amdfw-type := raw ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) diff --git a/src/soc/amd/morgana/Kconfig b/src/soc/amd/morgana/Kconfig index a1261c9..f031157 100644 --- a/src/soc/amd/morgana/Kconfig +++ b/src/soc/amd/morgana/Kconfig @@ -316,34 +316,29 @@ config AMD_FWM_POSITION_INDEX int "Firmware Directory Table location (0 to 5)" range 0 5 - default 0 if BOARD_ROMSIZE_KB_512 - default 1 if BOARD_ROMSIZE_KB_1024 - default 2 if BOARD_ROMSIZE_KB_2048 - default 3 if BOARD_ROMSIZE_KB_4096 - default 4 if BOARD_ROMSIZE_KB_8192 - default 5 if BOARD_ROMSIZE_KB_16384 + default 5 help - Typically this is calculated by the ROM size, but there may - be situations where you want to put the firmware directory - table in a different location. - 0: 512 KB - 0xFFFA0000 - 1: 1 MB - 0xFFF20000 - 2: 2 MB - 0xFFE20000 - 3: 4 MB - 0xFFC20000 - 4: 8 MB - 0xFF820000 - 5: 16 MB - 0xFF020000 + The PSP on-chip firmware scans the following offsets for the first + instance of the Embedded Firmware Structure in the 16M SPI address + window. + 0: 0xFA0000 + 1: 0xF20000 + 2: 0xE20000 + 3: 0xC20000 + 4: 0x820000 + 5: 0x20000 -comment "AMD Firmware Directory Table set to location for 512KB ROM" +comment "AMD Firmware Directory Table set to location 0xFA0000" depends on AMD_FWM_POSITION_INDEX = 0 -comment "AMD Firmware Directory Table set to location for 1MB ROM" +comment "AMD Firmware Directory Table set to location 0xF20000" depends on AMD_FWM_POSITION_INDEX = 1 -comment "AMD Firmware Directory Table set to location for 2MB ROM" +comment "AMD Firmware Directory Table set to location 0xE20000" depends on AMD_FWM_POSITION_INDEX = 2 -comment "AMD Firmware Directory Table set to location for 4MB ROM" +comment "AMD Firmware Directory Table set to location 0xC20000" depends on AMD_FWM_POSITION_INDEX = 3 -comment "AMD Firmware Directory Table set to location for 8MB ROM" +comment "AMD Firmware Directory Table set to location 0x820000" depends on AMD_FWM_POSITION_INDEX = 4 -comment "AMD Firmware Directory Table set to location for 16MB ROM" +comment "AMD Firmware Directory Table set to location 0x20000" depends on AMD_FWM_POSITION_INDEX = 5 config AMDFW_CONFIG_FILE diff --git a/src/soc/amd/morgana/Makefile.inc b/src/soc/amd/morgana/Makefile.inc index f4243bc..f82765b 100644 --- a/src/soc/amd/morgana/Makefile.inc +++ b/src/soc/amd/morgana/Makefile.inc @@ -70,22 +70,40 @@ $(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) -MORGANA_FWM_POSITION=$(call int-add, \ - $(call int-subtract, 0xffffffff \ +MORGANA_FWM_POSITION1=$(call int-add, \ + $(call int-subtract, 0x1000000 \ + $(call int-shift-left, \ + 1 $(call int-subtract, 24 3))) 0x20000) + +MORGANA_FWM_POSITION2=$(call int-add, \ + $(call int-subtract, 0xffffff \ + $(call int-shift-left, \ + 0x80000 3)) 0x20000 1) + +MORGANA_FWM_POSITION_REL=$(call int-add, \ + $(call int-subtract, 0xffffff \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) +MORGANA_FWM_POSITION_PHY=$(call int-add, \ + $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) \ + $(MORGANA_FWM_POSITION_REL) 1) # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes # Building the cbfs image will fail if the offset isn't large enough AMD_FW_AB_POSITION := 0x40 -MORGANA_FW_A_POSITION=$(call int-add, \ +MORGANA_FW_A_POSITION=$(call int-subtract, \ + $(call int-add, \ $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(AMD_FW_AB_POSITION)) \ + $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) -MORGANA_FW_B_POSITION=$(call int-add, \ +MORGANA_FW_B_POSITION=$(call int-subtract, \ + $(call int-add, \ $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(AMD_FW_AB_POSITION)) \ + $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) + # # PSP Directory Table items # @@ -260,7 +278,7 @@ $(OPT_VERSTAGE_FILE) \ $(OPT_VERSTAGE_SIG_FILE) \ $(OPT_SPL_TABLE_FILE) \ - --location $(shell printf "%#x" $(MORGANA_FWM_POSITION)) \ + --location $(shell printf "%#x" $(MORGANA_FWM_POSITION_REL)) \ --output $@ $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index b24102c..69e4895 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -364,34 +364,29 @@ config AMD_FWM_POSITION_INDEX int "Firmware Directory Table location (0 to 5)" range 0 5 - default 0 if BOARD_ROMSIZE_KB_512 - default 1 if BOARD_ROMSIZE_KB_1024 - default 2 if BOARD_ROMSIZE_KB_2048 - default 3 if BOARD_ROMSIZE_KB_4096 - default 4 if BOARD_ROMSIZE_KB_8192 - default 5 if BOARD_ROMSIZE_KB_16384 + default 5 help - Typically this is calculated by the ROM size, but there may - be situations where you want to put the firmware directory - table in a different location. - 0: 512 KB - 0xFFFA0000 - 1: 1 MB - 0xFFF20000 - 2: 2 MB - 0xFFE20000 - 3: 4 MB - 0xFFC20000 - 4: 8 MB - 0xFF820000 - 5: 16 MB - 0xFF020000 + The PSP on-chip firmware scans the following offsets for the first + instance of the Embedded Firmware Structure in the 16M SPI address + window. + 0: 0xFA0000 + 1: 0xF20000 + 2: 0xE20000 + 3: 0xC20000 + 4: 0x820000 + 5: 0x20000 -comment "AMD Firmware Directory Table set to location for 512KB ROM" +comment "AMD Firmware Directory Table set to location 0xFA0000" depends on AMD_FWM_POSITION_INDEX = 0 -comment "AMD Firmware Directory Table set to location for 1MB ROM" +comment "AMD Firmware Directory Table set to location 0xF20000" depends on AMD_FWM_POSITION_INDEX = 1 -comment "AMD Firmware Directory Table set to location for 2MB ROM" +comment "AMD Firmware Directory Table set to location 0xE20000" depends on AMD_FWM_POSITION_INDEX = 2 -comment "AMD Firmware Directory Table set to location for 4MB ROM" +comment "AMD Firmware Directory Table set to location 0xC20000" depends on AMD_FWM_POSITION_INDEX = 3 -comment "AMD Firmware Directory Table set to location for 8MB ROM" +comment "AMD Firmware Directory Table set to location 0x820000" depends on AMD_FWM_POSITION_INDEX = 4 -comment "AMD Firmware Directory Table set to location for 16MB ROM" +comment "AMD Firmware Directory Table set to location 0x20000" depends on AMD_FWM_POSITION_INDEX = 5 config AMDFW_OUTSIDE_CBFS diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 258323e..2da2753 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -71,22 +71,29 @@ $(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\ $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size)) -PICASSO_FWM_POSITION=$(call int-add, \ - $(call int-subtract, 0xffffffff \ +PICASSO_FWM_POSITION_REL=$(call int-add, \ + $(call int-subtract, 0xffffff \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) +PICASSO_FWM_POSITION_PHY=$(call int-add, \ + $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) \ + $(PICASSO_FWM_POSITION_REL) 1) # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes # Building the cbfs image will fail if the offset isn't large enough AMD_FW_AB_POSITION := 0x40 -PICASSO_FW_A_POSITION=$(call int-add, \ +PICASSO_FW_A_POSITION=$(call int-subtract, \ + $(call int-add, \ $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(AMD_FW_AB_POSITION)) \ + $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) -PICASSO_FW_B_POSITION=$(call int-add, \ +PICASSO_FW_B_POSITION=$(call int-subtract, \ + $(call int-add, \ $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(AMD_FW_AB_POSITION)) \ + $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) # # PSP Directory Table items @@ -255,7 +262,7 @@ $(OPT_APOB0_NV_BASE) \ $(OPT_VERSTAGE_FILE) \ $(OPT_VERSTAGE_SIG_FILE) \ - --location $(shell printf "%#x" $(PICASSO_FWM_POSITION)) \ + --location $(shell printf "%#x" $(PICASSO_FWM_POSITION_REL)) \ --output $@ $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) @@ -289,11 +296,12 @@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) $(call add_intermediate, add_amdfw, $(obj)/amdfw.rom) printf " DD Adding AMD Firmware\n" + printf "%x\n" $(PICASSO_FWM_POSITION_REL) $(CBFSTOOL) $(obj)/coreboot.pre write -r AMDFW -f $(obj)/amdfw.rom --fill-upward else cbfs-files-y += apu/amdfw apu/amdfw-file := $(obj)/amdfw.rom -apu/amdfw-position := $(PICASSO_FWM_POSITION) +apu/amdfw-position := $(PICASSO_FWM_POSITION_PHY) apu/amdfw-type := raw endif diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 53b986e..dd211d0 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -328,34 +328,29 @@ config AMD_FWM_POSITION_INDEX int "Firmware Directory Table location (0 to 5)" range 0 5 - default 0 if BOARD_ROMSIZE_KB_512 - default 1 if BOARD_ROMSIZE_KB_1024 - default 2 if BOARD_ROMSIZE_KB_2048 - default 3 if BOARD_ROMSIZE_KB_4096 - default 4 if BOARD_ROMSIZE_KB_8192 - default 5 if BOARD_ROMSIZE_KB_16384 + default 5 help - Typically this is calculated by the ROM size, but there may - be situations where you want to put the firmware directory - table in a different location. - 0: 512 KB - 0xFFFA0000 - 1: 1 MB - 0xFFF20000 - 2: 2 MB - 0xFFE20000 - 3: 4 MB - 0xFFC20000 - 4: 8 MB - 0xFF820000 - 5: 16 MB - 0xFF020000 + The PSP on-chip firmware scans the following offsets for the first + instance of the Embedded Firmware Structure in the 16M SPI address + window. + 0: 0xFA0000 + 1: 0xF20000 + 2: 0xE20000 + 3: 0xC20000 + 4: 0x820000 + 5: 0x20000 -comment "AMD Firmware Directory Table set to location for 512KB ROM" +comment "AMD Firmware Directory Table set to location 0xFA0000" depends on AMD_FWM_POSITION_INDEX = 0 -comment "AMD Firmware Directory Table set to location for 1MB ROM" +comment "AMD Firmware Directory Table set to location 0xF20000" depends on AMD_FWM_POSITION_INDEX = 1 -comment "AMD Firmware Directory Table set to location for 2MB ROM" +comment "AMD Firmware Directory Table set to location 0xE20000" depends on AMD_FWM_POSITION_INDEX = 2 -comment "AMD Firmware Directory Table set to location for 4MB ROM" +comment "AMD Firmware Directory Table set to location 0xC20000" depends on AMD_FWM_POSITION_INDEX = 3 -comment "AMD Firmware Directory Table set to location for 8MB ROM" +comment "AMD Firmware Directory Table set to location 0x820000" depends on AMD_FWM_POSITION_INDEX = 4 -comment "AMD Firmware Directory Table set to location for 16MB ROM" +comment "AMD Firmware Directory Table set to location 0x20000" depends on AMD_FWM_POSITION_INDEX = 5 config DIMM_SPD_SIZE diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 078a566..3f0b774 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -80,10 +80,13 @@ # +-----------+ # # EC ROM should be 64K aligned. -STONEYRIDGE_FWM_POSITION=$(call int-add, \ - $(call int-subtract, 0xffffffff \ +STONEYRIDGE_FWM_POSITION_REL=$(call int-add, \ + $(call int-subtract, 0xffffff \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) +STONEYRIDGE_FWM_POSITION_PHY=$(call int-add, \ + $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) \ + $(STONEYRIDGE_FWM_POSITION_REL) 1) ### 0 @@ -152,29 +155,24 @@ --config $(CONFIG_AMDFW_CONFIG_FILE) \ $(OPT_SOCNAME) \ --flashsize $(CONFIG_ROM_SIZE) \ - --location $(shell printf "0x%x" $(STONEYRIDGE_FWM_POSITION)) \ + --location $(shell printf "0x%x" $(STONEYRIDGE_FWM_POSITION_REL)) \ --output $@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) # Calculate firmware position inside the ROM -STONEYRIDGE_FWM_ROM_POSITION=$(call int-add, \ - $(call int-subtract, $(CONFIG_ROM_SIZE) \ - $(call int-shift-left, \ - 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000) - $(call add_intermediate, add_amdfw, $(obj)/amdfw.rom) printf " DD Adding AMD Firmware at ROM offset 0x%x\n" \ - "$(STONEYRIDGE_FWM_ROM_POSITION)" + "$(STONEYRIDGE_FWM_POSITION_REL)" dd if=$(obj)/amdfw.rom \ of=$< conv=notrunc bs=1 \ - seek=$(STONEYRIDGE_FWM_ROM_POSITION) >/dev/null 2>&1 + seek=$(STONEYRIDGE_FWM_POSITION_REL) >/dev/null 2>&1 else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) cbfs-files-y += apu/amdfw apu/amdfw-file := $(obj)/amdfw.rom -apu/amdfw-position := $(STONEYRIDGE_FWM_POSITION) +apu/amdfw-position := $(STONEYRIDGE_FWM_POSITION_PHY) apu/amdfw-type := raw endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index d3d9322..6c8d057 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -66,11 +66,8 @@ # # EC ROM should be 64K aligned. -ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) -else -HUDSON_FWM_POSITION=0xfff20000 -endif +HUDSON_FWM_POSITION_REL=$(call _toint,0x20000) +HUDSON_FWM_POSITION_PHY=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) $(HUDSON_FWM_POSITION_REL) 1) ifeq ($(CONFIG_HUDSON_PSP), y) @@ -144,7 +141,7 @@ $(OPT_2SMUFIRMWARE2_FN_FILE) \ $(OPT_2SMUSCS_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ - --location $(HUDSON_FWM_POSITION) \ + --location $(HUDSON_FWM_POSITION_REL) \ --config $(CONFIG_AMDFW_CONFIG_FILE) \ --output $@ @@ -152,13 +149,13 @@ $(call add_intermediate, add_amdfw, $(obj)/amdfw.rom) printf " DD Adding AMD Firmware\n" dd if=$(obj)/amdfw.rom \ - of=$< conv=notrunc bs=1 seek=131072 >/dev/null 2>&1 + of=$< conv=notrunc bs=1 seek=$(HUDSON_FWM_POSITION_REL) >/dev/null 2>&1 else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) cbfs-files-y += apu/amdfw apu/amdfw-file := $(obj)/amdfw.rom -apu/amdfw-position := $(HUDSON_FWM_POSITION) +apu/amdfw-position := $(HUDSON_FWM_POSITION_PHY) apu/amdfw-type := raw endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 389be9f..02de86e 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1990,7 +1990,6 @@ uint32_t dir_location = 0; bool any_location = 0; uint32_t romsig_offset; - uint32_t rom_base_address; uint8_t soc_id = PLATFORM_UNKNOWN; uint8_t efs_spi_readmode = 0xff; uint8_t efs_spi_speed = 0xff; @@ -2284,12 +2283,6 @@ printf(" AMDFWTOOL Using ROM size of %dKB\n", ctx.rom_size / 1024); - rom_base_address = 0xFFFFFFFF - ctx.rom_size + 1; - if (dir_location && (dir_location < rom_base_address)) { - fprintf(stderr, "Error: Directory location outside of ROM.\n\n"); - return 1; - } - if (any_location) { if (dir_location & 0x3f) { fprintf(stderr, "Error: Invalid Directory location.\n"); @@ -2298,18 +2291,18 @@ } } else { switch (dir_location) { - case 0: /* Fall through */ - case 0xFFFA0000: /* Fall through */ - case 0xFFF20000: /* Fall through */ - case 0xFFE20000: /* Fall through */ - case 0xFFC20000: /* Fall through */ - case 0xFF820000: /* Fall through */ - case 0xFF020000: /* Fall through */ + case 0: /* Fall through */ + case 0xFA0000: /* Fall through */ + case 0xF20000: /* Fall through */ + case 0xE20000: /* Fall through */ + case 0xC20000: /* Fall through */ + case 0x820000: /* Fall through */ + case 0x020000: /* Fall through */ break; default: fprintf(stderr, "Error: Invalid Directory location.\n"); - fprintf(stderr, " Valid locations are 0xFFFA0000, 0xFFF20000,\n"); - fprintf(stderr, " 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n"); + fprintf(stderr, " Valid locations are 0xFA0000, 0xF20000,\n"); + fprintf(stderr, " 0xE20000, 0xC20000, 0x820000, 0x020000\n"); return 1; } } @@ -2321,7 +2314,7 @@ memset(ctx.rom, 0xFF, ctx.rom_size); if (dir_location) - romsig_offset = ctx.current = dir_location - rom_base_address; + romsig_offset = ctx.current = dir_location; else romsig_offset = ctx.current = AMD_ROMSIG_OFFSET; -- To view, visit https://review.coreboot.org/c/coreboot/+/69429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6fd5b21be90ac37618c484506db9b8a1e350ea2 Gerrit-Change-Number: 69429 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: soc/amd/picasso: Move AMD firmware from 0x420000 to 0x20000
by Bao Zheng (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/69428 to review the following change. Change subject: soc/amd/picasso: Move AMD firmware from 0x420000 to 0x20000 ...................................................................... soc/amd/picasso: Move AMD firmware from 0x420000 to 0x20000 The address 0x42000 is not an offically accepted address even though it works well so far. Add a region in flash map where amdfw.rom can be put, instead of the CBFS which needs an extra 0x40 bytes space at the head. Change-Id: I62e22dd5eeb5b85497efcf1e753415c0a6fdf2ca Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/amd/mandolin/variants/mandolin/board.fmd M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 4 files changed, 34 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/69428/1 diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 50b3e5d..bfb4cae 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -11,6 +11,7 @@ select AZALIA_PLUGIN_SUPPORT select HAVE_ACPI_RESUME select DRIVERS_UART_ACPI + select AMDFW_OUTSIDE_CBFS if BOARD_AMD_MANDOLIN select AMD_SOC_CONSOLE_UART if !AMD_LPC_DEBUG_CARD config FMDFILE @@ -46,7 +47,7 @@ default 0x164e if SMSC_SIO1036_BASE_164E config CBFS_SIZE - default 0x7cf000 if BOARD_AMD_MANDOLIN # Maximum size for the Mandolin FMAP + default 0x400000 if BOARD_AMD_MANDOLIN # Maximum size for the Mandolin FMAP default 0xfcf000 if BOARD_AMD_CEREME # Maximum size for the Cereme FMAP config MAINBOARD_DIR @@ -69,7 +70,7 @@ config AMD_FWM_POSITION_INDEX int - default 3 if BOARD_AMD_MANDOLIN + default 4 if BOARD_AMD_MANDOLIN default 4 if BOARD_AMD_CEREME help TODO: might need to be adapted for better placement of files in cbfs diff --git a/src/mainboard/amd/mandolin/variants/mandolin/board.fmd b/src/mainboard/amd/mandolin/variants/mandolin/board.fmd index 33b281d..c3dc77f 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/board.fmd +++ b/src/mainboard/amd/mandolin/variants/mandolin/board.fmd @@ -1,8 +1,9 @@ FLASH@0xFF800000 8M { BIOS { EC 128K + AMDFW 2M RW_MRC_CACHE 64K FMAP 4K - COREBOOT(CBFS) + COREBOOT(CBFS) @4M } } diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index f3b982d..b24102c 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -394,6 +394,13 @@ comment "AMD Firmware Directory Table set to location for 16MB ROM" depends on AMD_FWM_POSITION_INDEX = 5 +config AMDFW_OUTSIDE_CBFS + def_bool n + help + The AMDFW (PSP) is typically locatable in cbfs. Select this + option to manually attach the generated amdfw.rom at an + offset of 0x20000 from the bottom of the coreboot ROM image. + config AMDFW_CONFIG_FILE string default "src/soc/amd/picasso/fw.cfg" diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index cff47af..258323e 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -286,10 +286,16 @@ --anywhere \ --output $@ +ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) +$(call add_intermediate, add_amdfw, $(obj)/amdfw.rom) + printf " DD Adding AMD Firmware\n" + $(CBFSTOOL) $(obj)/coreboot.pre write -r AMDFW -f $(obj)/amdfw.rom --fill-upward +else cbfs-files-y += apu/amdfw apu/amdfw-file := $(obj)/amdfw.rom apu/amdfw-position := $(PICASSO_FWM_POSITION) apu/amdfw-type := raw +endif ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_a -- To view, visit https://review.coreboot.org/c/coreboot/+/69428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62e22dd5eeb5b85497efcf1e753415c0a6fdf2ca Gerrit-Change-Number: 69428 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: soc/amd/morgana: Add 32M support
by Bao Zheng (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69150 to look at the new patch set (#3). Change subject: soc/amd/morgana: Add 32M support ...................................................................... soc/amd/morgana: Add 32M support The 32M has to be divided into 2 16M parts, top and bottom. We can only map one part at one time. By default, the bottom 16M is mapped to 0xFF000000-0xFFFFFFFF. By this default setting, the address in the image is not the actual phyical address. So we need to convert the address, or map the upper 16M instead (the easier way UEFI BIOS does). So we push all the modules with running code, like romstage, ramstage, even the fmap table, to upper 16M. For the bootblock part, which is loaded by bootloader, it is unchanged as a tiny relocatable image in bottom 16M in amdfw.rom. Since the amdfw.rom is not in CFBS, we put it in fmap. We put only EC FWs and PSP FWs in the botttom, where the PSP can load. If coreboot need to access bottom 16M, which in fact doesn't seem to be necessary, can be implemented by SMN command. The bit 14 of soft fuse decides which (top or bottom) 16M is mapped to 4G-16M. BUG=b:255374782 Change-Id: Ia0b5a75f828033b29c378bed9a939b23d7f19140 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/amd/birman/Kconfig M src/mainboard/amd/birman/board.fmd M src/mainboard/amd/birman/chromeos.fmd M src/soc/amd/morgana/Makefile.inc 4 files changed, 48 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/69150/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0b5a75f828033b29c378bed9a939b23d7f19140 Gerrit-Change-Number: 69150 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: arch/x86/memmove: Add 64bit version
by build bot (Jenkins) (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Arthur Heymans. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69231 ) Change subject: arch/x86/memmove: Add 64bit version ...................................................................... Patch Set 8: Verified+1 (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163153): https://review.coreboot.org/c/coreboot/+/69231/comment/5b6a19ed_7f94543b PS8, Line 10: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib43ec19df97194d6b1c18bfacb5fe8211ba0ffe5 Gerrit-Change-Number: 69231 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 10 Nov 2022 07:33:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: configs: Add 64bit buildtest for prodrive/hermes
by Arthur Heymans (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69236 ) Change subject: configs: Add 64bit buildtest for prodrive/hermes ...................................................................... Patch Set 10: (1 comment) File configs/config.prodrive_hermes_x86_64: PS1: > File might need to be named `config.prodrive_hermes. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic62a33f8d8c3fdaa8182e797b2bf6fbed6b55731 Gerrit-Change-Number: 69236 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 07:33:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Fix set but unused variable
by Arthur Heymans (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Tarun Tuli, Martin L Roth, Subrata Banik, Kapil Porwal, Angel Pons, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66264 ) Change subject: soc/intel/meteorlake: Fix set but unused variable ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/meteorlake/systemagent.c: https://review.coreboot.org/c/coreboot/+/66264/comment/e48c12ce_d8769bed PS5, Line 87: (void)soc_config; > Nit: Add a comment? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/66264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe1de3057c17b4aa8ecbd87fac598e43294584e3 Gerrit-Change-Number: 66264 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 10 Nov 2022 07:32:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Fix set but unused variable
by Arthur Heymans (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Tarun Tuli, Martin L Roth, Subrata Banik, Kapil Porwal, Angel Pons, Felix Held. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/66264 to look at the new patch set (#6). Change subject: soc/intel/meteorlake: Fix set but unused variable ...................................................................... soc/intel/meteorlake: Fix set but unused variable Clang complains about this. Change-Id: Ibe1de3057c17b4aa8ecbd87fac598e43294584e3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/meteorlake/systemagent.c 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/66264/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/66264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe1de3057c17b4aa8ecbd87fac598e43294584e3 Gerrit-Change-Number: 66264 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2022