coreboot-gerrit November 2022

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: Generate SPD ID for supported memory parts
by Felix Held (Code Review) 10 Nov '22

10 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69311 ) Change subject: mb/google/brya/var/marasov: Generate SPD ID for supported memory parts ...................................................................... mb/google/brya/var/marasov: Generate SPD ID for supported memory parts Add supported memory parts in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 1 (0001) MT62F1G32D4DR-031 WT:B 4 (0100) H9JCNNNCP3MLYR-N6E 5 (0101) BUG=b:254365935 BRANCH=None TEST=run part_id_gen to generate SPD id Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: Ifa0637b47d0017cdb9e26ed32328f4405c0df3f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69311 Reviewed-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/marasov/memory/Makefile.inc M src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt 3 files changed, 47 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Frank Chu: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/marasov/memory/Makefile.inc b/src/mainboard/google/brya/variants/marasov/memory/Makefile.inc index eace2e4..444b95d 100644 --- a/src/mainboard/google/brya/variants/marasov/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/marasov/memory/Makefile.inc @@ -1,5 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/marasov/memory/ src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 4(0b0100) Parts = MT62F1G32D4DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 5(0b0101) Parts = H9JCNNNCP3MLYR-N6E diff --git a/src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt index fa24790..f752d5f 100644 --- a/src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt @@ -1 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/marasov/memory/ src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt + DRAM Part Name ID to assign +MT62F512M32D2DR-031 WT:B 0 (0000) +H9JCNNNBK3MLYR-N6E 1 (0001) +MT62F1G32D4DR-031 WT:B 4 (0100) +H9JCNNNCP3MLYR-N6E 5 (0101) diff --git a/src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt index 9621137..0d9e2a7 100644 --- a/src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt @@ -9,3 +9,7 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +MT62F512M32D2DR-031 WT:B +H9JCNNNBK3MLYR-N6E +MT62F1G32D4DR-031 WT:B +H9JCNNNCP3MLYR-N6E -- To view, visit https://review.coreboot.org/c/coreboot/+/69311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa0637b47d0017cdb9e26ed32328f4405c0df3f7 Gerrit-Change-Number: 69311 Gerrit-PatchSet: 6 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: mb/google/brya/var/marasov: Update devicetree setting for marasov
by Felix Held (Code Review) 10 Nov '22

10 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69364 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brya/var/marasov: Update devicetree setting for marasov ...................................................................... mb/google/brya/var/marasov: Update devicetree setting for marasov update devicetree setting per the schematic BUG=b:254365935 BRANCH=None TEST=Built successfully Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: Ifa4cb18b8e1a7b162f505ff12612ef808fb7061a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69364 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/marasov/overridetree.cb 1 file changed, 262 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Frank Chu: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index 4f2c04a..3f9dcfa 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -1,6 +1,246 @@ +fw_config + field KB_BL 7 7 + option KB_BL_ABSENT 0 + option KB_BL_PRESENT 1 + end + field AUDIO 8 10 + option AUDIO_UNKNOWN 0 + option ALC1019_ALC5682I_VD_I2S 1 + option ALC1019_ALC5682I_VS_I2S 2 + end + field THERMAL 18 18 + option THERMAL_6W 0 + option THERMAL_15W 1 + end + field STORAGE 30 31 + option STORAGE_NVME 0 + option STORAGE_UFS 1 + end +end + chip soc/intel/alderlake - device domain 0 on - end + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C3 | TouchScreen | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + register "sagv" = "SaGv_Enabled" + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + }" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_Port 1 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C2 + register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # Type-A Port A1 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 6 + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # DCI port + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # DCI port + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Disable USB3 Port 2 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1 + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC1)" + + device domain 0 on + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO AUDIO_UNKNOWN + probe AUDIO ALC1019_ALC5682I_VD_I2S + end + end + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO ALC1019_ALC5682I_VS_I2S + end + end + chip drivers/generic/alc1015 + register "hid" = ""RTL1019"" + register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + device generic 1 on end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end #I2C1 + device ref pcie_rp11 on + # Enable NVMe SSD PCIe 11-12 using clk 1 + register "pch_pcie_rp[PCH_RP(11)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + probe STORAGE STORAGE_NVME + end + device ref ish on + probe STORAGE STORAGE_UFS + end + device ref ufs on + probe STORAGE STORAGE_UFS + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)" + register "enable_delay_ms" = "3" + device spi 0 on end + end # FPMCU + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 2 alias conn2 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 2))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 2))" + device ref usb3_port4 on end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/69364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa4cb18b8e1a7b162f505ff12612ef808fb7061a Gerrit-Change-Number: 69364 Gerrit-PatchSet: 6 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driver
by Arthur Heymans (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Mario Scheithauer, Werner Zeh. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69387 ) Change subject: mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driver ...................................................................... Patch Set 9: (1 comment) File src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb: https://review.coreboot.org/c/coreboot/+/69387/comment/2a19909c_bf382db5 PS9, Line 197: device pnp 0.0 on end # PHY address PNP is for LPC/ISA devices. Is it meaningful here? There exists a 'generic' device. -- To view, visit https://review.coreboot.org/c/coreboot/+/69387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51d817bc720bf787279777f503efdc17dbb1274d Gerrit-Change-Number: 69387 Gerrit-PatchSet: 9 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 15:49:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/x86: Set thread local storage in C code
by build bot (Jenkins) (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Raul Rangel, Arthur Heymans. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69435 ) Change subject: cpu/x86: Set thread local storage in C code ...................................................................... Patch Set 5: (1 comment) File src/cpu/x86/mp_init.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163225): https://review.coreboot.org/c/coreboot/+/69435/comment/162675bc_51a1def7 PS5, Line 179: static void asmlinkage ap_init(unsigned int index) storage class 'asmlinkage' should be located before type 'void' -- To view, visit https://review.coreboot.org/c/coreboot/+/69435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19d3285daf97798a2d28408b5601ad991e29e718 Gerrit-Change-Number: 69435 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 10 Nov 2022 15:47:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/x86: Set thread local storage in C code
by Arthur Heymans (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Raul Rangel, Arthur Heymans. Hello build bot (Jenkins), Raul Rangel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69435 to look at the new patch set (#5). Change subject: cpu/x86: Set thread local storage in C code ...................................................................... cpu/x86: Set thread local storage in C code Doing this in C code is way easier to understand. Also the thread local storage is now in .bss instead of the AP stack. This makes it more robust against stack overflows, as APs stacks overflow in each other. TESTED: work on qemu. Change-Id: I19d3285daf97798a2d28408b5601ad991e29e718 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/c_start.S M src/arch/x86/cpu.c M src/arch/x86/include/arch/cpu.h D src/cpu/x86/cpu_info.S.inc M src/cpu/x86/mp_init.c M src/cpu/x86/sipi_vector.S 6 files changed, 71 insertions(+), 110 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/69435/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/69435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19d3285daf97798a2d28408b5601ad991e29e718 Gerrit-Change-Number: 69435 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/var/gladios: use i2c1 for TPM support
by Tarun Tuli (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Kevin Chiu, Nick Vaccaro, Ricky Chang. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69424 ) Change subject: mb/google/brya/var/gladios: use i2c1 for TPM support ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6f2bf2a79df883bcb70171051cec4c577ca3bc4 Gerrit-Change-Number: 69424 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 15:42:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/nvidia/tegra124: Fix building with clang
by Martin Roth (Code Review) 10 Nov '22

10 Nov '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63063 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/nvidia/tegra124: Fix building with clang ...................................................................... soc/nvidia/tegra124: Fix building with clang This kind of allocation without '=' is not working with clang. Change-Id: I2d3e9eb44c3e0e25e5a67c5386e5ddde1487cc74 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63063 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/nvidia/tegra124/clock.c 1 file changed, 23 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index a2427fe..f8a232f 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -90,35 +90,35 @@ struct pllcx_dividers plldp; /* target; 270 MHz */ /* PLLDP treats p differently (OUT = VCO / (p + 1) for p < 6). */ } static const osc_table[16] = { - [OSC_FREQ_12]{ + [OSC_FREQ_12] = { .khz = 12000, .pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0}, .pllc = {.n = 50, .m = 1, .p = 0}, .pllu = {.n = 960, .m = 12, .p = 0, .cpcon = 12, .lfcon = 2}, .plldp = {.n = 90, .m = 1, .p = 3}, }, - [OSC_FREQ_13]{ + [OSC_FREQ_13] = { .khz = 13000, .pllx = {.n = TEGRA_PLLX_KHZ / 13000, .m = 1, .p = 0}, .pllc = {.n = 46, .m = 1, .p = 0}, /* 598.0 MHz */ .pllu = {.n = 960, .m = 13, .p = 0, .cpcon = 12, .lfcon = 2}, .plldp = {.n = 83, .m = 1, .p = 3}, /* 269.8 MHz */ }, - [OSC_FREQ_16P8]{ + [OSC_FREQ_16P8] = { .khz = 16800, .pllx = {.n = TEGRA_PLLX_KHZ / 16800, .m = 1, .p = 0}, .pllc = {.n = 71, .m = 1, .p = 1}, /* 596.4 MHz */ .pllu = {.n = 400, .m = 7, .p = 0, .cpcon = 5, .lfcon = 2}, .plldp = {.n = 64, .m = 1, .p = 3}, /* 268.8 MHz */ }, - [OSC_FREQ_19P2]{ + [OSC_FREQ_19P2] = { .khz = 19200, .pllx = {.n = TEGRA_PLLX_KHZ / 19200, .m = 1, .p = 0}, .pllc = {.n = 62, .m = 1, .p = 1}, /* 595.2 MHz */ .pllu = {.n = 200, .m = 4, .p = 0, .cpcon = 3, .lfcon = 2}, .plldp = {.n = 56, .m = 1, .p = 3}, /* 268.8 MHz */ }, - [OSC_FREQ_26]{ + [OSC_FREQ_26] = { .khz = 26000, .pllx = {.n = TEGRA_PLLX_KHZ / 26000, .m = 1, .p = 0}, .pllc = {.n = 23, .m = 1, .p = 0}, /* 598.0 MHz */ @@ -127,14 +127,14 @@ }, /* These oscillators get predivided as PLL inputs... n/m/p divisors for * 38.4 should always match 19.2, and 48 should always match 12. */ - [OSC_FREQ_38P4]{ + [OSC_FREQ_38P4] = { .khz = 38400, .pllx = {.n = TEGRA_PLLX_KHZ / 19200, .m = 1, .p = 0}, .pllc = {.n = 62, .m = 1, .p = 1}, /* 595.2 MHz */ .pllu = {.n = 200, .m = 4, .p = 0, .cpcon = 3, .lfcon = 2}, .plldp = {.n = 56, .m = 1, .p = 3}, /* 268.8 MHz */ }, - [OSC_FREQ_48]{ + [OSC_FREQ_48] = { .khz = 48000, .pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0}, .pllc = {.n = 50, .m = 1, .p = 0}, -- To view, visit https://review.coreboot.org/c/coreboot/+/63063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d3e9eb44c3e0e25e5a67c5386e5ddde1487cc74 Gerrit-Change-Number: 63063 Gerrit-PatchSet: 27 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/sifive/ux00ddr.h: Remove set but unused variables
by Martin Roth (Code Review) 10 Nov '22

10 Nov '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63074 ) ( 16 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/sifive/ux00ddr.h: Remove set but unused variables ...................................................................... soc/sifive/ux00ddr.h: Remove set but unused variables It looks like this code was not finished so it's left commented out for now. Change-Id: I442a42e297f2968dd2c824a93a9a1e2bc74ea2f4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63074 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/sifive/fu540/ux00ddr.h 1 file changed, 20 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/sifive/fu540/ux00ddr.h b/src/soc/sifive/fu540/ux00ddr.h index cc67508..bf856f3 100644 --- a/src/soc/sifive/fu540/ux00ddr.h +++ b/src/soc/sifive/fu540/ux00ddr.h @@ -176,10 +176,10 @@ if (failc0 || failc1) { //if (fails==0) uart_puts((void*) UART0_CTRL_ADDR, "DDR error in fixing up \n"); fails |= (1<<dq); - char slicelsc = '0'; - char slicemsc = '0'; - slicelsc += (dq % 10); - slicemsc += (dq / 10); + /* char slicelsc = '0'; */ + /* char slicemsc = '0'; */ + /* slicelsc += (dq % 10); */ + /* slicemsc += (dq / 10); */ //uart_puts((void*) UART0_CTRL_ADDR, "S "); //uart_puts((void*) UART0_CTRL_ADDR, &slicemsc); //uart_puts((void*) UART0_CTRL_ADDR, &slicelsc); -- To view, visit https://review.coreboot.org/c/coreboot/+/63074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I442a42e297f2968dd2c824a93a9a1e2bc74ea2f4 Gerrit-Change-Number: 63074 Gerrit-PatchSet: 28 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: drivers/spi: Add support for Macronix SPI ROM MX77U25650F
by Martin L Roth (Code Review) 10 Nov '22

10 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69381 ) Change subject: drivers/spi: Add support for Macronix SPI ROM MX77U25650F ...................................................................... drivers/spi: Add support for Macronix SPI ROM MX77U25650F Change-Id: I8fedea1d566f0c35a9e028d4b2bb939592bd5f74 Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69381 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/drivers/spi/macronix.c 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index b6981e0..cc834d9 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -138,6 +138,11 @@ .id[0] = 0x9517, .nr_sectors_shift = 11, }, + { + /* MX77U25650F */ + .id[0] = 0x7539, + .nr_sectors_shift = 13, + }, }; const struct spi_flash_vendor_info spi_flash_macronix_vi = { -- To view, visit https://review.coreboot.org/c/coreboot/+/69381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fedea1d566f0c35a9e028d4b2bb939592bd5f74 Gerrit-Change-Number: 69381 Gerrit-PatchSet: 2 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: ec/google/chromeec: Fix USB_PD_PORTS response data type
by Martin L Roth (Code Review) 10 Nov '22

10 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69370 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: ec/google/chromeec: Fix USB_PD_PORTS response data type ...................................................................... ec/google/chromeec: Fix USB_PD_PORTS response data type The EC_CMD_USB_PD_PORTS host command returns a struct ec_response_usb_pd_ports, not a struct ec_response_charge_port_count. Luckily, both structs have the same memory layout, so this is simply a name change. BUG=b:258126464 BRANCH=none TEST=none Change-Id: I0d7710ca8a45f0ea3939f58bbba6bab31ff41919 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69370 Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/google/chromeec/ec.c 1 file changed, 26 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Daisuke Nojiri: Looks good to me, approved diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 3afe840..01f9ff4 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1378,7 +1378,7 @@ int google_chromeec_get_num_pd_ports(unsigned int *num_ports) { - struct ec_response_charge_port_count resp = {}; + struct ec_response_usb_pd_ports resp = {}; struct chromeec_command cmd = { .cmd_code = EC_CMD_USB_PD_PORTS, .cmd_version = 0, @@ -1393,7 +1393,7 @@ if (rv) return rv; - *num_ports = resp.port_count; + *num_ports = resp.num_ports; return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/69370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d7710ca8a45f0ea3939f58bbba6bab31ff41919 Gerrit-Change-Number: 69370 Gerrit-PatchSet: 4 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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