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Change subject: util/xcompile: Fix building for clang + 64bit
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69232/comment/2cb91262_9b3fcad3
PS8, Line 9: and the -ccc-gcc-name variable is
: not needed anymore.
Please mention the LLVM/clang version.
The option was added in commit 8ef928af4ed7 (xcompile: Fix compiler invocation in testcc).
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Change subject: ACPI: Add acpi_create_madt_ioapic_from_hw()
......................................................................
Patch Set 10:
(1 comment)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/55310/comment/68b53719_66f93bf6
PS3, Line 186: int acpi_create_madt_ioapic_from_hw(acpi_madt_ioapic_t *ioapic, u32 addr)
> I added the comment about order of calls and I agree we should do something better. […]
Ack
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Change subject: libpayload: Enable LTO by default
......................................................................
Patch Set 12:
(1 comment)
Patchset:
PS12:
Angel, at last weeks meeting you said something about adding a build config for LTO. Could you please elaborate? If it’s enabled by default no dedicated configuration is needed, is it?
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Change subject: cpu/x86: Set up cpu_info storage using MSR
......................................................................
Patch Set 5:
(2 comments)
File src/arch/x86/include/arch/cpu.h:
https://review.coreboot.org/c/coreboot/+/68913/comment/74acc404_ac278795
PS5, Line 156: (cpuid_edx(0x80000001) & (1 << 29)) != 0;
Make this a helper method so you don't need to duplicate it.
https://review.coreboot.org/c/coreboot/+/68913/comment/10fd8e5a_8e936b1e
PS5, Line 159: msr_t msr = rdmsr(IA32_GS_BASE);
: ci = (struct cpu_info *)(uintptr_t)msr.raw;
: return ci;
```
struct per_cpu_segment_data *segment_data = (struct per_cpu_segment_data *)(uintptr_t)msr.raw;
return segment_data->cpu_info.
```
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Change subject: soc/qualcomm/sc7280: Add API to differentialize PRO and NON_PRO SKUs
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Patch Set 14: -Code-Review
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Change subject: cpu/x86: Set thread local storage in C code
......................................................................
Patch Set 5: Code-Review+1
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69435/comment/6625c3c3_07d3e467
PS5, Line 11: overflow
Be nice if we could enable paging :)
File src/arch/x86/cpu.c:
https://review.coreboot.org/c/coreboot/+/69435/comment/4212286b_4aa4938a
PS5, Line 346: cpu_info
Can you make this a `struct per_cpu_segment_data` so we keep using the same thing as `cpu_info()`.
File src/cpu/x86/mp_init.c:
https://review.coreboot.org/c/coreboot/+/69435/comment/61af0bc8_28c7bdde
PS5, Line 181: struct cpu_info *info = cpu_info();
So the reason that cpu_info was setup very early on was that `printk` calls `spin_lock` which calls `thread_coop_disable`. `thread_coop_disable used to call `cpu_info`, so if the cpu_info wasn't setup early on then we would be reading an invalid value and bad things would happen. With https://review.coreboot.org/c/coreboot/+/58199 we dropped the requirement on cpu_info and switched over to using `boot_cpu()` which doesn't require any initial setup. So moving it into C code I think is a great idea.
https://review.coreboot.org/c/coreboot/+/69435/comment/6ec5611f_1f70a9bb
PS5, Line 179: static void asmlinkage ap_init(unsigned int index)
> storage class 'asmlinkage' should be located before type 'void'
Please fix.
File src/cpu/x86/sipi_vector.S:
https://review.coreboot.org/c/coreboot/+/69435/comment/01f5f70c_f1f71ede
PS5, Line 93: /* Obtain CPU number. */
: movl ap_count, %ecx
: inc %ecx
: lock cmpxchg %ecx, ap_count
: jnz 1b
I wonder if we could just use the APIC ID instead of racing to get an AP number.
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Change subject: soc/qualcomm/sc7280: Add API to differentialize PRO and NON_PRO SKUs
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