coreboot-gerrit November 2022

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[S] Change in coreboot[master]: soc/qualcomm/sc7280: Update Skuid to support pro/non-pro
by Shelley Chen (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Venkat Thogaru, Paul Menzel, Sudheer Amrabadi. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68385 ) Change subject: soc/qualcomm/sc7280: Update Skuid to support pro/non-pro ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec392c03c2e2c79d20b1fcb79236ca9e048bfd07 Gerrit-Change-Number: 68385 Gerrit-PatchSet: 15 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Thu, 10 Nov 2022 19:24:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [RFC] cpu/x86/lapic: Always have LAPIC enabled
by Kyösti Mälkki (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Kyösti Mälkki. Hello build bot (Jenkins), Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61794 to look at the new patch set (#2). Change subject: [RFC] cpu/x86/lapic: Always have LAPIC enabled ...................................................................... [RFC] cpu/x86/lapic: Always have LAPIC enabled LAPIC has been available since P54C released 1993. Change-Id: Id564a3007ea7a3d9fb81005a05399a18c4cf7289 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/lapic/lapic.c M src/include/cpu/x86/lapic.h 2 files changed, 12 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/61794/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id564a3007ea7a3d9fb81005a05399a18c4cf7289 Gerrit-Change-Number: 61794 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: arch/x86/ioapic: Reduce API exposure
by Kyösti Mälkki (Code Review) 10 Nov '22

10 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55316 ) Change subject: arch/x86/ioapic: Reduce API exposure ...................................................................... arch/x86/ioapic: Reduce API exposure Change-Id: I6ff18e5ede0feda65f81c064394febd3eebc5247 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55316 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/include/arch/ioapic.h M src/arch/x86/ioapic.c 2 files changed, 17 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 288f54c..12f9387 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -26,9 +26,6 @@ #define SMI (2 << 8) #define INT (1 << 8) -u32 io_apic_read(void *ioapic_base, u32 reg); -void io_apic_write(void *ioapic_base, u32 reg, u32 value); -void set_ioapic_id(void *ioapic_base, u8 ioapic_id); u8 get_ioapic_id(void *ioapic_base); u8 get_ioapic_version(void *ioapic_base); diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index 1440bb4..28bbcb1 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -6,13 +6,13 @@ #include <console/console.h> #include <cpu/x86/lapic.h> -u32 io_apic_read(void *ioapic_base, u32 reg) +static u32 io_apic_read(void *ioapic_base, u32 reg) { write32(ioapic_base, reg); return read32(ioapic_base + 0x10); } -void io_apic_write(void *ioapic_base, u32 reg, u32 value) +static void io_apic_write(void *ioapic_base, u32 reg, u32 value) { write32(ioapic_base, reg); write32(ioapic_base + 0x10, value); @@ -108,7 +108,7 @@ } } -void set_ioapic_id(void *ioapic_base, u8 ioapic_id) +static void set_ioapic_id(void *ioapic_base, u8 ioapic_id) { int i; -- To view, visit https://review.coreboot.org/c/coreboot/+/55316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ff18e5ede0feda65f81c064394febd3eebc5247 Gerrit-Change-Number: 55316 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: sb/intel/i82870: Use register_new_ioapic()
by Kyösti Mälkki (Code Review) 10 Nov '22

10 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58407 ) Change subject: sb/intel/i82870: Use register_new_ioapic() ...................................................................... sb/intel/i82870: Use register_new_ioapic() Commentary about mixing LAPIC IDs and IOAPIC IDs was wrong, remove it. The only platform affected is aopen/dxplplusu with i82801dx southbridge. Change-Id: I1276a2050cabaaf07f740c2490d92c48bd5801fa Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58407 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82870/ioapic.c 1 file changed, 18 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index 65fecd1..f6a4ac0 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -8,8 +8,6 @@ #include <assert.h> #include "82870.h" -static int num_p64h2_ioapics = 0; - static void p64h2_ioapic_enable(struct device *dev) { /* We have to enable MEM and Bus Master for IOAPIC */ @@ -30,34 +28,13 @@ static void p64h2_ioapic_init(struct device *dev) { uint32_t memoryBase; - int apic_index, apic_id; - - apic_index = num_p64h2_ioapics; - num_p64h2_ioapics++; - - // A note on IOAPIC addresses: - // 0 and 1 are used for the local APICs of the dual virtual - // (hyper-threaded) CPUs of physical CPU 0 (devicetree.cb). - // 6 and 7 are used for the local APICs of the dual virtual - // (hyper-threaded) CPUs of physical CPU 1 (devicetree.cb). - // 2 is used for the IOAPIC in the 82801 southbridge (hard-coded in i82801xx_lpc.c) - - // Map APIC index into APIC ID - // IDs 3, 4, 5, and 8+ are available (see above note) - - if (apic_index < 3) - apic_id = apic_index + 3; - else - apic_id = apic_index + 5; - - ASSERT(apic_id < 16); // ID is only 4 bits // Read the MBAR address for setting up the IOAPIC in memory space // NOTE: this address was assigned during enumeration of the bus memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - set_ioapic_id((void *)memoryBase, apic_id); + register_new_ioapic((void *)memoryBase); // Use Processor System Bus to deliver interrupts ioapic_set_boot_config((void *)memoryBase, true); -- To view, visit https://review.coreboot.org/c/coreboot/+/58407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1276a2050cabaaf07f740c2490d92c48bd5801fa Gerrit-Change-Number: 58407 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: drivers/generic/ioapic: Use register_new_ioapic_gsi0()
by Kyösti Mälkki (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Stefan Ott, Alexander Couzens, Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55315 ) Change subject: drivers/generic/ioapic: Use register_new_ioapic_gsi0() ...................................................................... Patch Set 9: Code-Review-2 (1 comment) File src/mainboard/lenovo/t400/devicetree.cb: https://review.coreboot.org/c/coreboot/+/55315/comment/cf3eb6e2_31a75f5e PS9, Line 136: ioapic_irq 2 INTA 0x10 We are linking to this with the ioapic id I suggest to remove. Potentially only used with MP table but I will check. -- To view, visit https://review.coreboot.org/c/coreboot/+/55315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b03d32fa16fb9eb8a035e58bb7e3e027904f076 Gerrit-Change-Number: 55315 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 10 Nov 2022 19:17:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: amdfwtool: Add new family morgana
by Martin Roth (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Bao Zheng, Jason Glenesk, Marshall Dawson, Matt DeVillier, Zheng Bao, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69046 ) Change subject: amdfwtool: Add new family morgana ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib82f6c03b93d277f3f7f27ce57c1a41fdc103575 Gerrit-Change-Number: 69046 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 10 Nov 2022 19:10:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: sb,soc/intel: Use register_new_ioapic_gsi0()
by Kyösti Mälkki (Code Review) 10 Nov '22

10 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55314 ) Change subject: sb,soc/intel: Use register_new_ioapic_gsi0() ...................................................................... sb,soc/intel: Use register_new_ioapic_gsi0() Change-Id: I6b0e4021595fb160ae3bf798468f4505b460266f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55314 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/broadwell/pch/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/denverton_ns/lpc.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 10 files changed, 23 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 5a1623f..1ddee34 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -33,7 +33,7 @@ /* PCH-LP has 40 redirection entries */ ioapic_set_max_vectors(VIO_APIC_VADDR, 40); - setup_ioapic(VIO_APIC_VADDR, 0x02); + register_new_ioapic_gsi0(VIO_APIC_VADDR); } static void enable_hpet(struct device *dev) diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index d499918..c820203 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -387,7 +387,7 @@ /* affirm full set of redirection table entries ("write once") */ ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR); - setup_ioapic((void *)IO_APIC_ADDR, 0x02); + register_new_ioapic_gsi0((void *)IO_APIC_ADDR); } static const uint8_t pch_interrupt_routing[PIRQ_COUNT] = { diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 5d1eda5..7ebca1e 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -34,7 +34,7 @@ /* affirm full set of redirection table entries ("write once") */ ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR); - setup_ioapic((void *)IO_APIC_ADDR, IO_APIC0); + register_new_ioapic_gsi0((void *)IO_APIC_ADDR); } /* interrupt router lookup for internal devices */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 4635189..7c10c81 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -44,7 +44,7 @@ /* affirm full set of redirection table entries ("write once") */ ioapic_lock_max_vectors(VIO_APIC_VADDR); - setup_ioapic(VIO_APIC_VADDR, 0x02); + register_new_ioapic_gsi0(VIO_APIC_VADDR); } static void pch_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 1de3766..1569c1c 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -50,7 +50,7 @@ pci_write_config32(dev, GEN_CNTL, reg32); printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - setup_ioapic(VIO_APIC_VADDR, 0x02); + register_new_ioapic_gsi0(VIO_APIC_VADDR); ioapic_set_boot_config(VIO_APIC_VADDR, true); } diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 90d4eab..ec0df27 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -33,7 +33,7 @@ */ static void i82801gx_enable_ioapic(struct device *dev) { - setup_ioapic(VIO_APIC_VADDR, 0x02); + register_new_ioapic_gsi0(VIO_APIC_VADDR); } static void i82801gx_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 8d44384..24b8a27 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -35,7 +35,7 @@ /* Lock maximum redirection entries (MRE), R/WO register. */ ioapic_lock_max_vectors(VIO_APIC_VADDR); - setup_ioapic(VIO_APIC_VADDR, 2); /* ICH7 code uses id 2. */ + register_new_ioapic_gsi0(VIO_APIC_VADDR); } static void i82801ix_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 1297837..7dfc33f 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -36,7 +36,7 @@ /* Lock maximum redirection entries (MRE), R/WO register. */ ioapic_lock_max_vectors(VIO_APIC_VADDR); - setup_ioapic(VIO_APIC_VADDR, 2); /* ICH7 code uses id 2. */ + register_new_ioapic_gsi0(VIO_APIC_VADDR); } static void i82801jx_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index d4e3098..f0d0ac9 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -35,7 +35,7 @@ /* affirm full set of redirection table entries ("write once") */ ioapic_lock_max_vectors(VIO_APIC_VADDR); - setup_ioapic(VIO_APIC_VADDR, 0x01); + register_new_ioapic_gsi0(VIO_APIC_VADDR); } static void pch_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 20e40cb..b8e9d5f 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -42,8 +42,7 @@ else ioapic_lock_max_vectors(VIO_APIC_VADDR); - setup_ioapic(VIO_APIC_VADDR, 0x02); - + register_new_ioapic_gsi0(VIO_APIC_VADDR); } static void pch_enable_serial_irqs(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/55314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b0e4021595fb160ae3bf798468f4505b460266f Gerrit-Change-Number: 55314 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: drivers/fsp2: Don't die if the FSP signature doesn't match
by Jason Glenesk (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Jason Glenesk, Martin L Roth, Andrey Petrov, Fred Reitberger, Felix Held. Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69412 ) Change subject: drivers/fsp2: Don't die if the FSP signature doesn't match ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12aca7cad3298ac36b1fed09efaa190c958cf126 Gerrit-Change-Number: 69412 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 10 Nov 2022 19:10:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: sb,soc/intel: Use acpi_create_madt_ioapic_from_hw()
by Kyösti Mälkki (Code Review) 10 Nov '22

10 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55311 ) Change subject: sb,soc/intel: Use acpi_create_madt_ioapic_from_hw() ...................................................................... sb,soc/intel: Use acpi_create_madt_ioapic_from_hw() Change-Id: I9fd9cf230ce21674d1c24b40f310e5558e65be25 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55311 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/aopen/dxplplusu/acpi_tables.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/southbridge/intel/common/madt.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/madt.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/madt.c 9 files changed, 24 insertions(+), 28 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c index 7faa73d..2a3a97e 100644 --- a/src/mainboard/aopen/dxplplusu/acpi_tables.c +++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c @@ -8,15 +8,8 @@ #include <acpi/acpi.h> #include <device/pci_def.h> -#define IOAPIC_ICH4 2 -#define IOAPIC_P64H2_BUS_B 3 /* IOAPIC 3 at 02:1c.0 */ -#define IOAPIC_P64H2_BUS_A 4 /* IOAPIC 4 at 02:1e.0 */ - -#define INTEL_IOAPIC_NUM_INTERRUPTS 24 /* Both ICH-4 and P64-H2 */ - unsigned long acpi_fill_madt(unsigned long current) { - unsigned int irq_start = 0; struct device *bdev, *dev = NULL; struct resource *res = NULL; @@ -27,9 +20,7 @@ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 7); /* Southbridge IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH4, - 0xfec00000, irq_start); - irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, 0xfec00000); bdev = pcidev_on_root(2, 0); /* P64H2 Bus B IOAPIC */ @@ -37,9 +28,7 @@ dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(28, 0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - IOAPIC_P64H2_BUS_B, res->base, irq_start); - irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, res->base); } /* P64H2 Bus A IOAPIC */ @@ -47,9 +36,7 @@ dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(30, 0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - IOAPIC_P64H2_BUS_A, res->base, irq_start); - irq_start += INTEL_IOAPIC_NUM_INTERRUPTS; + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, res->base); } /* Map ISA IRQ 0 to IRQ 2 */ diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 0f97687..7589464 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -92,8 +92,7 @@ current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); current = acpi_madt_irq_overrides(current); diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index cb9cb2d..1c9eb4e 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -332,7 +332,7 @@ current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); current = acpi_madt_irq_overrides(current); diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index f0903ff..c355c944 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -105,7 +105,7 @@ } } else { /* Default SOC IOAPIC entry */ - current += acpi_create_madt_ioapic((void *)current, 2, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic_from_hw((void *)current, IO_APIC_ADDR); } return acpi_madt_irq_overrides(current); diff --git a/src/southbridge/intel/common/madt.c b/src/southbridge/intel/common/madt.c index 3eebe3a..eb11c21 100644 --- a/src/southbridge/intel/common/madt.c +++ b/src/southbridge/intel/common/madt.c @@ -10,7 +10,7 @@ current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 4d82706..90d4eab 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -355,7 +355,7 @@ current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); /* LAPIC_NMI */ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) diff --git a/src/southbridge/intel/i82801ix/madt.c b/src/southbridge/intel/i82801ix/madt.c index f3a7da5..19d5d8c 100644 --- a/src/southbridge/intel/i82801ix/madt.c +++ b/src/southbridge/intel/i82801ix/madt.c @@ -10,8 +10,7 @@ current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); /* LAPIC_NMI */ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 41bcccd..1297837 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -370,8 +370,7 @@ current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); /* LAPIC_NMI */ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) diff --git a/src/southbridge/intel/ibexpeak/madt.c b/src/southbridge/intel/ibexpeak/madt.c index 0c58f7f..a1a28a1 100644 --- a/src/southbridge/intel/ibexpeak/madt.c +++ b/src/southbridge/intel/ibexpeak/madt.c @@ -12,8 +12,7 @@ current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - 1, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) -- To view, visit https://review.coreboot.org/c/coreboot/+/55311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fd9cf230ce21674d1c24b40f310e5558e65be25 Gerrit-Change-Number: 55311 Gerrit-PatchSet: 11 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: arch/x86: Add register_new_ioapic()
by Kyösti Mälkki (Code Review) 10 Nov '22

10 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55313 ) Change subject: arch/x86: Add register_new_ioapic() ...................................................................... arch/x86: Add register_new_ioapic() Using this I/O APIC IDs will be assigned incrementally in the order of calling. I/O APIC ID #0 is reserved for the I/O APIC delivering GSI #0. Change-Id: I6493dc3b4fa542e81f80bb0355eac6dad30b93ec Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55313 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/include/arch/ioapic.h M src/arch/x86/ioapic.c 2 files changed, 32 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 9e524e2..288f54c 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -37,6 +37,8 @@ void ioapic_lock_max_vectors(void *ioapic_base); void setup_ioapic(void *ioapic_base, u8 ioapic_id); +void register_new_ioapic(void *ioapic_base); +void register_new_ioapic_gsi0(void *ioapic_base); void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb); #endif diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index d65637c..1440bb4 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -163,3 +163,16 @@ clear_vectors(ioapic_base, 0, ioapic_get_max_vectors(ioapic_base) - 1); route_i8259_irq0(ioapic_base); } + +void register_new_ioapic_gsi0(void *ioapic_base) +{ + setup_ioapic(ioapic_base, 0); +} + +void register_new_ioapic(void *ioapic_base) +{ + static u8 ioapic_id; + ioapic_id++; + set_ioapic_id(ioapic_base, ioapic_id); + clear_vectors(ioapic_base, 0, ioapic_get_max_vectors(ioapic_base) - 1); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/55313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6493dc3b4fa542e81f80bb0355eac6dad30b93ec Gerrit-Change-Number: 55313 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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