coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: mb/emulation/q35: Fix running with qemu-i386 with SMM_TSEG
by Kyösti Mälkki (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Paul Menzel, Angel Pons, Arthur Heymans. Kyösti Mälkki has uploaded a new patch set (#6) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/55138 ) Change subject: mb/emulation/q35: Fix running with qemu-i386 with SMM_TSEG ...................................................................... mb/emulation/q35: Fix running with qemu-i386 with SMM_TSEG Depending on whether qemu emulates an amd64 or i386 machine the SMM save state will differ. The smbase offsets are incompatible between those save states. Tested qemu with TSEG now properly relocates smm on both x86_64 and i386. TESTED both qemu-system-i386 and qemu-system-amd64 (v5.2) have a working smihandler. Change-Id: Ic6994c8d6e10fd06655129dbd801f1f9d5fd639f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/emulation/qemu-q35/cpu.c 1 file changed, 58 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/55138/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/55138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6994c8d6e10fd06655129dbd801f1f9d5fd639f Gerrit-Change-Number: 55138 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: cpu/intel/socket_mPGA604: Drop non-working SSE2 disablement
by Kyösti Mälkki (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Kyösti Mälkki. Hello Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69443 to look at the new patch set (#2). Change subject: cpu/intel/socket_mPGA604: Drop non-working SSE2 disablement ...................................................................... cpu/intel/socket_mPGA604: Drop non-working SSE2 disablement The disablement of SSE2 was not honoured since there is explicit select under CPU_INTEL_MODEL_F2X. The removed commentary originates probably from ROMCC romstage implementation. Change-Id: I7d9ac007406a82c498f3ed23568e2ff064504983 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/socket_mPGA604/Kconfig 1 file changed, 14 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/69443/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d9ac007406a82c498f3ed23568e2ff064504983 Gerrit-Change-Number: 69443 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: google/chromeec: Add ACPI method for EC Panic
by 9elements QA (Code Review) 10 Nov '22

10 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69391 ) Change subject: google/chromeec: Add ACPI method for EC Panic ...................................................................... Patch Set 5: Automatic boot test returned (PASS/FAIL/TOTAL): 12 / 2 / 14 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/135532 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/135530 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/135529 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/135528 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135527 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/135526 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/135525 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/135524 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/135522 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/135521 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/135520 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/135519 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/135518 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/135517 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafa642c1c50f9a0083a8e618e1eabec9a7ce39b4 Gerrit-Change-Number: 69391 Gerrit-PatchSet: 5 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 21:14:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/intel/socket_mPGA604: Drop implicit SSE/SSE2
by Paul Menzel (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Kyösti Mälkki. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69443 ) Change subject: cpu/intel/socket_mPGA604: Drop implicit SSE/SSE2 ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69443/comment/5b3123a5_db4e4d36 PS1, Line 7: implicit SSE/SSE2 non-working implicit SSE/SSE2 disablement -- To view, visit https://review.coreboot.org/c/coreboot/+/69443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d9ac007406a82c498f3ed23568e2ff064504983 Gerrit-Change-Number: 69443 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 20:34:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/intel/socket_mPGA604: Drop implicit SSE/SSE2
by Kyösti Mälkki (Code Review) 10 Nov '22

10 Nov '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69443 ) Change subject: cpu/intel/socket_mPGA604: Drop implicit SSE/SSE2 ...................................................................... cpu/intel/socket_mPGA604: Drop implicit SSE/SSE2 The disablement of SSE2 was not honoured since there is explicit select under CPU_INTEL_MODEL_F2X. The removed commentary originates probably from ROMCC romstage implementation. Change-Id: I7d9ac007406a82c498f3ed23568e2ff064504983 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/socket_mPGA604/Kconfig 1 file changed, 14 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/69443/1 diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 7b08699..12c8e37 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -7,20 +7,12 @@ def_bool y select CPU_INTEL_MODEL_F2X select MMX - select SSE select UDELAY_TSC select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE -# mPGA604 are usually Intel Netburst CPUs which should have SSE2 -# but the ramtest.c code on the Dell S1850 seems to choke on -# enabling it, so disable it for now. -config SSE2 - bool - default n - config DCACHE_RAM_BASE hex default 0xfefc0000 -- To view, visit https://review.coreboot.org/c/coreboot/+/69443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d9ac007406a82c498f3ed23568e2ff064504983 Gerrit-Change-Number: 69443 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: aopen/dxplplusu: Add early GPIO settings
by Kyösti Mälkki (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Kyösti Mälkki, Patrick Rudolph. Hello build bot (Jenkins), Angel Pons, Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52815 to look at the new patch set (#4). Change subject: aopen/dxplplusu: Add early GPIO settings ...................................................................... aopen/dxplplusu: Add early GPIO settings Required for 2nd COM port to work. Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/aopen/dxplplusu/bootblock.c M src/mainboard/aopen/dxplplusu/devicetree.cb M src/southbridge/intel/i82801dx/i82801dx.h 3 files changed, 122 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/52815/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579 Gerrit-Change-Number: 52815 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/morgana: Add 32M support
by Martin Roth (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Bao Zheng, Jason Glenesk, Marshall Dawson, Matt DeVillier, Zheng Bao, Fred Reitberger, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69150 ) Change subject: soc/amd/morgana: Add 32M support ...................................................................... Patch Set 4: Code-Review-2 (1 comment) Patchset: PS4: This change makes so many assumptions about how things are going to work, and breaks so many current assumptions. - We need to be able to support the amd firmware inside CBFS. - We need to be able to support it living at any of the existing addresses. For chromeos, it needs to be within the RO area, which is in the upper half of the ROM. For the non-chromeos *BIRMAN* ROM, some of these assumption may be true, but if we ever wanted to build a chromeos rom that has 3 sections, this will completely break the ability to do that. -- To view, visit https://review.coreboot.org/c/coreboot/+/69150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0b5a75f828033b29c378bed9a939b23d7f19140 Gerrit-Change-Number: 69150 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 10 Nov 2022 20:03:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: amdfwtool: Set the base address of AMDFW as relative
by Martin Roth (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Matt DeVillier, Zheng Bao, Fred Reitberger, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69429 ) Change subject: amdfwtool: Set the base address of AMDFW as relative ...................................................................... Patch Set 2: (7 comments) Patchset: PS2: I think we might want to look at rearchitecting this somewhat. Maybe consider using the offset from the TOP of the rom space instead of the bottom. Then the rom size isn't needed. File src/mainboard/amd/mandolin/Kconfig: https://review.coreboot.org/c/coreboot/+/69429/comment/fb2ba2c8_a28b4ad1 PS2, Line 73: default 5 if BOARD_AMD_MANDOLIN why change this? File src/soc/amd/cezanne/Kconfig: https://review.coreboot.org/c/coreboot/+/69429/comment/61986a30_b95c479e PS2, Line 322: default 5 Why? https://review.coreboot.org/c/coreboot/+/69429/comment/16638832_52fd3c1c PS2, Line 334: comment "AMD Firmware Directory Table set to location 0xFA0000" You've updated the addresses from a memory location to the location in the spi rom without saying so. Maybe update the comments to something like: AMD EFS Table set to SPI ROM location 0xFA0000 File src/soc/amd/cezanne/Makefile.inc: https://review.coreboot.org/c/coreboot/+/69429/comment/603632cf_79f3663e PS2, Line 69: CEZANNE_FWM_POSITION_REL=$(call int-add, \ : $(call int-subtract, 0xffffff \ : $(call int-shift-left, \ : 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) : CEZANNE_FWM_POSITION_PHY=$(call int-add, \ : $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) \ : $(CEZANNE_FWM_POSITION_REL) 1) : : # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes : # Building the cbfs image will fail if the offset isn't large enough : AMD_FW_AB_POSITION := 0x40 : : CEZANNE_FW_A_POSITION=$(call int-subtract, \ : $(call int-add, \ : $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ : $(AMD_FW_AB_POSITION)) \ : $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) : : CEZANNE_FW_B_POSITION=$(call int-subtract, \ : $(call int-add, \ : $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ : $(AMD_FW_AB_POSITION)) \ : $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) I thought we were getting rid of the calculations and just setting the actual values in Kconfig. File src/soc/amd/mendocino/Kconfig: https://review.coreboot.org/c/coreboot/+/69429/comment/7ef5ade2_faf44b9a PS2, Line 327: config AMD_FWM_POSITION_INDEX : int "Firmware Directory Table location (0 to 5)" : range 0 5 : default 5 If we're repeating the same stuff over and over, why not make a single common Kconfig file that has all of this instead of updating it in every location? File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/69429/comment/664d8212_ba80d9b7 PS2, Line 2293: dir_location Can we change everywhere it formerly said location to now say offset? Previously it was an address, now it's the offset from the start of the SPI rom, right? -- To view, visit https://review.coreboot.org/c/coreboot/+/69429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6fd5b21be90ac37618c484506db9b8a1e350ea2 Gerrit-Change-Number: 69429 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 10 Nov 2022 19:54:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: libpayload: Enable LTO by default
by Stefan Reinauer (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Nico Huber, Paul Menzel, Angel Pons, Julius Werner. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51177 ) Change subject: libpayload: Enable LTO by default ...................................................................... Patch Set 12: (1 comment) Patchset: PS12: How has this been tested? There might be breakage in individual drivers by enabling LTO. Did we do at least some testing of a majority of drivers / libpayload subsystems before enabling this? -- To view, visit https://review.coreboot.org/c/coreboot/+/51177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bc58034ea8a9510ddc08d61d19e75a7c6f9cbc7 Gerrit-Change-Number: 51177 Gerrit-PatchSet: 12 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 10 Nov 2022 19:34:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/picasso: Move AMD firmware from 0x420000 to 0x20000
by Martin Roth (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Bao Zheng, Jason Glenesk, Matt DeVillier, Zheng Bao, Fred Reitberger, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69428 ) Change subject: soc/amd/picasso: Move AMD firmware from 0x420000 to 0x20000 ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: Where do you see the address 0x42000? slot 4 is 0xffc2000, which is absolutely a documented address. #define EFS_OFFSET (0xffffff - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX) + 0x20000 + 1) I don't think this patch is needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/69428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62e22dd5eeb5b85497efcf1e753415c0a6fdf2ca Gerrit-Change-Number: 69428 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 10 Nov 2022 19:32:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2022