coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[S] Change in coreboot[master]: ACPI: Add acpi_create_madt_ioapic_from_hw()
by Kyösti Mälkki (Code Review) 10 Nov '22

10 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55310 ) Change subject: ACPI: Add acpi_create_madt_ioapic_from_hw() ...................................................................... ACPI: Add acpi_create_madt_ioapic_from_hw() Read I/O APIC ID and vector counts from hardware. Change-Id: Ia173582eaad305000f958c5d207e9efaa06d8750 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55310 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 36 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index e211558..3ddb1d0 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -30,6 +30,10 @@ #include <types.h> #include <version.h> +#if ENV_X86 +#include <arch/ioapic.h> +#endif + static acpi_rsdp_t *valid_rsdp(acpi_rsdp_t *rsdp); u8 acpi_checksum(u8 *table, u32 length) @@ -180,6 +184,22 @@ return ioapic->length; } +#if ENV_X86 +/* For a system with multiple I/O APICs it's required that the one potentially + routing i8259 via ExtNMI delivery calls this first to get GSI #0. */ +int acpi_create_madt_ioapic_from_hw(acpi_madt_ioapic_t *ioapic, u32 addr) +{ + static u32 gsi_base; + u32 my_base; + u8 id = get_ioapic_id((void *)(uintptr_t)addr); + u8 count = ioapic_get_max_vectors((void *)(uintptr_t)addr); + + my_base = gsi_base; + gsi_base += count; + return acpi_create_madt_ioapic(ioapic, id, addr, my_base); +} +#endif + int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, u8 bus, u8 source, u32 gsirq, u16 flags) { diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 286ebfa..d7fc243 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1263,6 +1263,7 @@ int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic); int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, u32 gsi_base); +int acpi_create_madt_ioapic_from_hw(acpi_madt_ioapic_t *ioapic, u32 addr); int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, u8 bus, u8 source, u32 gsirq, u16 flags); int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, -- To view, visit https://review.coreboot.org/c/coreboot/+/55310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia173582eaad305000f958c5d207e9efaa06d8750 Gerrit-Change-Number: 55310 Gerrit-PatchSet: 11 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: sb,soc/intel: Use register_new_ioapic_gsi0()
by Kyösti Mälkki (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Keith Hui, Jeff Daly, Branden Waldner, Vanessa Eusebio, Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55314 ) Change subject: sb,soc/intel: Use register_new_ioapic_gsi0() ...................................................................... Patch Set 9: (1 comment) File src/southbridge/intel/i82371eb/isa.c: https://review.coreboot.org/c/coreboot/+/55314/comment/c55076a5_98124870 PS8, Line 64: register_new_ioapic_gsi0(VIO_APIC_VADDR); > The hardware uses APIC BUS so IOAPIC must not overlap any LAPIC ID. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/55314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b0e4021595fb160ae3bf798468f4505b460266f Gerrit-Change-Number: 55314 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 10 Nov 2022 19:07:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/xeon_sp: Move SMBIOS type 4 override functions from mainboa...
by Martin Roth (Code Review) 10 Nov '22

10 Nov '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69363 ) Change subject: soc/intel/xeon_sp: Move SMBIOS type 4 override functions from mainboard to soc ...................................................................... soc/intel/xeon_sp: Move SMBIOS type 4 override functions from mainboard to soc Move SMBIOS type 4 override functions from mainboard to soc so that all xeon family cpus share same functions without implementing again. Tested=On OCP Deltalake, dmidecode -t 4 shows expected info. Signed-off-by: JingleHsuWiwynn <jingle_hsu(a)wiwynn.com> Change-Id: I17df8de67bc2f5e89ea04da36efb2480a7e73174 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69363 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/mainboard/ocp/deltalake/ramstage.c M src/soc/intel/xeon_sp/ramstage.c 2 files changed, 31 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Jonathan Zhang: Looks good to me, approved Martin Roth: Looks good to me, approved diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index fb81e10..0fca920 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -327,17 +327,6 @@ t->bank_locator = smbios_add_string(t->eos, buf); } -unsigned int smbios_processor_family(struct cpuid_result res) -{ - return 0xb3; /* Xeon */ -} - -unsigned int smbios_processor_characteristics(void) -{ - /* 64-bit Capable, Multi-Core, Power/Performance Control */ - return 0x8c; /* BIT2 | BIT3 | BIT7 */ -} - static void mainboard_enable(struct device *dev) { dev->ops->get_smbios_strings = dl_oem_smbios_strings; diff --git a/src/soc/intel/xeon_sp/ramstage.c b/src/soc/intel/xeon_sp/ramstage.c index 68d5d46..9882660 100644 --- a/src/soc/intel/xeon_sp/ramstage.c +++ b/src/soc/intel/xeon_sp/ramstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/cpu.h> #include <smbios.h> unsigned int smbios_cache_error_correction_type(u8 level) @@ -24,3 +25,13 @@ return SMBIOS_CACHE_OP_MODE_UNKNOWN; } } + +unsigned int smbios_processor_family(struct cpuid_result res) +{ + return SMBIOS_PROCESSOR_FAMILY_XEON; +} + +unsigned int smbios_processor_characteristics(void) +{ + return PROCESSOR_64BIT_CAPABLE|PROCESSOR_MULTI_CORE|PROCESSOR_POWER_PERFORMANCE_CONTROL; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/69363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17df8de67bc2f5e89ea04da36efb2480a7e73174 Gerrit-Change-Number: 69363 Gerrit-PatchSet: 3 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/intel/xeon_sp: Move SMBIOS type 4 override functions from mainboa...
by Martin Roth (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Johnny Lin, Christian Walter, Shuming Chu (Shuming), Arthur Heymans, Elyes Haouas. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69363 ) Change subject: soc/intel/xeon_sp: Move SMBIOS type 4 override functions from mainboard to soc ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17df8de67bc2f5e89ea04da36efb2480a7e73174 Gerrit-Change-Number: 69363 Gerrit-PatchSet: 2 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 10 Nov 2022 19:06:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: src/include/smbios: Add definition for smbios type 4 and type 9
by Martin Roth (Code Review) 10 Nov '22

10 Nov '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68902 ) Change subject: src/include/smbios: Add definition for smbios type 4 and type 9 ...................................................................... src/include/smbios: Add definition for smbios type 4 and type 9 Add definition for smbios type 4 and type 9 Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: I559995b0204f8e5bdeef2c0f8b394f9011d72240 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68902 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/include/smbios.h 1 file changed, 27 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jonathan Zhang: Looks good to me, approved Martin Roth: Looks good to me, approved diff --git a/src/include/smbios.h b/src/include/smbios.h index 3611eb6..cb317b0 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -485,6 +485,16 @@ #define SMBIOS_PROCESSOR_STATUS_POPULATED (1 << 6) #define SMBIOS_PROCESSOR_STATUS_CPU_ENABLED (1 << 0) +/* defines for processor family */ +#define SMBIOS_PROCESSOR_FAMILY_OTHER 0x01 +#define SMBIOS_PROCESSOR_FAMILY_UNKNOWN 0x02 +#define SMBIOS_PROCESSOR_FAMILY_XEON 0xb3 + +/* defines for processor characteristics */ +#define PROCESSOR_64BIT_CAPABLE (1 << 2) +#define PROCESSOR_MULTI_CORE (1 << 3) +#define PROCESSOR_POWER_PERFORMANCE_CONTROL (1 << 7) + /* defines for supported_sram_type/current_sram_type */ #define SMBIOS_CACHE_SRAM_TYPE_OTHER (1 << 0) @@ -721,6 +731,7 @@ SlotTypePciExpressMini52pinWithBSKO = 0x21, SlotTypePciExpressMini52pinWithoutBSKO = 0x22, SlotTypePciExpressMini76pin = 0x23, + SlotTypePciExpressOCPNIC30SFF = 0x26, SlotTypePC98C20 = 0xA0, SlotTypePC98C24 = 0xA1, SlotTypePC98E = 0xA2, -- To view, visit https://review.coreboot.org/c/coreboot/+/68902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I559995b0204f8e5bdeef2c0f8b394f9011d72240 Gerrit-Change-Number: 68902 Gerrit-PatchSet: 6 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: src/include/smbios: Add definition for smbios type 4 and type 9
by Martin Roth (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Paul Menzel, Angel Pons, Shuming Chu (Shuming), Tim Chu. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68902 ) Change subject: src/include/smbios: Add definition for smbios type 4 and type 9 ...................................................................... Patch Set 5: Code-Review+2 (3 comments) File src/include/smbios.h: https://review.coreboot.org/c/coreboot/+/68902/comment/b78fc2ef_9ecdad1d PS5, Line 488: /* defines for processor family */ https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/defau… Table 23 – Processor Information: Processor Family field https://review.coreboot.org/c/coreboot/+/68902/comment/4beaf784_413dfba0 PS5, Line 493: /* defines for processor characteristics */ Table 27 – Processor Characteristics https://review.coreboot.org/c/coreboot/+/68902/comment/eef7fa45_36ee6d37 PS5, Line 697: /* System Slots - Slot Type */ Table 45 – System Slots: Slot Type field -- To view, visit https://review.coreboot.org/c/coreboot/+/68902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I559995b0204f8e5bdeef2c0f8b394f9011d72240 Gerrit-Change-Number: 68902 Gerrit-PatchSet: 5 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 19:05:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/skyrim: Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP
by Martin Roth (Code Review) 10 Nov '22

10 Nov '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67675 ) Change subject: mb/google/skyrim: Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP ...................................................................... mb/google/skyrim: Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP Skyrim platforms have I2C3 controller which is shared between PSP and X86. In order to enable cooperation, PSP acts as an arbitrator. Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP, so that proper driver is binded on the OS side. BUG=b:241878652 BRANCH=none TEST=Build kernel and firmware. Run on skyrim and verify TPM functionality. Signed-off-by: Jan Dabros <jsd(a)semihalf.com> Change-Id: I2a3de8cb2b9241e2d81e02df49f317ac0408d5bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/67675 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/skyrim/Kconfig 1 file changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index d21bcc8..e545ba5 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -37,6 +37,7 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 select SOC_AMD_MENDOCINO + select SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP select SOC_AMD_COMMON_BLOCK_USE_ESPI select TPM_GOOGLE_TI50 select PCIEXP_ASPM -- To view, visit https://review.coreboot.org/c/coreboot/+/67675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a3de8cb2b9241e2d81e02df49f317ac0408d5bb Gerrit-Change-Number: 67675 Gerrit-PatchSet: 3 Gerrit-Owner: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: drivers/intel/fsp2_0/hand_off_block: remove unneeded line breaks
by Raul Rangel (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Andrey Petrov, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69461 ) Change subject: drivers/intel/fsp2_0/hand_off_block: remove unneeded line breaks ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92aa3fec8c8caba143e418efc999ec4a7c5d93c4 Gerrit-Change-Number: 69461 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 10 Nov 2022 18:48:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/amd/root_complex: don't skip reporting IOAPIC resource in !hob case
by Raul Rangel (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69460 ) Change subject: soc/amd/root_complex: don't skip reporting IOAPIC resource in !hob case ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9174c8d7e5e94144187d27210e12f2dca3a6010f Gerrit-Change-Number: 69460 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 10 Nov 2022 18:48:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: arch/x86: Add register_new_ioapic()
by Kyösti Mälkki (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Lance Zhao, Angel Pons. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55313 ) Change subject: arch/x86: Add register_new_ioapic() ...................................................................... Patch Set 9: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55313/comment/44ad53ac_eb92fcd2 PS1, Line 13: overlap when APIC Serial Bus is no longer used. > Hardware perspective is I/O APIC ID register has no functionality with System Bus delivery mode. […] Ack File src/arch/x86/ioapic.c: https://review.coreboot.org/c/coreboot/+/55313/comment/01856f23_68ef5f35 PS3, Line 169: void register_new_ioapic(void *ioapic_base) : { : set_ioapic_id(ioapic_base, ioapic_id); : clear_vectors(ioapic_base, 0, ioapic_get_max_vectors(ioapic_base) - 1); : ioapic_id++; : } > Thanks. A simply search in gerrit didn't locate this change. […] https://review.coreboot.org/c/coreboot/+/55571/8 too With xeon_sp in mind, we potentially will want proper device nodes for IOAPICs and that would clear the dependency of calling order with ACPI generation. -- To view, visit https://review.coreboot.org/c/coreboot/+/55313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6493dc3b4fa542e81f80bb0355eac6dad30b93ec Gerrit-Change-Number: 55313 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 18:44:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2022