coreboot-gerrit November 2022

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[L] Change in coreboot[master]: security/tpm: add TPM log format as per 2.0 spec
by Sergii Dmytruk (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Michał Żygowski, Maciej Pijanowski, Christian Walter, Krystian Hebel. Hello build bot (Jenkins), Michał Żygowski, Maciej Pijanowski, Christian Walter, Krystian Hebel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68748 to look at the new patch set (#5). Change subject: security/tpm: add TPM log format as per 2.0 spec ...................................................................... security/tpm: add TPM log format as per 2.0 spec Used by default for all boards with TPM2 which don't specify log format explicitly. Change-Id: I0fac386bebab1b7104378ae3424957c6497e84e1 Ticket: https://ticket.coreboot.org/issues/422 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/commonlib/include/commonlib/tpm_log_defs.h M src/security/tpm/Kconfig M src/security/tpm/Makefile.inc A src/security/tpm/tpm2_log_serialized.h M src/security/tpm/tspi.h M src/security/tpm/tspi/crtm.h A src/security/tpm/tspi/log-tpm2.c 7 files changed, 368 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/68748/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/68748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fac386bebab1b7104378ae3424957c6497e84e1 Gerrit-Change-Number: 68748 Gerrit-PatchSet: 5 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: security/tpm: add TPM log format as per 1.2 spec
by Sergii Dmytruk (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Michał Żygowski, Maciej Pijanowski, Christian Walter, Krystian Hebel, Sergii Dmytruk. Hello build bot (Jenkins), Michał Żygowski, Maciej Pijanowski, Christian Walter, Krystian Hebel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68747 to look at the new patch set (#5). Change subject: security/tpm: add TPM log format as per 1.2 spec ...................................................................... security/tpm: add TPM log format as per 1.2 spec Used by default for all boards with TPM1 which don't specify log format explicitly. Ticket: https://ticket.coreboot.org/issues/423 Change-Id: I89720615a75573d44dd0a39ad3d7faa78f125843 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h A src/commonlib/include/commonlib/tpm_log_defs.h M src/security/tpm/Kconfig M src/security/tpm/Makefile.inc A src/security/tpm/tpm12_log_serialized.h M src/security/tpm/tspi.h M src/security/tpm/tspi/crtm.h A src/security/tpm/tspi/log-tpm12.c 8 files changed, 282 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/68747/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/68747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89720615a75573d44dd0a39ad3d7faa78f125843 Gerrit-Change-Number: 68747 Gerrit-PatchSet: 5 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: security/tpm: make log format configurable via Kconfig
by Sergii Dmytruk (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Tarun Tuli, Michał Żygowski, Maciej Pijanowski, Jason Nien, Subrata Banik, Christian Walter, Kapil Porwal, Tim Wawrzynczak, Nick Vaccaro, Krystian Hebel, Martin Roth, Sergii Dmytruk. Hello build bot (Jenkins), Tarun Tuli, Michał Żygowski, Maciej Pijanowski, Jason Nien, Subrata Banik, Kapil Porwal, Christian Walter, Tim Wawrzynczak, Nick Vaccaro, Martin Roth, Krystian Hebel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68746 to look at the new patch set (#6). Change subject: security/tpm: make log format configurable via Kconfig ...................................................................... security/tpm: make log format configurable via Kconfig This commit doesn't add any new format options, just makes selecting existing format explicit. Ticket: https://ticket.coreboot.org/issues/422 Change-Id: I3903aff54e01093bc9ea75862bbf5989cc6e6c55 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/security/tpm/Kconfig M src/security/tpm/Makefile.inc M src/security/tpm/tspi.h M src/security/tpm/tspi/crtm.h 4 files changed, 46 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/68746/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/68746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3903aff54e01093bc9ea75862bbf5989cc6e6c55 Gerrit-Change-Number: 68746 Gerrit-PatchSet: 6 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/nissa/pujjo: Modify touch screen hid to ELAN901C
by Reka Norman (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Tarun Tuli, Kangheui Won, Shou-Chieh Hsu, Leo Chou. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69430 ) Change subject: mb/google/nissa/pujjo: Modify touch screen hid to ELAN901C ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3b374de8cba2125c478814a1890a4b6831715b9 Gerrit-Change-Number: 69430 Gerrit-PatchSet: 2 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jynn Chen <jynn.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin3 Yang <Kevin3.Yang(a)lcfuturecenter.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 22:04:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: aopen/dxplplusu: Add early GPIO settings
by Kyösti Mälkki (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Paul Menzel, Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52815 ) Change subject: aopen/dxplplusu: Add early GPIO settings ...................................................................... Patch Set 4: (1 comment) File src/mainboard/aopen/dxplplusu/bootblock.c: https://review.coreboot.org/c/coreboot/+/52815/comment/200f5d05_bfbd9e95 PS1, Line 100: gpio_write(0x47, 0x86); /* LED1 invert open-drain*/ > Nit: Could you please add a space before `*/`? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579 Gerrit-Change-Number: 52815 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 10 Nov 2022 21:56:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: sb/intel/i82801dx: Clean up includes
by Kyösti Mälkki (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Elyes Haouas. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69440 ) Change subject: sb/intel/i82801dx: Clean up includes ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8bfafe9b359856ccfb11a70ab5a6c1ffd453c54 Gerrit-Change-Number: 69440 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 10 Nov 2022 21:43:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/morgana/Kconfig: Remove TODO after review
by Felix Held (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69275 ) Change subject: soc/amd/morgana/Kconfig: Remove TODO after review ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/morgana/Kconfig: https://review.coreboot.org/c/coreboot/+/69275/comment/f14744d3_673417da PS2, Line 72: select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ # TODO: Check if this is still correct i'd prefer to select this new kconfig option in a separate patch. if you want to keep it in this patch, please mention it in the commit message -- To view, visit https://review.coreboot.org/c/coreboot/+/69275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I598daf40a774ec81a956ce8c1aeb1cbbf4b475f3 Gerrit-Change-Number: 69275 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 10 Nov 2022 21:35:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to device...
by Felix Held (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Arthur Heymans. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69301 ) Change subject: soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetree ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77a333827552741453d8b575f2a8009b3e1bf8f1 Gerrit-Change-Number: 69301 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 10 Nov 2022 21:32:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: /: Remove "ERROR: "/"WARNING: " prefixes from log messages
by Felix Held (Code Review) 10 Nov '22

10 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69405 ) Change subject: /: Remove "ERROR: "/"WARNING: " prefixes from log messages ...................................................................... /: Remove "ERROR: "/"WARNING: " prefixes from log messages It is no longer necessary to explicitly add "ERROR: "/"WARNING: " in front of every BIOS_ERR/BIOS_WARN message. Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69405 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/commonlib/fsp_relocate.c M src/device/pci_device.c M src/soc/amd/glinda/i2c.c M src/soc/amd/glinda/psp_verstage/chipset.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/glinda/smihandler.c M src/soc/amd/mendocino/i2c.c M src/soc/amd/mendocino/psp_verstage/chipset.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/mendocino/smihandler.c M src/soc/amd/morgana/i2c.c M src/soc/amd/morgana/psp_verstage/chipset.c M src/soc/amd/morgana/root_complex.c M src/soc/amd/morgana/smihandler.c M src/soc/qualcomm/sc7280/display/edp_aux.c M src/soc/qualcomm/sc7280/display/edp_ctrl.c 16 files changed, 49 insertions(+), 32 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c index 8dabad5..55295ca 100644 --- a/src/commonlib/fsp_relocate.c +++ b/src/commonlib/fsp_relocate.c @@ -259,10 +259,10 @@ write_le32(&pe_base[aoff], val + delta); break; case EFI_IMAGE_REL_BASED_DIR64: - printk(BIOS_ERR, "Error: Unsupported DIR64\n"); + printk(BIOS_ERR, "Unsupported DIR64\n"); break; default: - printk(BIOS_ERR, "Error: Unsupported relocation type %d\n", + printk(BIOS_ERR, "Unsupported relocation type %d\n", rtype); return -1; } diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 70af9c5..16c31ea 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -408,7 +408,7 @@ int max_requested_bits = __fls64(size_mask); if (max_requested_bits > CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS) { - printk(BIOS_WARNING, "WARNING: Device %s requests a BAR with" + printk(BIOS_WARNING, "Device %s requests a BAR with" " %u bits of address space, which coreboot is not" " configured to hand out, truncating to %u bits\n", dev_path(dev), max_requested_bits, @@ -417,7 +417,7 @@ } if (!(res->flags & IORESOURCE_PCI64) && max_requested_bits > 32) { - printk(BIOS_ERR, "ERROR: Resizable BAR requested" + printk(BIOS_ERR, "Resizable BAR requested" " above 32 bits, but PCI function reported a" " 32-bit BAR."); return; diff --git a/src/soc/amd/glinda/i2c.c b/src/soc/amd/glinda/i2c.c index 97b982b..bd3d4dc 100644 --- a/src/soc/amd/glinda/i2c.c +++ b/src/soc/amd/glinda/i2c.c @@ -34,7 +34,7 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar) { if (bus >= ARRAY_SIZE(i2c_ctrlr)) { - printk(BIOS_ERR, "Error: i2c index out of bounds: %u.", bus); + printk(BIOS_ERR, "i2c index out of bounds: %u.", bus); return; } diff --git a/src/soc/amd/glinda/psp_verstage/chipset.c b/src/soc/amd/glinda/psp_verstage/chipset.c index 2366909..b266fc2 100644 --- a/src/soc/amd/glinda/psp_verstage/chipset.c +++ b/src/soc/amd/glinda/psp_verstage/chipset.c @@ -24,7 +24,7 @@ uint32_t len; if (!spi_ptr) { - printk(BIOS_ERR, "Error: AMD Firmware hash table %s not found\n", fname); + printk(BIOS_ERR, "AMD Firmware hash table %s not found\n", fname); /* * If we don't supply hash table, the PSP will refuse to boot. * So returning here is safe to do. @@ -36,7 +36,7 @@ if (hash_table.no_of_entries_256 > MAX_NUM_HASH_ENTRIES || hash_table.no_of_entries_384 > MAX_NUM_HASH_ENTRIES) { - printk(BIOS_ERR, "Error: Too many entries in AMD Firmware hash table" + printk(BIOS_ERR, "Too many entries in AMD Firmware hash table" " (SHA256:%d, SHA384:%d)\n", hash_table.no_of_entries_256, hash_table.no_of_entries_384); return; @@ -44,7 +44,7 @@ if (hash_table.no_of_entries_256 == 0 && hash_table.no_of_entries_384 == 0) { - printk(BIOS_ERR, "Error: No entries in AMD Firmware hash table" + printk(BIOS_ERR, "No entries in AMD Firmware hash table" " (SHA256:%d, SHA384:%d)\n", hash_table.no_of_entries_256, hash_table.no_of_entries_384); return; diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index ef6c630..2a4a547 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -158,7 +158,7 @@ mmconf_resource(dev, idx++); if (!hob) { - printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n", + printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", __func__); return; } @@ -180,7 +180,7 @@ else if (res->type == EFI_RESOURCE_MEMORY_RESERVED) reserved_ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB); else - printk(BIOS_ERR, "Error: failed to set resources for type %d\n", + printk(BIOS_ERR, "Failed to set resources for type %d\n", res->type); } diff --git a/src/soc/amd/glinda/smihandler.c b/src/soc/amd/glinda/smihandler.c index 95d12bf..9cc34b5 100644 --- a/src/soc/amd/glinda/smihandler.c +++ b/src/soc/amd/glinda/smihandler.c @@ -100,7 +100,7 @@ psp_notify_sx_info(ACPI_S3); smu_sx_entry(); /* Leave SlpTypeEn clear, SMU will set */ - printk(BIOS_ERR, "Error: System did not go to sleep\n"); + printk(BIOS_ERR, "System did not go to sleep\n"); hlt(); } } diff --git a/src/soc/amd/mendocino/i2c.c b/src/soc/amd/mendocino/i2c.c index 75efe0c..92e46b9 100644 --- a/src/soc/amd/mendocino/i2c.c +++ b/src/soc/amd/mendocino/i2c.c @@ -32,7 +32,7 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar) { if (bus >= ARRAY_SIZE(i2c_ctrlr)) { - printk(BIOS_ERR, "Error: i2c index out of bounds: %u.", bus); + printk(BIOS_ERR, "i2c index out of bounds: %u.", bus); return; } diff --git a/src/soc/amd/mendocino/psp_verstage/chipset.c b/src/soc/amd/mendocino/psp_verstage/chipset.c index b896279..fe79979 100644 --- a/src/soc/amd/mendocino/psp_verstage/chipset.c +++ b/src/soc/amd/mendocino/psp_verstage/chipset.c @@ -24,7 +24,7 @@ uint32_t len; if (!spi_ptr) { - printk(BIOS_ERR, "Error: AMD Firmware hash table %s not found\n", fname); + printk(BIOS_ERR, "AMD Firmware hash table %s not found\n", fname); /* * If we don't supply hash table, the PSP will refuse to boot. * So returning here is safe to do. @@ -36,7 +36,7 @@ if (hash_table.no_of_entries_256 > MAX_NUM_HASH_ENTRIES || hash_table.no_of_entries_384 > MAX_NUM_HASH_ENTRIES) { - printk(BIOS_ERR, "Error: Too many entries in AMD Firmware hash table" + printk(BIOS_ERR, "Too many entries in AMD Firmware hash table" " (SHA256:%d, SHA384:%d)\n", hash_table.no_of_entries_256, hash_table.no_of_entries_384); return; @@ -44,7 +44,7 @@ if (hash_table.no_of_entries_256 == 0 && hash_table.no_of_entries_384 == 0) { - printk(BIOS_ERR, "Error: No entries in AMD Firmware hash table" + printk(BIOS_ERR, "No entries in AMD Firmware hash table" " (SHA256:%d, SHA384:%d)\n", hash_table.no_of_entries_256, hash_table.no_of_entries_384); return; diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 6768613..7feb7f7 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -158,7 +158,7 @@ mmconf_resource(dev, idx++); if (!hob) { - printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n", + printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", __func__); return; } @@ -180,7 +180,7 @@ else if (res->type == EFI_RESOURCE_MEMORY_RESERVED) reserved_ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB); else - printk(BIOS_ERR, "Error: failed to set resources for type %d\n", + printk(BIOS_ERR, "Failed to set resources for type %d\n", res->type); } diff --git a/src/soc/amd/mendocino/smihandler.c b/src/soc/amd/mendocino/smihandler.c index c05f3ee..8e32b5d 100644 --- a/src/soc/amd/mendocino/smihandler.c +++ b/src/soc/amd/mendocino/smihandler.c @@ -100,7 +100,7 @@ psp_notify_sx_info(ACPI_S3); smu_sx_entry(); /* Leave SlpTypeEn clear, SMU will set */ - printk(BIOS_ERR, "Error: System did not go to sleep\n"); + printk(BIOS_ERR, "System did not go to sleep\n"); hlt(); } } diff --git a/src/soc/amd/morgana/i2c.c b/src/soc/amd/morgana/i2c.c index 92dd00d..0e416cf 100644 --- a/src/soc/amd/morgana/i2c.c +++ b/src/soc/amd/morgana/i2c.c @@ -32,7 +32,7 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar) { if (bus >= ARRAY_SIZE(i2c_ctrlr)) { - printk(BIOS_ERR, "Error: i2c index out of bounds: %u.", bus); + printk(BIOS_ERR, "i2c index out of bounds: %u.", bus); return; } diff --git a/src/soc/amd/morgana/psp_verstage/chipset.c b/src/soc/amd/morgana/psp_verstage/chipset.c index 539ddb4..2f5fb44 100644 --- a/src/soc/amd/morgana/psp_verstage/chipset.c +++ b/src/soc/amd/morgana/psp_verstage/chipset.c @@ -24,7 +24,7 @@ uint32_t len; if (!spi_ptr) { - printk(BIOS_ERR, "Error: AMD Firmware hash table %s not found\n", fname); + printk(BIOS_ERR, "AMD Firmware hash table %s not found\n", fname); /* * If we don't supply hash table, the PSP will refuse to boot. * So returning here is safe to do. @@ -36,7 +36,7 @@ if (hash_table.no_of_entries_256 > MAX_NUM_HASH_ENTRIES || hash_table.no_of_entries_384 > MAX_NUM_HASH_ENTRIES) { - printk(BIOS_ERR, "Error: Too many entries in AMD Firmware hash table" + printk(BIOS_ERR, "Too many entries in AMD Firmware hash table" " (SHA256:%d, SHA384:%d)\n", hash_table.no_of_entries_256, hash_table.no_of_entries_384); return; @@ -44,7 +44,7 @@ if (hash_table.no_of_entries_256 == 0 && hash_table.no_of_entries_384 == 0) { - printk(BIOS_ERR, "Error: No entries in AMD Firmware hash table" + printk(BIOS_ERR, "No entries in AMD Firmware hash table" " (SHA256:%d, SHA384:%d)\n", hash_table.no_of_entries_256, hash_table.no_of_entries_384); return; diff --git a/src/soc/amd/morgana/root_complex.c b/src/soc/amd/morgana/root_complex.c index 88bcca7..1a4f0bd 100644 --- a/src/soc/amd/morgana/root_complex.c +++ b/src/soc/amd/morgana/root_complex.c @@ -158,7 +158,7 @@ mmconf_resource(dev, idx++); if (!hob) { - printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n", + printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", __func__); return; } @@ -180,7 +180,7 @@ else if (res->type == EFI_RESOURCE_MEMORY_RESERVED) reserved_ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB); else - printk(BIOS_ERR, "Error: failed to set resources for type %d\n", + printk(BIOS_ERR, "Failed to set resources for type %d\n", res->type); } diff --git a/src/soc/amd/morgana/smihandler.c b/src/soc/amd/morgana/smihandler.c index a1eabed..d04f9a3 100644 --- a/src/soc/amd/morgana/smihandler.c +++ b/src/soc/amd/morgana/smihandler.c @@ -100,7 +100,7 @@ psp_notify_sx_info(ACPI_S3); smu_sx_entry(); /* Leave SlpTypeEn clear, SMU will set */ - printk(BIOS_ERR, "Error: System did not go to sleep\n"); + printk(BIOS_ERR, "System did not go to sleep\n"); hlt(); } } diff --git a/src/soc/qualcomm/sc7280/display/edp_aux.c b/src/soc/qualcomm/sc7280/display/edp_aux.c index 4e5f7da..2d2821b 100644 --- a/src/soc/qualcomm/sc7280/display/edp_aux.c +++ b/src/soc/qualcomm/sc7280/display/edp_aux.c @@ -32,13 +32,13 @@ u32 intr_status = 0; if (!wait_ms(100, read32(&edp_auxclk->status) & EDP_AUX_INTERRUPT)) { - printk(BIOS_ERR, "ERROR: AUX SEND not acknowledged\n"); + printk(BIOS_ERR, "AUX SEND not acknowledged\n"); return; } intr_status = read32(&edp_auxclk->status); if (!(intr_status & AUX_INTR_I2C_DONE)) { - printk(BIOS_ERR, "ERROR: AUX command failed, status = %#x\n", intr_status); + printk(BIOS_ERR, "AUX command failed, status = %#x\n", intr_status); return; } @@ -176,7 +176,7 @@ err = edp_aux_transfer(EDID_I2C_ADDR, DP_AUX_I2C_READ, edid, EDID_LENGTH); if (err < EDID_LENGTH) { - printk(BIOS_ERR, "ERROR: Failed to read EDID. :%d\n", err); + printk(BIOS_ERR, "Failed to read EDID. :%d\n", err); return err; } @@ -196,7 +196,7 @@ } if (decode_edid(edid, edid_size, out) != EDID_CONFORMANT) { - printk(BIOS_ERR, "ERROR: Failed to decode EDID.\n"); + printk(BIOS_ERR, "Failed to decode EDID.\n"); return CB_ERR; } diff --git a/src/soc/qualcomm/sc7280/display/edp_ctrl.c b/src/soc/qualcomm/sc7280/display/edp_ctrl.c index e9254cc..1455cac 100644 --- a/src/soc/qualcomm/sc7280/display/edp_ctrl.c +++ b/src/soc/qualcomm/sc7280/display/edp_ctrl.c @@ -1375,7 +1375,7 @@ if (dpcd[DP_DPCD_REV] >= 0x11) { ret = edp_aux_transfer(DP_SET_POWER, DP_AUX_NATIVE_READ, &value, 1); if (ret < 0) { - printk(BIOS_ERR, "ERROR: edp native read failure\n"); + printk(BIOS_ERR, "edp native read failure\n"); return -1; } @@ -1384,7 +1384,7 @@ ret = edp_aux_transfer(DP_SET_POWER, DP_AUX_NATIVE_WRITE, &value, 1); if (ret < 0) { - printk(BIOS_ERR, "ERROR: edp native read failure\n"); + printk(BIOS_ERR, "edp native read failure\n"); return -1; } @@ -1401,7 +1401,7 @@ /* Start link training */ ret = edp_ctrl_training(ctrl, edid, dpcd); if (ret != EDP_TRAIN_SUCCESS) { - printk(BIOS_ERR, "ERROR: edp training failure\n"); + printk(BIOS_ERR, "edp training failure\n"); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/69405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5 Gerrit-Change-Number: 69405 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: cpu/intel/socket_mPGA604: Drop non-working SSE2 disablement
by Kyösti Mälkki (Code Review) 10 Nov '22

10 Nov '22

Attention is currently required from: Paul Menzel. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69443 ) Change subject: cpu/intel/socket_mPGA604: Drop non-working SSE2 disablement ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69443/comment/8fc617df_e161707e PS1, Line 7: implicit SSE/SSE2 > non-working implicit SSE/SSE2 disablement Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d9ac007406a82c498f3ed23568e2ff064504983 Gerrit-Change-Number: 69443 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 10 Nov 2022 21:29:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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