coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: util/xcompile: Fix building for clang + 64bit
by Arthur Heymans (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Martin L Roth, Arthur Heymans. Hello build bot (Jenkins), Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69232 to look at the new patch set (#10). Change subject: util/xcompile: Fix building for clang + 64bit ...................................................................... util/xcompile: Fix building for clang + 64bit -malign-abi does not exist on clang (v15.0.0) and the -ccc-gcc-name variable is not needed anymore. TESTED: This also boots on qemu q35 Change-Id: I7f99ebea18d5c09fdc7ced5c793d57d6fedd2e47 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/xcompile/xcompile 1 file changed, 24 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/69232/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/69232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f99ebea18d5c09fdc7ced5c793d57d6fedd2e47 Gerrit-Change-Number: 69232 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: cpu/x86: Set up cpu_info storage using MSR
by Arthur Heymans (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Raul Rangel. Hello build bot (Jenkins), Marc Jones, Raul Rangel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68913 to look at the new patch set (#7). Change subject: cpu/x86: Set up cpu_info storage using MSR ...................................................................... cpu/x86: Set up cpu_info storage using MSR This MSR is available on all systems supporting long mode. This is needed to run coreboot stages above 4G as gs_base can only be set to 64bit values using the msr. Change-Id: Id38d3c84ef757c0b322ec0d387f57043147cb447 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/cpu.c M src/arch/x86/include/arch/cpu.h M src/include/cpu/x86/msr.h 3 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/68913/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/68913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id38d3c84ef757c0b322ec0d387f57043147cb447 Gerrit-Change-Number: 68913 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: cpu/x86: Set up cpu_info storage using MSR
by Arthur Heymans (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Raul Rangel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68913 ) Change subject: cpu/x86: Set up cpu_info storage using MSR ...................................................................... Patch Set 6: (1 comment) File src/arch/x86/include/arch/cpu.h: https://review.coreboot.org/c/coreboot/+/68913/comment/e5339477_9378c1db PS5, Line 159: msr_t msr = rdmsr(IA32_GS_BASE); : ci = (struct cpu_info *)(uintptr_t)msr.raw; : return ci; > Done Actually this is wrong. That msr returns struct per_cpu_segment_data and not a pointer to cpu_segment_data. -- To view, visit https://review.coreboot.org/c/coreboot/+/68913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id38d3c84ef757c0b322ec0d387f57043147cb447 Gerrit-Change-Number: 68913 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Fri, 11 Nov 2022 14:30:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/x86: Set thread local storage in C code
by Arthur Heymans (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Raul Rangel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69435 ) Change subject: cpu/x86: Set thread local storage in C code ...................................................................... Patch Set 6: (2 comments) File src/arch/x86/cpu.c: https://review.coreboot.org/c/coreboot/+/69435/comment/09360013_192afe60 PS5, Line 346: cpu_info > Can you make this a `struct per_cpu_segment_data` so we keep using the same thing as `cpu_info()`. Done File src/cpu/x86/mp_init.c: https://review.coreboot.org/c/coreboot/+/69435/comment/a87569cf_7f7048c6 PS5, Line 179: static void asmlinkage ap_init(unsigned int index) > > storage class 'asmlinkage' should be located before type 'void' […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19d3285daf97798a2d28408b5601ad991e29e718 Gerrit-Change-Number: 69435 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Fri, 11 Nov 2022 14:20:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/x86: Set up cpu_info storage using MSR
by Arthur Heymans (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Raul Rangel. Hello build bot (Jenkins), Marc Jones, Raul Rangel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68913 to look at the new patch set (#6). Change subject: cpu/x86: Set up cpu_info storage using MSR ...................................................................... cpu/x86: Set up cpu_info storage using MSR This MSR is available on all systems supporting long mode. This is needed to run coreboot stages above 4G as gs_base can only be set to 64bit values using the msr. Change-Id: Id38d3c84ef757c0b322ec0d387f57043147cb447 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/cpu.c M src/arch/x86/include/arch/cpu.h M src/include/cpu/x86/msr.h 3 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/68913/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/68913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id38d3c84ef757c0b322ec0d387f57043147cb447 Gerrit-Change-Number: 68913 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: cpu/x86: Set thread local storage in C code
by Arthur Heymans (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), Raul Rangel, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69435 to look at the new patch set (#6). Change subject: cpu/x86: Set thread local storage in C code ...................................................................... cpu/x86: Set thread local storage in C code Doing this in C code is way easier to understand. Also the thread local storage is now in .bss instead of the AP stack. This makes it more robust against stack overflows, as APs stacks overflow in each other. TESTED: work on qemu. Change-Id: I19d3285daf97798a2d28408b5601ad991e29e718 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/c_start.S M src/arch/x86/cpu.c M src/arch/x86/include/arch/cpu.h D src/cpu/x86/cpu_info.S.inc M src/cpu/x86/mp_init.c M src/cpu/x86/sipi_vector.S 6 files changed, 71 insertions(+), 110 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/69435/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/69435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19d3285daf97798a2d28408b5601ad991e29e718 Gerrit-Change-Number: 69435 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: include/cpu/msr.h: transform into an union
by Arthur Heymans (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Martin Roth, Arthur Heymans. Hello build bot (Jenkins), Martin Roth, Marc Jones, Raul Rangel, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68572 to look at the new patch set (#4). Change subject: include/cpu/msr.h: transform into an union ...................................................................... include/cpu/msr.h: transform into an union This makes it easier to get the content of an msr into a full 64bit variable. Change-Id: I1b026cd3807fd68d805051a74b3d31fcde1c5626 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/mtrr/earlymtrr.c M src/include/cpu/x86/msr.h M src/include/cpu/x86/msr_access.h M src/soc/intel/common/block/sgx/sgx.c 4 files changed, 39 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/68572/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/68572 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b026cd3807fd68d805051a74b3d31fcde1c5626 Gerrit-Change-Number: 68572 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: cpu/x86: Set up cpu_info storage using MSR
by Arthur Heymans (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Raul Rangel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68913 ) Change subject: cpu/x86: Set up cpu_info storage using MSR ...................................................................... Patch Set 5: (2 comments) File src/arch/x86/include/arch/cpu.h: https://review.coreboot.org/c/coreboot/+/68913/comment/a4c3846b_789cb1e9 PS5, Line 156: (cpuid_edx(0x80000001) & (1 << 29)) != 0; > Make this a helper method so you don't need to duplicate it. Done https://review.coreboot.org/c/coreboot/+/68913/comment/3bdf5439_0b1f5758 PS5, Line 159: msr_t msr = rdmsr(IA32_GS_BASE); : ci = (struct cpu_info *)(uintptr_t)msr.raw; : return ci; > ``` […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id38d3c84ef757c0b322ec0d387f57043147cb447 Gerrit-Change-Number: 68913 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Fri, 11 Nov 2022 14:20:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: security/tpm: improve tlcl_extend() signature
by Frans Hendriks (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Erik van den Bogaert, Michał Żygowski, Maciej Pijanowski, Christian Walter, Krystian Hebel, Sergii Dmytruk. Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68745 ) Change subject: security/tpm: improve tlcl_extend() signature ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Patchset: PS5: Verified patch with success on Facebook fbg-1701 -- To view, visit https://review.coreboot.org/c/coreboot/+/68745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I944302b502e3424c5041b17c713a867b0fc535c4 Gerrit-Change-Number: 68745 Gerrit-PatchSet: 5 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Fri, 11 Nov 2022 13:57:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/usb/gadget.c: Add support for EHCI debug using the WCH CH347
by Kyösti Mälkki (Code Review) 11 Nov '22

11 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68264 ) Change subject: drivers/usb/gadget.c: Add support for EHCI debug using the WCH CH347 ...................................................................... drivers/usb/gadget.c: Add support for EHCI debug using the WCH CH347 The WCH CH347 presents a USB CDC serial port on interface 4 while in operating modes 0, 1, and 3. Mode 0 also presents a UART on interface 2 but this is ignored for compatibility with the other modes. Mode 2 uses vendor defined HID usages for communication and is not currently supported. Like the FT232H the data format is hard coded to 8n1. Tested using a CH347 breakout board and a Dell Latitude E6400. Change-Id: Ibd4ad17b7369948003fff7e825b46fe852bc7eb9 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68264 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/usb/Kconfig M src/drivers/usb/gadget.c 2 files changed, 109 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/drivers/usb/Kconfig b/src/drivers/usb/Kconfig index 6854c4a..36fda75 100644 --- a/src/drivers/usb/Kconfig +++ b/src/drivers/usb/Kconfig @@ -92,6 +92,14 @@ Use this with FT232H usb-to-uart. Configuration is hard-coded to use 8n1, no flow control. +config USBDEBUG_DONGLE_WCH_CH347 + bool "WCH CH347 UART" + help + Use this with CH347 usb-to-uart. Configuration is hard-coded + to use 8n1, no flow control. For compatibility across modes + 0, 1, and 3, only UART 1 is supported. The UART in mode 2 is + not currently supported. + endchoice config USBDEBUG_DONGLE_FTDI_FT232H_BAUD @@ -104,6 +112,16 @@ connection works with it. Multiples of 115,200 seem to be a good choice, and EHCI debug usually can't saturate more than 576,000. +config USBDEBUG_DONGLE_WCH_CH347_BAUD + int "WCH CH347 baud rate" + default 115200 + depends on USBDEBUG_DONGLE_WCH_CH347 + help + Select baud rate for CH347 in the range 1200..9,000,000. Make + sure that your receiving side supports the same setting and your + connection works with it. Multiples of 115,200 seem to be a good + choice, and EHCI debug usually can't saturate more than 576,000. + config USBDEBUG_OPTIONAL_HUB_PORT int default 2 if USBDEBUG_DONGLE_BEAGLEBONE diff --git a/src/drivers/usb/gadget.c b/src/drivers/usb/gadget.c index fcb361c..d761447 100644 --- a/src/drivers/usb/gadget.c +++ b/src/drivers/usb/gadget.c @@ -205,6 +205,73 @@ return 0; } +/* Refer to USB CDC PSTN Subclass specification section 6.3 */ +#define CDC_SET_LINE_CODING_REQUEST 0x20 +struct cdc_line_coding { + u32 baudrate; + u8 stop_bits; + u8 parity; + u8 data_bits; +} __packed; + +static int probe_for_ch347(struct ehci_dbg_port *ehci_debug, struct dbgp_pipe *pipe) +{ + int ret; + u8 devnum = 0; + u8 uart_if = 2; /* CH347 UART 1 */ + + /* Move the device to 127 if it isn't already there */ + ret = dbgp_control_msg(ehci_debug, devnum, + USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE, + USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0); + if (ret < 0) { + printk(BIOS_INFO, "Could not move attached device to %d.\n", + USB_DEBUG_DEVNUM); + return -2; + } + devnum = USB_DEBUG_DEVNUM; + printk(BIOS_INFO, "EHCI debug device renamed to %d.\n", devnum); + + /* Send Set Configure request to device. */ + ret = dbgp_control_msg(ehci_debug, devnum, + USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE, + USB_REQ_SET_CONFIGURATION, 1, 0, NULL, 0); + if (ret < 0) { + printk(BIOS_INFO, "CH347 set configuration failed.\n"); + return -2; + } + + struct cdc_line_coding line_coding = { + .baudrate = CONFIG_USBDEBUG_DONGLE_WCH_CH347_BAUD, + .stop_bits = 0, /* 1 stop bit */ + .parity = 0, /* No parity */ + .data_bits = 8 + }; + + ret = dbgp_control_msg(ehci_debug, devnum, + USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE, + CDC_SET_LINE_CODING_REQUEST, 0, uart_if, &line_coding, sizeof(line_coding)); + if (ret < 0) { + printk(BIOS_INFO, "CDC SET_LINE_CODING failed.\n"); + return -3; + } + + /* Modes 0, 1, and 3 all have UART 1 on endpoint 4 in common */ + pipe[DBGP_CONSOLE_EPOUT].endpoint = 0x04; + pipe[DBGP_CONSOLE_EPIN].endpoint = 0x84; + + ack_set_configuration(pipe, devnum, 1000); + + /* Perform a small write. */ + ret = dbgp_bulk_write_x(&pipe[DBGP_CONSOLE_EPOUT], "USB\r\n", 5); + if (ret < 0) { + printk(BIOS_INFO, "dbgp_bulk_write failed: %d\n", ret); + return -4; + } + printk(BIOS_INFO, "Test write done\n"); + return 0; +} + /* FTDI FT232H UART programming. */ #define FTDI_SIO_SET_FLOW_CTRL_REQUEST 0x02 #define FTDI_SIO_SET_BAUDRATE_REQUEST 0x03 @@ -329,6 +396,8 @@ if (CONFIG(USBDEBUG_DONGLE_FTDI_FT232H)) { ret = probe_for_ftdi(ehci_debug, pipe); + } else if (CONFIG(USBDEBUG_DONGLE_WCH_CH347)) { + ret = probe_for_ch347(ehci_debug, pipe); } else { ret = probe_for_debug_descriptor(ehci_debug, pipe); } -- To view, visit https://review.coreboot.org/c/coreboot/+/68264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd4ad17b7369948003fff7e825b46fe852bc7eb9 Gerrit-Change-Number: 68264 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2022