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Hello build bot (Jenkins), Reka Norman, Dinesh Sharma, Kangheui Won, Haribalaraman Ramasubramanian, Haribalaraman Ramasubramanian, Reka Norman, Rizwan Qureshi, Eric Lai, Ronak Kanabar,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69427
to look at the new patch set (#3).
Change subject: drivers/wifi: Fix DSM parsing issue
......................................................................
drivers/wifi: Fix DSM parsing issue
commit b6ebcdfde58a77bea03a67b376401b9f0f3edefb restructured the DSM implementation which resulted in
a regression and DSM values gets filled with junk values.
This CL fixes this issue and passes the right pointer to the dsm
ids structure.
BUG=b:256938177
TEST=Build, boot Nivviks and check if the DSM values are parsed
correctly in the SSDT dump.
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Change-Id: I88782b0b7dde1fca0230472a38628e82dfd9c26c
---
M src/drivers/wifi/generic/acpi.c
1 file changed, 21 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/69427/3
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69201 )
Change subject: device & commonlib: Update pci_scan_bus postcodes
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69201/comment/c8d4248d_7c7277e0
PS2, Line 18: code. Those postcodes should be adjusted to avoid conflicting.
> Everything's actually going to be adjusted in the long run because our current map is all over the p […]
Hmmm, not sure if we have a list of postcodes anywhere other than the commonlib header.
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Change subject: cpu/intel/model_2065x: Don't use a magic APIC
......................................................................
Patch Set 11: Code-Review+1
(1 comment)
File src/cpu/intel/model_2065x/model_2065x_init.c:
https://review.coreboot.org/c/coreboot/+/59315/comment/152033cb_12b2c50f
PS11, Line 25: struct cpu_intel_model_2065x_config *conf = dev->bus->dev->chip_info;
Can any of these dereferences result in undefined behavior? Or are these pointers never NULL?
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Change subject: device & commonlib: Update pci_scan_bus postcodes
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69201/comment/ef17f952_49f556c0
PS2, Line 18: code. Those postcodes should be adjusted to avoid conflicting.
> Could we shift the PCI bus scan postcodes instead?
Everything's actually going to be adjusted in the long run because our current map is all over the place. These are just the first bunch of patches to go in.
But if I weren't adjusting everything, I'd say that it's a bad plan to adjust the core coreboot postcodes that are used on every single platform to make way for the few intel platforms that overlap.
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Change subject: nb/intel/ironlake: Hook up PCI domain and CPU ops to devicetree
......................................................................
Patch Set 9: Code-Review+2
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Change subject: nb/intel/haswell: Hook up PCI domain and CPU cluster ops to devicetree
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
Patchset:
PS3:
> would be good to add a chipset devicetree for haswell so that this doesn't need to be one in each ma […]
Yes, indeed.
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Change subject: cpu/intel/haswell: Move chip_ops to cpu cluster
......................................................................
Patch Set 12: Code-Review+1
(1 comment)
File src/northbridge/intel/haswell/northbridge.c:
https://review.coreboot.org/c/coreboot/+/59314/comment/58dda4c9_dde1750d
PS12, Line 559: struct device_operations haswell_cpu_bus_ops = {
: .read_resources = noop_read_resources,
: .set_resources = noop_set_resources,
: .init = mp_cpu_bus_init,
: .acpi_fill_ssdt = generate_cpu_entries,
: };
Could we move this struct to `cpu/intel/haswell`? It would avoid having two redundant structs (Haswell and Broadwell use `cpu/intel/haswell` code).
We can do this as a follow-up if you prefer.
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Change subject: soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetree
......................................................................
Patch Set 4: Code-Review+2
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Change subject: mb/*: Remove lapic from devicetree
......................................................................
Patch Set 6: Code-Review+1
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