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Kyösti Mälkki has uploaded a new patch set (#7) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/55138 )
Change subject: mb/emulation/qemu-q35: Fix running qemu-i386 with SMM
......................................................................
mb/emulation/qemu-q35: Fix running qemu-i386 with SMM
Depending on whether qemu emulates an amd64 or i386 machine the SMM
save state will differ. The smbase offsets are incompatible between
those save states.
TESTED: Both qemu-system-i386 and qemu-system-x86_64 (v7.0.50) have a
working smihandler, ASEG and TSEG.
Change-Id: Ic6994c8d6e10fd06655129dbd801f1f9d5fd639f
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/emulation/qemu-q35/cpu.c
1 file changed, 55 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/55138/7
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Change subject: cpu/x86/smm/module_loader: Fix ASEG loading
......................................................................
Patch Set 4:
(1 comment)
File src/cpu/x86/smm/smm_module_loader.c:
https://review.coreboot.org/c/coreboot/+/69233/comment/2c5a3a90_29fce207
PS4, Line 444: const size_t fx_save_area_size = CONFIG(SSE) ? FXSAVE_SIZE * params->num_cpus : 0;
We currently have these:
CFLAGS_x86_64 += -march=nocona
CFLAGS_x86_32 += -march=i686
Even if we set SSE=y, x86_32 compiler will not use MMX or XMM registers, and fxsave could be skipped?
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Change subject: cpu/x86: Set up cpu_info storage using MSR
......................................................................
Patch Set 7:
(1 comment)
File src/arch/x86/include/arch/cpu.h:
https://review.coreboot.org/c/coreboot/+/68913/comment/c4d01fb4_e491ba0d
PS5, Line 159: msr_t msr = rdmsr(IA32_GS_BASE);
: ci = (struct cpu_info *)(uintptr_t)msr.raw;
: return ci;
> > Done […]
Oh, I didn't notice you changed the semantics. x86_32 %gs points to `segment_data`, while x86_64 points to `cpu_infos`. Can you leave the semantics how they were so it's not confusing? I think if you leave %gs pointing to `segment_data` you can leave this function unchanged since the `mov %gs:0` should correctly work.
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Change subject: soc/intel/meteorlake: Fix set but unused variable
......................................................................
Patch Set 7: Code-Review+2
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Change subject: cpu/x86: Set thread local storage in C code
......................................................................
Patch Set 6: Code-Review+2
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Change subject: include/cpu/msr.h: transform into an union
......................................................................
Patch Set 4: Code-Review+2
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Change subject: ec/clevo/it5570e: add driver for EC used on various Clevo laptops
......................................................................
Patch Set 12:
(3 comments)
File src/ec/clevo/it5570e/i2ec.h:
https://review.coreboot.org/c/coreboot/+/68791/comment/20890a65_8f02b580
PS4, Line 10: #define D2ADR 0x2e
> Ah, thanks for the explanation. […]
that's what the comment on line 13 tried to do ;) I'll make it clearer
File src/ec/clevo/it5570e/i2ec.c:
https://review.coreboot.org/c/coreboot/+/68791/comment/e0d39857_bf74a960
PS4, Line 11: 0x2e
> OK, so it's not the same thing. It would be best to use the PNP infrastructure, see <device/pnp_ops.h> .
Ah yes, thanks for the hint. I thought PNP ops were not present in bootblock but they are
File src/ec/clevo/it5570e/i2ec.c:
https://review.coreboot.org/c/coreboot/+/68791/comment/88bf5791_594962f6
PS12, Line 17: I2EC_ADDR_H
> "Writing" (won't work because `outb(value, port)` arguments are backwards) 2 times to the same regis […]
good catch. I'm completely confused now... I had tested the backlight effect switch and it worked... but with this code it never could work... need to check my reflog what went wrong and where.... o.O
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69424 )
Change subject: mb/google/brya/var/gladios: use i2c1 for TPM support
......................................................................
mb/google/brya/var/gladios: use i2c1 for TPM support
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the
gladios variant.
BUG=b:239513596
TEST=emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com>
Change-Id: Id6f2bf2a79df883bcb70171051cec4c577ca3bc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69424
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---
M src/mainboard/google/brya/Kconfig
1 file changed, 21 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Eric Lai: Looks good to me, approved
Tarun Tuli: Looks good to me, approved
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index a114860..88202da 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -149,6 +149,7 @@
default 0x0 if BOARD_GOOGLE_YAVIKS
default 0x1 if BOARD_GOOGLE_ZYDRON
default 0x1 if BOARD_GOOGLE_LISBON
+ default 0x1 if BOARD_GOOGLE_GLADIOS
config DRIVER_TPM_I2C_ADDR
hex
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Change subject: security/tpm: resolve conflicts in TSS implementations
......................................................................
Patch Set 4:
(1 comment)
File src/security/tpm/tss/tss.c:
https://review.coreboot.org/c/coreboot/+/69160/comment/3f51cbfe_5c8e569d
PS4, Line 62: die("%s: can't be used with TPM %d\n", __func__, tpm_family);
> nit: not really sure you need these since it shouldn't be possible to get to this place (tlcl_lib_in […]
also, die() here and elsewhere in the file seems inappropriate. This is not a fatal error that would prevent the system from booting, so it shouldn't be treated as such
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Change subject: lib/ramtest.c: Update ram failure post code
......................................................................
Patch Set 1: Code-Review+2
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