coreboot-gerrit November 2022

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[S] Change in coreboot[master]: mb/google/zork: Move PCIe GPIO config from bootblock to romstage
by Martin Roth (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Jason Nien, Matt DeVillier. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69454 ) Change subject: mb/google/zork: Move PCIe GPIO config from bootblock to romstage ...................................................................... Patch Set 2: Code-Review-1 (1 comment) Patchset: PS2: These have been painstakingly configured to allow the correct amount of time for the wifi and wwan devices to be brought up meeting their timing parameters. I don't think moving these just for the sake of moving them is a good idea at all. -- To view, visit https://review.coreboot.org/c/coreboot/+/69454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I609b9a8bd78587b60c0cf1ef14feda88ad3bb4a2 Gerrit-Change-Number: 69454 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 11 Nov 2022 21:39:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/zork: rename baseboard GPIO table getter for clarity
by Martin Roth (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Jason Nien, Matt DeVillier. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69453 ) Change subject: mb/google/zork: rename baseboard GPIO table getter for clarity ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: I love it, but google might be unhappy because it doesn't match the standard way that other chromeos boards work. "Uniformity is more important than clarity." -- To view, visit https://review.coreboot.org/c/coreboot/+/69453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd8ea3446ab7940b21265a3ed8080ba4029c4ff7 Gerrit-Change-Number: 69453 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 11 Nov 2022 21:35:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/zork: Move PCIe GPIO config from bootblock to romstage
by Matt DeVillier (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Jason Nien, Martin Roth. Hello Jason Nien, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69454 to look at the new patch set (#2). Change subject: mb/google/zork: Move PCIe GPIO config from bootblock to romstage ...................................................................... mb/google/zork: Move PCIe GPIO config from bootblock to romstage Aligns with how things done on newer platforms/boards (guybrush/skyrim) and allows for additional GPIO config in romstage (to be implemented in a subsquent patch). No functional impact as the GPIOs only need to be configured prior to FSP-M. Change-Id: I609b9a8bd78587b60c0cf1ef14feda88ad3bb4a2 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/google/zork/bootblock.c M src/mainboard/google/zork/romstage.c 2 files changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/69454/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I609b9a8bd78587b60c0cf1ef14feda88ad3bb4a2 Gerrit-Change-Number: 69454 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/picasso: add mb_pre_fspm() definition and weak implementation
by Martin Roth (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69452 ) Change subject: soc/amd/picasso: add mb_pre_fspm() definition and weak implementation ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia422aaa9e80355f9a9f8f850368441e5c8ff6598 Gerrit-Change-Number: 69452 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 11 Nov 2022 21:32:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/zork: Move PCIe GPIO config from bootblock to romstage
by build bot (Jenkins) (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Jason Nien, Martin Roth. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69454 ) Change subject: mb/google/zork: Move PCIe GPIO config from bootblock to romstage ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163340): https://review.coreboot.org/c/coreboot/+/69454/comment/860d0dd7_ded34c1b PS1, Line 9: Aligns with how things done on newer platforms/boards (eg guybrush, skyrim) Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I609b9a8bd78587b60c0cf1ef14feda88ad3bb4a2 Gerrit-Change-Number: 69454 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 11 Nov 2022 21:28:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/zork: Use detect vs probed flag for touchscreens
by Matt DeVillier (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Jason Nien, Martin Roth. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69457 ) Change subject: mb/google/zork: Use detect vs probed flag for touchscreens ...................................................................... mb/google/zork: Use detect vs probed flag for touchscreens Now that coreboot performs the necessary power sequencing, switch from using the 'probed' flag to 'detect' for all I2C touchscreens. This alleviates ChromeOS from having to probe to see which touchscreen model is actually present, prevents breaking ACPI spec by generating device entries with status 'enabled and present' which aren't actually present, and improves compatibility with upstream Linux and Windows. BUG=b:121309055 TEST=build/boot ChromeOS and Linux on zork, ensure touchscreen is functional, and ACPI device entry generated for correct touchscreen model. This mirrors the changes made for skyrim in CB:67779. Change-Id: Idfe899bd535507c56f0825c6538246441b3b0827 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/google/zork/variants/berknip/overridetree.cb M src/mainboard/google/zork/variants/dalboz/overridetree.cb M src/mainboard/google/zork/variants/dirinboz/overridetree.cb M src/mainboard/google/zork/variants/ezkinil/overridetree.cb M src/mainboard/google/zork/variants/gumboz/overridetree.cb M src/mainboard/google/zork/variants/morphius/overridetree.cb M src/mainboard/google/zork/variants/shuboz/overridetree.cb M src/mainboard/google/zork/variants/trembyle/overridetree.cb M src/mainboard/google/zork/variants/vilboz/overridetree.cb M src/mainboard/google/zork/variants/woomax/overridetree.cb 10 files changed, 45 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/69457/1 diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index 60360ef..702451e 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -143,7 +143,7 @@ chip drivers/i2c/generic register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" - register "probed" = "1" + register "detect" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" register "enable_delay_ms" = "1" @@ -158,7 +158,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "probed" = "1" + register "detect" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" register "enable_delay_ms" = "1" @@ -171,7 +171,7 @@ register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" register "generic.enable_delay_ms" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb index 078fd87..26cd771 100644 --- a/src/mainboard/google/zork/variants/dalboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb @@ -46,7 +46,7 @@ chip drivers/i2c/generic register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" - register "probed" = "1" + register "detect" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" # 32ms: Rise time of the reset line @@ -59,7 +59,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "probed" = "1" + register "detect" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "reset_delay_ms" = "20" @@ -70,7 +70,7 @@ register "generic.hid" = ""SYTS7817"" register "generic.desc" = ""Synaptics Touchscreen"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "generic.reset_delay_ms" = "45" register "generic.has_power_resource" = "1" @@ -82,7 +82,7 @@ register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "generic.reset_delay_ms" = "120" register "generic.reset_off_delay_ms" = "1" diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index 1d66abe..c2a2598 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -206,7 +206,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "probed" = "1" + register "detect" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" register "enable_delay_ms" = "1" @@ -222,7 +222,7 @@ register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" register "generic.enable_delay_ms" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb index c52d52f..120c4ba 100644 --- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -101,7 +101,7 @@ chip drivers/i2c/generic register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" - register "probed" = "1" + register "detect" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" register "enable_delay_ms" = "1" @@ -116,7 +116,7 @@ chip drivers/i2c/hid register "generic.hid" = ""ELAN9004"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" register "generic.enable_delay_ms" = "1" diff --git a/src/mainboard/google/zork/variants/gumboz/overridetree.cb b/src/mainboard/google/zork/variants/gumboz/overridetree.cb index 1d66abe..c2a2598 100644 --- a/src/mainboard/google/zork/variants/gumboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/gumboz/overridetree.cb @@ -206,7 +206,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "probed" = "1" + register "detect" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" register "enable_delay_ms" = "1" @@ -222,7 +222,7 @@ register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" register "generic.enable_delay_ms" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index 6063430..228a906 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -119,7 +119,7 @@ register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" register "generic.enable_delay_ms" = "10" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" diff --git a/src/mainboard/google/zork/variants/shuboz/overridetree.cb b/src/mainboard/google/zork/variants/shuboz/overridetree.cb index 6c7252e..a6c07d4 100644 --- a/src/mainboard/google/zork/variants/shuboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/shuboz/overridetree.cb @@ -143,7 +143,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "probed" = "1" + register "detect" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" register "enable_delay_ms" = "1" diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb index 0bdf5a9..f36a4f0 100644 --- a/src/mainboard/google/zork/variants/trembyle/overridetree.cb +++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb @@ -92,7 +92,7 @@ chip drivers/i2c/generic register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" - register "probed" = "1" + register "detect" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" # 32ms: Rise time of the reset line @@ -107,7 +107,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "probed" = "1" + register "detect" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "reset_delay_ms" = "20" diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index 75df05d..7372ba1 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -234,7 +234,7 @@ register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" register "generic.enable_delay_ms" = "10" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" @@ -250,7 +250,7 @@ chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "probed" = "1" + register "detect" = "1" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" register "enable_delay_ms" = "1" diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb index b7862a5..43c717b 100644 --- a/src/mainboard/google/zork/variants/woomax/overridetree.cb +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -117,7 +117,7 @@ chip drivers/i2c/hid register "generic.hid" = ""ELAN9008"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_90)" register "generic.enable_delay_ms" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/69457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfe899bd535507c56f0825c6538246441b3b0827 Gerrit-Change-Number: 69457 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/zork: Implement touchscreen power sequencing
by Matt DeVillier (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Jason Nien, Martin Roth. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69456 ) Change subject: mb/google/zork: Implement touchscreen power sequencing ...................................................................... mb/google/zork: Implement touchscreen power sequencing As all variants have a touchscreen option, in baseboard tables set the enable GPIO high and hold in reset during romstage, then release reset in ramstage. This will allow the touchscreen to make use of the runtime I2C detect feature (enabled in a subsequent commit) so that an ACPI device entry is created only for the touchscreen actually present. This mirrors the change to skyrim in CB:67778. Change-Id: Ifdd75cd96e7b6880085a3f47214b92948a56aa2e Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 2 files changed, 34 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/69456/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index f2c1a19..b182f41 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -64,7 +64,7 @@ /* EC_AP_INT_ODL (Sensor Framesync) */ PAD_GPI(GPIO_31, PULL_NONE), /* EN_PWR_TOUCHSCREEN */ - PAD_GPO(GPIO_32, LOW), + PAD_GPO(GPIO_32, HIGH), /* GPIO_33 - GPIO_39: Not available */ /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), @@ -148,8 +148,8 @@ PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), /* DEV_BEEP_BCLK */ PAD_GPI(GPIO_139, PULL_NONE), - /* USI_RESET_L */ - PAD_GPO(GPIO_140, LOW), + /* TOUCHSCREEN_RESET_L */ + PAD_GPO(GPIO_140, HIGH), /* USB_HUB_RST_L */ PAD_GPO(GPIO_141, HIGH), /* SD_AUX_RESET_L */ @@ -263,6 +263,11 @@ PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), /* SD_AUX_RESET_L */ PAD_GPO(GPIO_142, HIGH), + /* Enable touchscreen, hold in reset */ + /* EN_PWR_TOUCHSCREEN */ + PAD_GPO(GPIO_32, HIGH), + /* TOUCHSCREEN_RESET_L */ + PAD_GPO(GPIO_140, LOW), }; gpio_configure_pads(romstage_gpio_table, ARRAY_SIZE(romstage_gpio_table)); diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 9864a93..a60eb18 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -108,7 +108,7 @@ /* GPIO_89 - unused */ PAD_NC(GPIO_89), /* EN_PWR_TOUCHSCREEN */ - PAD_GPO(GPIO_90, LOW), + PAD_GPO(GPIO_90, HIGH), /* EN_SPKR */ PAD_GPO(GPIO_91, LOW), /* CLK_REQ0_L - WIFI */ @@ -160,8 +160,8 @@ PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), /* DEV_BEEP_BCLK */ PAD_GPI(GPIO_139, PULL_NONE), - /* USI_RESET_L */ - PAD_GPO(GPIO_140, LOW), + /* TOUCHSCREEN_RESET_L */ + PAD_GPO(GPIO_140, HIGH), /* UART1_RXD - FPMCU */ PAD_NF(GPIO_141, UART1_RXD, PULL_NONE), /* SD_AUX_RESET_L */ @@ -271,6 +271,11 @@ PAD_NF(GPIO_132, CLK_REQ4_L, PULL_NONE), /* SD_AUX_RESET_L */ PAD_GPO(GPIO_142, HIGH), + /* Enable touchscreen, hold in reset */ + /* EN_PWR_TOUCHSCREEN */ + PAD_GPO(GPIO_90, HIGH), + /* TOUCHSCREEN_RESET_L */ + PAD_GPO(GPIO_140, LOW), }; gpio_configure_pads(romstage_gpio_table, ARRAY_SIZE(romstage_gpio_table)); -- To view, visit https://review.coreboot.org/c/coreboot/+/69456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdd75cd96e7b6880085a3f47214b92948a56aa2e Gerrit-Change-Number: 69456 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/zork: Rename pcie_gpio_table to romstage_gpio_table
by Matt DeVillier (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Jason Nien, Martin Roth. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69455 ) Change subject: mb/google/zork: Rename pcie_gpio_table to romstage_gpio_table ...................................................................... mb/google/zork: Rename pcie_gpio_table to romstage_gpio_table Rename so table more indicative of when GPIOs are set, and so it can be used for more than just setting PCIe GPIOs. Will be used to set touchscreen GPIOs as part of power sequencing in a subsequent commit. Rename getter functions to match. This mirrors the changes made for skyrim in CB:67810 Change-Id: Ib1bfd9a12e0a8cb91fa928b7f93b87567314849d Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/google/zork/romstage.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h 4 files changed, 27 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/69455/1 diff --git a/src/mainboard/google/zork/romstage.c b/src/mainboard/google/zork/romstage.c index dc35a05..a9fcb4e 100644 --- a/src/mainboard/google/zork/romstage.c +++ b/src/mainboard/google/zork/romstage.c @@ -13,5 +13,5 @@ void mb_pre_fspm(void) { - baseboard_pcie_gpio_configure(); + baseboard_romstage_gpio_configure(); } diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 70e456c..f2c1a19 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -248,9 +248,9 @@ gpio_set(GPIO_42, 1); } -void baseboard_pcie_gpio_configure(void) +void baseboard_romstage_gpio_configure(void) { - static const struct soc_amd_gpio pcie_gpio_table[] = { + static const struct soc_amd_gpio romstage_gpio_table[] = { /* PCIE_RST1_L - Variable timings (May remove) */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* NVME_AUX_RESET_L */ @@ -265,7 +265,7 @@ PAD_GPO(GPIO_142, HIGH), }; - gpio_configure_pads(pcie_gpio_table, ARRAY_SIZE(pcie_gpio_table)); + gpio_configure_pads(romstage_gpio_table, ARRAY_SIZE(romstage_gpio_table)); /* Deassert PCIE_RST1_L */ gpio_set(GPIO_27, 1); diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 455684e..9864a93 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -258,9 +258,9 @@ gpio_set(GPIO_42, 1); } -void baseboard_pcie_gpio_configure(void) +void baseboard_romstage_gpio_configure(void) { - static const struct soc_amd_gpio pcie_gpio_table[] = { + static const struct soc_amd_gpio romstage_gpio_table[] = { /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), /* CLK_REQ0_L - WIFI */ @@ -273,7 +273,7 @@ PAD_GPO(GPIO_142, HIGH), }; - gpio_configure_pads(pcie_gpio_table, ARRAY_SIZE(pcie_gpio_table)); + gpio_configure_pads(romstage_gpio_table, ARRAY_SIZE(romstage_gpio_table)); if (variant_uses_v3_schematics()) wifi_power_reset_configure_v3(); diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index c76ca02..b44cd65 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -47,8 +47,8 @@ void variant_bluetooth_update(void); /* Update touchscreen configuration in devicetree during ramstage. */ void variant_touchscreen_update(void); -/* Configure PCIe GPIOs as per baseboard sequencing requirements. */ -void baseboard_pcie_gpio_configure(void); +/* Configure romstage GPIOs as per baseboard sequencing requirements. */ +void baseboard_romstage_gpio_configure(void); /* Per variant FSP-S initialization, default implementation in baseboard and * overridable by the variant. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1bfd9a12e0a8cb91fa928b7f93b87567314849d Gerrit-Change-Number: 69455 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/zork: Move PCIe GPIO config from bootblock to romstage
by Matt DeVillier (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Jason Nien, Martin Roth. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69454 ) Change subject: mb/google/zork: Move PCIe GPIO config from bootblock to romstage ...................................................................... mb/google/zork: Move PCIe GPIO config from bootblock to romstage Aligns with how things done on newer platforms/boards (eg guybrush, skyrim) and allows for additional GPIO config in romstage (to be implemented in a subsquent patch). No functional impact as the GPIOs only need to be configured prior to FSP-M. Change-Id: I609b9a8bd78587b60c0cf1ef14feda88ad3bb4a2 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/google/zork/bootblock.c M src/mainboard/google/zork/romstage.c 2 files changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/69454/1 diff --git a/src/mainboard/google/zork/bootblock.c b/src/mainboard/google/zork/bootblock.c index 022a5e0..6009308 100644 --- a/src/mainboard/google/zork/bootblock.c +++ b/src/mainboard/google/zork/bootblock.c @@ -11,6 +11,4 @@ gpios = variant_bootblock_gpio_table(&num_gpios, acpi_get_sleep_type()); gpio_configure_pads(gpios, num_gpios); - - baseboard_pcie_gpio_configure(); } diff --git a/src/mainboard/google/zork/romstage.c b/src/mainboard/google/zork/romstage.c index f72789a..dc35a05 100644 --- a/src/mainboard/google/zork/romstage.c +++ b/src/mainboard/google/zork/romstage.c @@ -2,6 +2,7 @@ #include <baseboard/variants.h> #include <soc/fsp.h> +#include <soc/platform_descriptors.h> void __weak variant_updm_update(FSP_M_CONFIG *mcfg) {} @@ -9,3 +10,8 @@ { variant_updm_update(mcfg); } + +void mb_pre_fspm(void) +{ + baseboard_pcie_gpio_configure(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/69454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I609b9a8bd78587b60c0cf1ef14feda88ad3bb4a2 Gerrit-Change-Number: 69454 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/zork: rename baseboard GPIO table getter for clarity
by Matt DeVillier (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Jason Nien, Martin Roth. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69453 ) Change subject: mb/google/zork: rename baseboard GPIO table getter for clarity ...................................................................... mb/google/zork: rename baseboard GPIO table getter for clarity Rename variant_pcie_gpio_table() to baseboard_pcie_gpio_table(), since the GPIO table comes from the baseboard (and is not overridden by any variant). Drop the __weak qualifier as this function is not overridden. This is similar to the change made for skyrim in CB:67809 Change-Id: Idd8ea3446ab7940b21265a3ed8080ba4029c4ff7 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/google/zork/bootblock.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h 4 files changed, 23 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/69453/1 diff --git a/src/mainboard/google/zork/bootblock.c b/src/mainboard/google/zork/bootblock.c index 96cbe4d..022a5e0 100644 --- a/src/mainboard/google/zork/bootblock.c +++ b/src/mainboard/google/zork/bootblock.c @@ -12,5 +12,5 @@ gpios = variant_bootblock_gpio_table(&num_gpios, acpi_get_sleep_type()); gpio_configure_pads(gpios, num_gpios); - variant_pcie_gpio_configure(); + baseboard_pcie_gpio_configure(); } diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 6dc3595..70e456c 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -248,7 +248,7 @@ gpio_set(GPIO_42, 1); } -__weak void variant_pcie_gpio_configure(void) +void baseboard_pcie_gpio_configure(void) { static const struct soc_amd_gpio pcie_gpio_table[] = { /* PCIE_RST1_L - Variable timings (May remove) */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 8d264c8..455684e 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -258,7 +258,7 @@ gpio_set(GPIO_42, 1); } -__weak void variant_pcie_gpio_configure(void) +void baseboard_pcie_gpio_configure(void) { static const struct soc_amd_gpio pcie_gpio_table[] = { /* NVME_AUX_RESET_L */ diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 11926d1..c76ca02 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -47,8 +47,8 @@ void variant_bluetooth_update(void); /* Update touchscreen configuration in devicetree during ramstage. */ void variant_touchscreen_update(void); -/* Configure PCIe GPIOs as per variant sequencing requirements. */ -void variant_pcie_gpio_configure(void); +/* Configure PCIe GPIOs as per baseboard sequencing requirements. */ +void baseboard_pcie_gpio_configure(void); /* Per variant FSP-S initialization, default implementation in baseboard and * overridable by the variant. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd8ea3446ab7940b21265a3ed8080ba4029c4ff7 Gerrit-Change-Number: 69453 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2022