coreboot-gerrit November 2022

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[S] Change in coreboot[master]: drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512
by Mario Scheithauer (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Mario Scheithauer, Werner Zeh. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69384 to look at the new patch set (#6). Change subject: drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512 ...................................................................... drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512 This driver enables the usage of an external Marvell PHY 88E1512 which should be connected to a SOC internal MAC controller. In a first step it is only the framework of the driver. Functionality will follow with a second patch. Change-Id: I24011860caa7bb206770f9779eb34b689293db10 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- A src/drivers/phy/m88e1512/Kconfig A src/drivers/phy/m88e1512/Makefile.inc A src/drivers/phy/m88e1512/m88e1512.c 3 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/69384/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/69384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24011860caa7bb206770f9779eb34b689293db10 Gerrit-Change-Number: 69384 Gerrit-PatchSet: 6 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: src/device + util/sconfig: Introduce new device 'mdio'
by Mario Scheithauer (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Mario Scheithauer. Hello build bot (Jenkins), Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69382 to look at the new patch set (#4). Change subject: src/device + util/sconfig: Introduce new device 'mdio' ...................................................................... src/device + util/sconfig: Introduce new device 'mdio' This patch extends the available device paths with a new device 'mdio'. MDIO is the 'Management Data Input/Output' called interface which is used to access an Ethernet PHY behind a MAC to change settings. The real payload data path is not handled by this interface. To address the PHY correctly on the MDIO bus, there is a 5 bit address needed, which often can be configured via pins on the mainboard. Therefore, the new introduced device has an 'addr' field to define its address. If one want to use a MDIO device in devicetree, the syntax is straight forward (example): device mdio 0x2 on end As the MDIO interface is driven by the MAC, most likely this MDIO device will be hooked in as a child device of the (PCI attached) MAC device. With the new introduced ops_mdio a new interface is added to provide an API for read and write access over MDIO. Change-Id: I6691f92c4233bc30afc9029840b06f74bb1eb4b2 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/device/Makefile.inc M src/device/device_const.c M src/device/device_util.c A src/device/mdio.c M src/include/device/device.h A src/include/device/mdio.h M src/include/device/path.h M util/sconfig/lex.yy.c_shipped M util/sconfig/main.c M util/sconfig/sconfig.l M util/sconfig/sconfig.tab.c_shipped M util/sconfig/sconfig.tab.h_shipped M util/sconfig/sconfig.y 13 files changed, 353 insertions(+), 259 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/69382/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6691f92c4233bc30afc9029840b06f74bb1eb4b2 Gerrit-Change-Number: 69382 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Fix set but unused variable
by Arthur Heymans (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Tarun Tuli, Martin L Roth, Subrata Banik, Paul Menzel, Kapil Porwal, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66264 ) Change subject: soc/intel/meteorlake: Fix set but unused variable ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/meteorlake/systemagent.c: https://review.coreboot.org/c/coreboot/+/66264/comment/972850bf_7878a6f3 PS6, Line 86: line > commented Done -- To view, visit https://review.coreboot.org/c/coreboot/+/66264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe1de3057c17b4aa8ecbd87fac598e43294584e3 Gerrit-Change-Number: 66264 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 11 Nov 2022 13:01:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/ironlake: Work around unused variable warning
by Arthur Heymans (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69237 to look at the new patch set (#6). Change subject: nb/intel/ironlake: Work around unused variable warning ...................................................................... nb/intel/ironlake: Work around unused variable warning It's not clear whether this variable should actually be used or not so leave it be with a FIXME comment. Change-Id: I4892600bfec55830acae56d2b293947c2d9ddd07 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/69237/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/69237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4892600bfec55830acae56d2b293947c2d9ddd07 Gerrit-Change-Number: 69237 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Fix set but unused variable
by Arthur Heymans (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Tarun Tuli, Martin L Roth, Subrata Banik, Kapil Porwal, Arthur Heymans, Felix Held. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Paul Menzel, Kapil Porwal, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/66264 to look at the new patch set (#7). Change subject: soc/intel/meteorlake: Fix set but unused variable ...................................................................... soc/intel/meteorlake: Fix set but unused variable Clang complains about this. Change-Id: Ibe1de3057c17b4aa8ecbd87fac598e43294584e3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/meteorlake/systemagent.c 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/66264/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/66264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe1de3057c17b4aa8ecbd87fac598e43294584e3 Gerrit-Change-Number: 66264 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: drivers/ipmi/ocp: Fix building with clang
by Arthur Heymans (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Paul Menzel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69437 ) Change subject: drivers/ipmi/ocp: Fix building with clang ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69437/comment/d18aa20e_dbdd5c90 PS1, Line 7: Fix building with clang > Maybe more specific? Something like: > > > Use explicit comparison in if condition The explanation below captures this. -- To view, visit https://review.coreboot.org/c/coreboot/+/69437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a2f03a0e05088a780ce1e829859421b461032ca Gerrit-Change-Number: 69437 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 11 Nov 2022 13:01:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: aopen/dxplplusu: Add early GPIO settings
by Kyösti Mälkki (Code Review) 11 Nov '22

11 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52815 ) Change subject: aopen/dxplplusu: Add early GPIO settings ...................................................................... aopen/dxplplusu: Add early GPIO settings Required for 2nd COM port to work. Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52815 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/aopen/dxplplusu/bootblock.c M src/mainboard/aopen/dxplplusu/devicetree.cb M src/southbridge/intel/i82801dx/i82801dx.h 3 files changed, 126 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/aopen/dxplplusu/bootblock.c b/src/mainboard/aopen/dxplplusu/bootblock.c index 5a969cf..93662a2 100644 --- a/src/mainboard/aopen/dxplplusu/bootblock.c +++ b/src/mainboard/aopen/dxplplusu/bootblock.c @@ -1,12 +1,120 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <bootblock_common.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <device/pnp.h> +#include <southbridge/intel/i82801dx/i82801dx.h> #include <superio/smsc/lpc47m10x/lpc47m10x.h> #define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) +#define GPIO_DEV PNP_DEV(0x2e, LPC47M10X2_PME) +#define PME_BASE 0xe00 + +/* + * JP3 + * 1-2 0:1f.0 0xd4 GEN_STA SAFE_MODE = 0 + * 2-3 0:1f.0 0xd4 GEN_STA SAFE_MODE = 1 + */ + +static void enable_gpio(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + + /* These should go under sb/. */ + pci_write_config8(dev, COM_DEC, 0x10); + pci_write_config16(dev, LPC_EN, 0x300F); + + pnp_enter_conf_state(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + pnp_set_enable(GPIO_DEV, 0); + pnp_set_iobase(GPIO_DEV, PNP_IDX_IO0, PME_BASE); + pnp_set_enable(GPIO_DEV, 1); + pnp_exit_conf_state(GPIO_DEV); + + pci_write_config16(dev, GEN1_DEC, PME_BASE | 0x01); +} + +static void gpio_write(u8 addr, u8 val) +{ + outb(val, PME_BASE + addr); +} + +static void gpio_read_write(u8 addr, u8 amask, u8 omask) +{ + u8 val = inb(PME_BASE + addr); + val &= amask; + val |= omask; + outb(val, PME_BASE + addr); +} + +static void configure_gpios(void) +{ + /* GP10-17 */ + gpio_write(0x23, 0x00); /* push-pull output */ + gpio_write(0x24, 0x81); /* open-drain but input ? */ + gpio_write(0x25, 0x01); + gpio_write(0x26, 0x01); + gpio_write(0x27, 0x01); + gpio_write(0x28, 0x01); + gpio_write(0x29, 0x01); + gpio_write(0x2a, 0x00); /* push-pull output */ + + /* GP20-27 */ + gpio_write(0x2b, 0x01); + gpio_write(0x2c, 0x0c); /* nDS1 floppy select */ + gpio_write(0x2d, 0x00); /* push-pull output */ + gpio_write(0x2f, 0x01); + gpio_write(0x30, 0x01); + gpio_write(0x31, 0x01); + gpio_write(0x32, 0x04); /* nIO_SMI */ + + /* GP30-37 */ + gpio_write(0x33, 0x04); /* FAN_TACH2 */ + gpio_write(0x34, 0x01); + gpio_write(0x35, 0x01); + gpio_write(0x36, 0x01); + gpio_write(0x37, 0x01); + gpio_write(0x38, 0x01); + gpio_write(0x39, 0x04); /* nKBDRESET */ + gpio_write(0x3a, 0x04); /* A20M */ + + /* GP40-43 */ + gpio_write(0x3b, 0x84); /* DRVDEN0 open-drain */ + gpio_write(0x3c, 0x04); /* DRVDEN1 push/pull */ + gpio_write(0x3d, 0x84); /* nIO_PME open-drain */ + gpio_write(0x3e, 0x01); + + /* GP50-GP57 to UART signals */ + gpio_write(0x3f, 0x05); + gpio_write(0x40, 0x05); + gpio_write(0x41, 0x05); + gpio_write(0x42, 0x04); + gpio_write(0x43, 0x05); + gpio_write(0x44, 0x04); + gpio_write(0x45, 0x05); + gpio_write(0x46, 0x04); + + /* GP60-GP61 */ + gpio_write(0x47, 0x86); /* LED1 invert open-drain */ + gpio_write(0x48, 0x81); /* open-drain but input */ + + /* Set initial output bits */ + gpio_read_write(0x4b, 0xff, 0x81); /* GP1 */ + gpio_read_write(0x4c, ~0x01, 0x00); /* GP2 */ + gpio_read_write(0x4d, 0xff, 0x80); /* GP3 */ + gpio_read_write(0x4e, ~0x08, 0x00); /* GP4 */ + + /* LED1 off */ + gpio_write(0x5d, 0x00); +} void bootblock_mainboard_early_init(void) { + enable_gpio(); + configure_gpios(); + /* Get the serial port configured. */ lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/aopen/dxplplusu/devicetree.cb b/src/mainboard/aopen/dxplplusu/devicetree.cb index 4f3102d..2dfa03d 100644 --- a/src/mainboard/aopen/dxplplusu/devicetree.cb +++ b/src/mainboard/aopen/dxplplusu/devicetree.cb @@ -41,7 +41,7 @@ io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.5 off # Com2 + device pnp 2e.5 on # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index e63327c..c07e581 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -71,6 +71,7 @@ #define PIRQG_ROUT 0x6A #define PIRQH_ROUT 0x6B #define COM_DEC 0xE0 +#define GEN1_DEC 0xE4 #define LPC_EN 0xE6 #define FUNC_DIS 0xF2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579 Gerrit-Change-Number: 52815 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: util/cbfstool: Add a new mechanism to provide a memory mapped
by build bot (Jenkins) (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Nico Huber, Maximilian Brune, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68160 ) Change subject: util/cbfstool: Add a new mechanism to provide a memory mapped ...................................................................... Patch Set 6: (5 comments) File util/cbfstool/cbfstool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163294): https://review.coreboot.org/c/coreboot/+/68160/comment/dd3a56d4_45d5bd82 PS6, Line 395: * Default decode window lives just below 4G boundary in host space and maps up to a line length of 100 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163294): https://review.coreboot.org/c/coreboot/+/68160/comment/386faebd_f9d19b5e PS6, Line 396: * maximum of 16MiB. If the window is smaller than 16MiB, the SPI flash window is mapped line length of 104 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163294): https://review.coreboot.org/c/coreboot/+/68160/comment/13bfe989_8a345e95 PS6, Line 399: add_mmap_window(std_window_flash_offset, DEFAULT_DECODE_WINDOW_TOP - std_window_size, std_window_size); line length of 119 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163294): https://review.coreboot.org/c/coreboot/+/68160/comment/a6e8a778_5b75110c PS6, Line 408: ERROR("Flash space windows (base=0x%zx, limit=0x%zx) and (base=0x%zx, limit=0x%zx) overlap!\n", line length of 135 exceeds 96 columns Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163294): https://review.coreboot.org/c/coreboot/+/68160/comment/43f36d16_41b563c9 PS6, Line 418: ERROR("Host space windows (base=0x%zx, limit=0x%zx) and (base=0x%zx, limit=0x%zx) overlap!\n", line length of 134 exceeds 96 columns -- To view, visit https://review.coreboot.org/c/coreboot/+/68160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38ab4c369704497f711e14ecda3ff3a8cdc0d089 Gerrit-Change-Number: 68160 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 11 Nov 2022 12:32:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/cbfstool: Add a new mechanism to provide a memory mapped
by Arthur Heymans (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Nico Huber, Maximilian Brune, Julius Werner. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68160 ) Change subject: util/cbfstool: Add a new mechanism to provide a memory mapped ...................................................................... Patch Set 4: (3 comments) File src/soc/intel/common/block/fast_spi/Makefile.inc: https://review.coreboot.org/c/coreboot/+/68160/comment/19c41f48_c8301769 PS4, Line 91: FLASH_BIOS_BASE > If anything I would use your first suggestion. […] Done https://review.coreboot.org/c/coreboot/+/68160/comment/5557957b_333933fa PS4, Line 93: $(call int-subtract, $(CONFIG_ROM_SIZE) 0x1000000)) > EXT_BIOS_SIZE Done File util/cbfstool/cbfstool.c: https://review.coreboot.org/c/coreboot/+/68160/comment/37cb39a1_6e2eb5ad PS3, Line 358: optarg); > Note that this will no longer print the full argument because strtok() cuts it into pieces in-place. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/68160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38ab4c369704497f711e14ecda3ff3a8cdc0d089 Gerrit-Change-Number: 68160 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 11 Nov 2022 12:32:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/cbfstool: Add a new mechanism to provide a memory mapped
by Arthur Heymans (Code Review) 11 Nov '22

11 Nov '22

Attention is currently required from: Nico Huber, Julius Werner, Arthur Heymans. Hello build bot (Jenkins), Nico Huber, Julius Werner, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68160 to look at the new patch set (#6). Change subject: util/cbfstool: Add a new mechanism to provide a memory mapped ...................................................................... util/cbfstool: Add a new mechanism to provide a memory mapped This replaces the mechanism with --ext-win-base --ext-win-size with a more generic mechanism where cbfstool can be provided with an arbitrary memory map. This will be useful for AMD platforms with flash sizes larger than 16M where only the lower 16M half gets memory mapped below 4G. Also on Intel system the IFD allows for a memory map where the "top of flash" != "below 4G". This is for instance the case by default on Intel APL. TEST: google/brya build for chromeos which used --ext-win-base remains the same after this change with BUILD_TIMELESS=1. Change-Id: I38ab4c369704497f711e14ecda3ff3a8cdc0d089 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/fast_spi/Makefile.inc M util/cbfstool/cbfstool.c 2 files changed, 147 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/68160/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/68160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38ab4c369704497f711e14ecda3ff3a8cdc0d089 Gerrit-Change-Number: 68160 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2022