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Change subject: util/cbfstool: Add a new mechanism to provide a memory mapped
......................................................................
Patch Set 5:
(5 comments)
File util/cbfstool/cbfstool.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163293):
https://review.coreboot.org/c/coreboot/+/68160/comment/1c8df4c3_a4439eeb
PS5, Line 395: * Default decode window lives just below 4G boundary in host space and maps up to a
line length of 100 exceeds 96 columns
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163293):
https://review.coreboot.org/c/coreboot/+/68160/comment/ce9a36b1_16b6d15f
PS5, Line 396: * maximum of 16MiB. If the window is smaller than 16MiB, the SPI flash window is mapped
line length of 104 exceeds 96 columns
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163293):
https://review.coreboot.org/c/coreboot/+/68160/comment/7cdebb3b_ea51d007
PS5, Line 399: add_mmap_window(std_window_flash_offset, DEFAULT_DECODE_WINDOW_TOP - std_window_size, std_window_size);
line length of 119 exceeds 96 columns
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163293):
https://review.coreboot.org/c/coreboot/+/68160/comment/de106692_c8853f9b
PS5, Line 408: ERROR("Flash space windows (base=0x%zx, limit=0x%zx) and (base=0x%zx, limit=0x%zx) overlap!\n",
line length of 135 exceeds 96 columns
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163293):
https://review.coreboot.org/c/coreboot/+/68160/comment/b08c66d1_d1717f1f
PS5, Line 418: ERROR("Host space windows (base=0x%zx, limit=0x%zx) and (base=0x%zx, limit=0x%zx) overlap!\n",
line length of 134 exceeds 96 columns
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Hello build bot (Jenkins), Nico Huber, Julius Werner, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68160
to look at the new patch set (#5).
Change subject: util/cbfstool: Add a new mechanism to provide a memory mapped
......................................................................
util/cbfstool: Add a new mechanism to provide a memory mapped
This replaces the mechanism with --ext-win-base --ext-win-size with a
more generic mechanism where cbfstool can be provided with an arbitrary
memory map.
This will be useful for AMD platforms with flash sizes larger than 16M
where only the lower 16M half gets memory mapped below 4G. Also on Intel
system the IFD allows for a memory map where the "top of flash" !=
"below 4G". This is for instance the case by default on Intel APL.
TEST: google/brya build for chromeos which used --ext-win-base remains
the same after this change with BUILD_TIMELESS=1.
Change-Id: I38ab4c369704497f711e14ecda3ff3a8cdc0d089
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/common/block/fast_spi/Makefile.inc
M util/cbfstool/cbfstool.c
2 files changed, 147 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/68160/5
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Change subject: cpu/intel/socket_*: Clean up Kconfig files
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> For instruction set extensions like SSE, should we have a `default y` […]
Would be a good idea, especially if the extensions are supported on most platforms.
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Change subject: cpu/intel/socket_*: Clean up Kconfig files
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
For instruction set extensions like SSE, should we have a `default y`
in the sockets and a potential `default n` opt-out for the CPUs that
don't support it? That is, if we have sockets that support CPUs with
and without an extension.
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Change subject: soc/intel/meteorlake: Fix set but unused variable
......................................................................
Patch Set 6: Code-Review+2
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Change subject: nb/intel/ironlake: Remove set but unused variable
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS2:
> > Looks like a bug somewhere... […]
Let's keep the code, but mark the variable as unused and add a FIXME. WDYT?
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Change subject: cpu/x86: Set thread local storage in C code
......................................................................
Patch Set 5: Code-Review+1
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Change subject: include/cpu/msr.h: transform into an union
......................................................................
Patch Set 3: Code-Review+2
(2 comments)
File src/include/cpu/x86/msr_access.h:
https://review.coreboot.org/c/coreboot/+/68572/comment/2d66d491_093917ce
PS3, Line 10: struct {
: unsigned int lo;
: unsigned int hi;
: };
: uint64_t raw;
> lol, touche!
Don't worry, had the same question over here before remembering the portability of MSRs 😄
File src/soc/intel/common/block/sgx/sgx.c:
https://review.coreboot.org/c/coreboot/+/68572/comment/3f23409c_08fd0077
PS3, Line 81: if ((prmrr_base.hi == 0) && (prmrr_base.lo == 0)
A bunch of these could be cleaned up in follow-ups.
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Change subject: mb/google/brya/var/agah: Add Power Limits for RPL SKU
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Patchset:
PS3:
maybe can check the FSP log with ADL.
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Change subject: mb/emulation/q35: Fix running with qemu-i386 with SMM_TSEG
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