coreboot-gerrit November 2022

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[S] Change in coreboot[master]: mb/starlabs/starbook/kbl: Drop redundant option code
by Angel Pons (Code Review) 13 Nov '22

13 Nov '22

Attention is currently required from: Sean Rhodes. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69522 ) Change subject: mb/starlabs/starbook/kbl: Drop redundant option code ...................................................................... mb/starlabs/starbook/kbl: Drop redundant option code Commit 9bbc039c457774dbeb44ea37ecc6507144d49b61 ("soc/intel/skylake: Hook up FSP hyper-threading setting to option API") already hooks up the `hyper_threading` CMOS option in SoC code, so there's no need to do it from mainboard code. Change-Id: I602452266a8465cced12454f800ea023f382ba6f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/kbl/romstage.c 1 file changed, 15 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/69522/1 diff --git a/src/mainboard/starlabs/starbook/variants/kbl/romstage.c b/src/mainboard/starlabs/starbook/variants/kbl/romstage.c index 098f753..72fe9ed 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/kbl/romstage.c @@ -19,8 +19,4 @@ mem_cfg->MemorySpdPtr00 = spd_cbfs_map(6); mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; - - const uint8_t ht = get_uint_option("hyper_threading", - mupd->FspmConfig.HyperThreading); - mupd->FspmConfig.HyperThreading = ht; } -- To view, visit https://review.coreboot.org/c/coreboot/+/69522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I602452266a8465cced12454f800ea023f382ba6f Gerrit-Change-Number: 69522 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/clevo/cml-u: Fix CMOS options
by Angel Pons (Code Review) 13 Nov '22

13 Nov '22

Attention is currently required from: Felix Singer, Michael Niewöhner. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69521 ) Change subject: mb/clevo/cml-u: Fix CMOS options ...................................................................... mb/clevo/cml-u: Fix CMOS options The `hyper_threading` CMOS option was hooked up to the wrong enumeration and lacked a default value in `cmos.default`. Thus, use the correct enum for the `hyper_threading` option, remove the now-unused "backwards" enum and provide a default value in `cmos.default`. Change-Id: I56b0320f9210cde8ff58db176d2b7d2207c98aa9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/clevo/cml-u/cmos.default M src/mainboard/clevo/cml-u/cmos.layout 2 files changed, 17 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/69521/1 diff --git a/src/mainboard/clevo/cml-u/cmos.default b/src/mainboard/clevo/cml-u/cmos.default index a20f1b1..098bfa6 100644 --- a/src/mainboard/clevo/cml-u/cmos.default +++ b/src/mainboard/clevo/cml-u/cmos.default @@ -1,5 +1,6 @@ boot_option=Fallback debug_level=Debug +hyper_threading=Enable power_on_after_fail=Disable # EC options diff --git a/src/mainboard/clevo/cml-u/cmos.layout b/src/mainboard/clevo/cml-u/cmos.layout index 391deb1..8350704 100644 --- a/src/mainboard/clevo/cml-u/cmos.layout +++ b/src/mainboard/clevo/cml-u/cmos.layout @@ -17,7 +17,7 @@ # ----------------------------------------------------------------- # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 1 hyper_threading # ----------------------------------------------------------------- # coreboot config options: southbridge @@ -52,8 +52,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency -- To view, visit https://review.coreboot.org/c/coreboot/+/69521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56b0320f9210cde8ff58db176d2b7d2207c98aa9 Gerrit-Change-Number: 69521 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/supermicro/x11-lga1151-series: Fix CMOS options
by Angel Pons (Code Review) 13 Nov '22

13 Nov '22

Attention is currently required from: Felix Singer, Angel Pons. Hello Felix Singer, build bot (Jenkins), Sean Rhodes, Arthur Heymans, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69491 to look at the new patch set (#4). Change subject: mb/supermicro/x11-lga1151-series: Fix CMOS options ...................................................................... mb/supermicro/x11-lga1151-series: Fix CMOS options The `hyper_threading` CMOS option was hooked up to the wrong enumeration and lacked a default value in `cmos.default`. Thus, use the correct enum for the `hyper_threading` option, remove the now-unused "backwards" enum and provide a default value in `cmos.default`. Change-Id: I2ee9ced2881ed5e348e84a35e8abd6b7a363d936 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/supermicro/x11-lga1151-series/cmos.default M src/mainboard/supermicro/x11-lga1151-series/cmos.layout 2 files changed, 17 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/69491/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ee9ced2881ed5e348e84a35e8abd6b7a363d936 Gerrit-Change-Number: 69491 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/supermicro/x11-lga1151-series: Fix CMOS options
by Michael Niewöhner (Code Review) 13 Nov '22

13 Nov '22

Attention is currently required from: Felix Singer, Angel Pons. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69491 ) Change subject: mb/supermicro/x11-lga1151-series: Fix CMOS options ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ee9ced2881ed5e348e84a35e8abd6b7a363d936 Gerrit-Change-Number: 69491 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 13 Nov 2022 18:59:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: arch/x86/mpspec.c: Drop weak write_smp_table()
by Kyösti Mälkki (Code Review) 13 Nov '22

13 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69489 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch/x86/mpspec.c: Drop weak write_smp_table() ...................................................................... arch/x86/mpspec.c: Drop weak write_smp_table() Creating MP table is not useful when it does not include the interrupt routing entries. Change-Id: I1f38fb32a9436de64dfaf82e426cbd64b220ffa7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69489 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/mpspec.c 1 file changed, 16 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index 15b64b3..cbf6743 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -507,25 +507,3 @@ mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); } - -unsigned long __weak write_smp_table(unsigned long addr) -{ - struct mp_config_table *mc; - int isa_bus; - void *tmp, *v; - - v = smp_write_floating_table(addr, 0); - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &isa_bus); - - mptable_lintsrc(mc, isa_bus); - tmp = mptable_finalize(mc); - printk(BIOS_INFO, "MPTABLE len: %d\n", (unsigned int)((uintptr_t)tmp - - (uintptr_t)v)); - return (unsigned long)tmp; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/69489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f38fb32a9436de64dfaf82e426cbd64b220ffa7 Gerrit-Change-Number: 69489 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: drivers/generic/ioapic: Drop poor implementation
by Kyösti Mälkki (Code Review) 13 Nov '22

13 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69488 ) Change subject: drivers/generic/ioapic: Drop poor implementation ...................................................................... drivers/generic/ioapic: Drop poor implementation This disables MP table generation for the affected boards since interrupt routing entries would now be completely missing. The mechanism itself is flawed and redundant. The mapping of integrated PCI devices' INTx pins to IOAPIC pins is dependent of configuration registers and needs not appear in the devicetree.cb files at all. The write_smp_table implementation would skip writing any entry delivering to destination IOAPIC ID 0. This does not follow MP table specification. There were duplicate calls to register_new_ioapic_gsi0(), with another present under southbridge LPC device. Change-Id: I383d55ba2bc0800423617215e0bfdfad5136e9ac Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69488 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/Kconfig M src/arch/x86/mpspec.c D src/drivers/generic/ioapic/Kconfig D src/drivers/generic/ioapic/Makefile.inc D src/drivers/generic/ioapic/chip.h D src/drivers/generic/ioapic/ioapic.c M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/roda/rk9/Kconfig M src/mainboard/roda/rk9/devicetree.cb M src/mainboard/samsung/lumpy/Kconfig M src/mainboard/samsung/lumpy/devicetree.cb 14 files changed, 54 insertions(+), 303 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/Kconfig b/src/Kconfig index 08b2437..f30a1bb 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -795,9 +795,9 @@ menu "System tables" config GENERATE_MP_TABLE - prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC + prompt "Generate an MP table" if HAVE_MP_TABLE bool - default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC + default HAVE_MP_TABLE help Generate an MP table (conforming to the Intel MultiProcessor specification 1.4) for this board. diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index d94308e..15b64b3 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -9,7 +9,6 @@ #include <device/device.h> #include <device/path.h> #include <device/pci_ids.h> -#include <drivers/generic/ioapic/chip.h> #include <stdint.h> #include <string.h> @@ -509,34 +508,11 @@ return smp_next_mpe_entry(mc); } -static const struct device *find_next_ioapic(unsigned int last_ioapic_id) -{ - const struct device *dev; - const struct device *result = NULL; - unsigned int ioapic_id = MAX_APICS; - - for (dev = all_devices; dev; dev = dev->next) { - if (dev->path.type == DEVICE_PATH_IOAPIC && - dev->path.ioapic.ioapic_id > last_ioapic_id && - dev->path.ioapic.ioapic_id <= ioapic_id) { - result = dev; - } - } - return result; -} - unsigned long __weak write_smp_table(unsigned long addr) { - struct drivers_generic_ioapic_config *ioapic_config; struct mp_config_table *mc; - int isa_bus, pin, parentpin; - const struct device *dev; - const struct device *parent; - const struct device *oldparent; + int isa_bus; void *tmp, *v; - int isaioapic = -1, have_fixed_entries; - const struct pci_irq_info *pci_irq_info; - unsigned int ioapic_id = 0; v = smp_write_floating_table(addr, 0); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -547,99 +523,6 @@ mptable_write_buses(mc, NULL, &isa_bus); - while ((dev = find_next_ioapic(ioapic_id))) { - ioapic_config = dev->chip_info; - if (!ioapic_config) { - printk(BIOS_ERR, "%s has no config, ignoring\n", - dev_path(dev)); - ioapic_id++; - continue; - } - - ioapic_id = dev->path.ioapic.ioapic_id; - smp_write_ioapic(mc, ioapic_id, - ioapic_config->version, - ioapic_config->base); - - if (ioapic_config->have_isa_interrupts) { - if (isaioapic >= 0) - printk(BIOS_ERR, - "More than one IOAPIC with ISA interrupts?\n"); - else - isaioapic = dev->path.ioapic.ioapic_id; - } - } - - if (isaioapic >= 0) { - /* Legacy Interrupts */ - printk(BIOS_DEBUG, "Writing ISA IRQs\n"); - mptable_add_isa_interrupts(mc, isa_bus, isaioapic, 0); - } - - for (dev = all_devices; dev; dev = dev->next) { - - if (!is_enabled_pci(dev)) - continue; - - have_fixed_entries = 0; - for (pin = 0; pin < 4; pin++) { - if (dev->pci_irq_info[pin].ioapic_dst_id) { - printk(BIOS_DEBUG, - "fixed IRQ entry for: %s: INT%c# -> IOAPIC %d PIN %d\n", - dev_path(dev), - pin + 'A', - dev->pci_irq_info[pin].ioapic_dst_id, - dev->pci_irq_info[pin].ioapic_irq_pin); - smp_write_intsrc(mc, mp_INT, - dev->pci_irq_info[pin].ioapic_flags, - dev->bus->secondary, - ((dev->path.pci.devfn & 0xf8) >> 1) - | pin, - dev->pci_irq_info[pin].ioapic_dst_id, - dev->pci_irq_info[pin].ioapic_irq_pin); - have_fixed_entries = 1; - } - } - - if (!have_fixed_entries) { - pin = (dev->path.pci.devfn & 7) % 4; - oldparent = parent = dev; - while ((parent = parent->bus->dev)) { - parentpin = (oldparent->path.pci.devfn >> 3) - + (oldparent->path.pci.devfn & 7); - parentpin += dev->path.pci.devfn & 7; - parentpin += dev->path.pci.devfn >> 3; - parentpin %= 4; - - pci_irq_info = &parent->pci_irq_info[parentpin]; - if (pci_irq_info->ioapic_dst_id) { - printk(BIOS_DEBUG, - "automatic IRQ entry for %s: INT%c# -> IOAPIC %d PIN %d\n", - dev_path(dev), pin + 'A', - pci_irq_info->ioapic_dst_id, - pci_irq_info->ioapic_irq_pin); - smp_write_intsrc(mc, mp_INT, - pci_irq_info->ioapic_flags, - dev->bus->secondary, - ((dev->path.pci.devfn & 0xf8) - >> 1) | pin, - pci_irq_info->ioapic_dst_id, - pci_irq_info->ioapic_irq_pin); - - break; - } - - if (parent->path.type == DEVICE_PATH_DOMAIN) { - printk(BIOS_WARNING, - "no IRQ found for %s\n", - dev_path(dev)); - break; - } - oldparent = parent; - } - } - } - mptable_lintsrc(mc, isa_bus); tmp = mptable_finalize(mc); printk(BIOS_INFO, "MPTABLE len: %d\n", (unsigned int)((uintptr_t)tmp - diff --git a/src/drivers/generic/ioapic/Kconfig b/src/drivers/generic/ioapic/Kconfig deleted file mode 100644 index f8b46cb..0000000 --- a/src/drivers/generic/ioapic/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config DRIVERS_GENERIC_IOAPIC - bool diff --git a/src/drivers/generic/ioapic/Makefile.inc b/src/drivers/generic/ioapic/Makefile.inc deleted file mode 100644 index d34542b..0000000 --- a/src/drivers/generic/ioapic/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-$(CONFIG_DRIVERS_GENERIC_IOAPIC) += ioapic.c diff --git a/src/drivers/generic/ioapic/chip.h b/src/drivers/generic/ioapic/chip.h deleted file mode 100644 index a5fbeab..0000000 --- a/src/drivers/generic/ioapic/chip.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef DRIVERS_GENERIC_IOAPIC_CHIP_H -#define DRIVERS_GENERIC_IOAPIC_CHIP_H - -typedef struct drivers_generic_ioapic_config { - u32 version; - u8 apicid; - u8 have_isa_interrupts; - void *base; -} ioapic_config_t; - -#endif diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c deleted file mode 100644 index 8184484..0000000 --- a/src/drivers/generic/ioapic/ioapic.c +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include "chip.h" -#include <arch/ioapic.h> - -static void ioapic_init(struct device *dev) -{ - struct drivers_generic_ioapic_config *config = dev->chip_info; - - if (!dev->enabled || !config) - return; - - setup_ioapic(config->base, config->apicid); -} - -static void ioapic_read_resources(struct device *dev) -{ - struct drivers_generic_ioapic_config *config = (struct drivers_generic_ioapic_config *)dev->chip_info; - struct resource *res; - - res = new_resource(dev, 0); - res->base = (resource_t)(uintptr_t)config->base; - res->size = 0x1000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static struct device_operations ioapic_operations = { - .read_resources = ioapic_read_resources, - .set_resources = noop_set_resources, - .init = ioapic_init, -}; - -static void enable_dev(struct device *dev) -{ - dev->ops = &ioapic_operations; -} - -struct chip_operations drivers_generic_ioapic_ops = { - CHIP_NAME("IOAPIC") - .enable_dev = enable_dev, -}; diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index f90ed53..7854bbf 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -12,8 +12,6 @@ select H8_HAS_BAT_THRESHOLDS_IMPL select BOARD_ROMSIZE_KB_8192 if !BOARD_LENOVO_R500 select BOARD_ROMSIZE_KB_4096 if BOARD_LENOVO_R500 - select DRIVERS_GENERIC_IOAPIC - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select EC_ACPI select HAVE_OPTION_TABLE diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 670b488..57f1f37 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -34,7 +34,6 @@ device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on # VGA subsystemid 0x17aa 0x20e4 - ioapic_irq 2 INTA 0x10 end device pci 02.1 on subsystemid 0x17aa 0x20e4 @@ -85,27 +84,21 @@ device pci 19.0 on end # LAN device pci 1a.0 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 2 INTA 0x10 end device pci 1a.1 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 2 INTB 0x11 end device pci 1a.2 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 2 INTC 0x12 end device pci 1a.7 on # EHCI subsystemid 0x17aa 0x20f1 - ioapic_irq 2 INTC 0x12 end device pci 1b.0 on # HD Audio subsystemid 0x17aa 0x20f2 - ioapic_irq 2 INTA 0x10 end device pci 1c.0 on # PCIe Port #1 subsystemid 0x17aa 0x20f3 # WWAN - ioapic_irq 2 INTA 0x10 end device pci 1c.1 on subsystemid 0x17aa 0x20f3 # WLAN @@ -121,19 +114,15 @@ device pci 1c.5 off end # PCIe Port #6 device pci 1d.0 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 2 INTA 0x10 end device pci 1d.1 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 2 INTB 0x11 end device pci 1d.2 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 2 INTC 0x12 end device pci 1d.7 on # EHCI subsystemid 0x17aa 0x20f1 - ioapic_irq 2 INTA 0x10 end device pci 1e.0 on # PCI subsystemid 0x17aa 0x20f4 @@ -141,12 +130,6 @@ device pci 1f.0 on # LPC bridge subsystemid 0x17aa 0x20f5 - chip drivers/generic/ioapic - register "have_isa_interrupts" = "1" - register "base" = "(void *)0xfec00000" - device ioapic 2 on end - end - chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -217,7 +200,6 @@ end device pci 1f.2 on # SATA/IDE 1 subsystemid 0x17aa 0x20f8 - ioapic_irq 2 INTB 0x11 end device pci 1f.3 on end # SMBus device pci 1f.5 off end # SATA/IDE 2 diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 812ceee..8669300 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -11,8 +11,6 @@ select H8_HAS_BAT_THRESHOLDS_IMPL select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_8192 - select DRIVERS_GENERIC_IOAPIC - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select EC_ACPI select HAVE_OPTION_TABLE diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index dd631a7..059dc00 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -33,7 +33,6 @@ end # host bridge device pci 02.0 on # VGA subsystemid 0x17aa 0x20e4 - ioapic_irq 2 INTA 0x10 end device pci 02.1 on subsystemid 0x17aa 0x20e4 @@ -78,27 +77,21 @@ device pci 19.0 on end # LAN device pci 1a.0 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 2 INTA 0x10 end device pci 1a.1 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 2 INTB 0x11 end device pci 1a.2 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 2 INTC 0x12 end device pci 1a.7 on # EHCI subsystemid 0x17aa 0x20f1 - ioapic_irq 2 INTC 0x12 end device pci 1b.0 on # HD Audio subsystemid 0x17aa 0x20f2 - ioapic_irq 2 INTA 0x10 end device pci 1c.0 on # PCIe Port #1 subsystemid 0x17aa 0x20f3 # WWAN - ioapic_irq 2 INTA 0x10 end device pci 1c.1 on subsystemid 0x17aa 0x20f3 # WLAN @@ -111,19 +104,15 @@ device pci 1c.5 off end # PCIe Port #6 device pci 1d.0 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 2 INTA 0x10 end device pci 1d.1 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 2 INTB 0x11 end device pci 1d.2 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 2 INTC 0x12 end device pci 1d.7 on # EHCI subsystemid 0x17aa 0x20f1 - ioapic_irq 2 INTA 0x10 end device pci 1e.0 on # PCI subsystemid 0x17aa 0x20f4 @@ -131,12 +120,6 @@ device pci 1f.0 on # LPC bridge subsystemid 0x17aa 0x20f5 - chip drivers/generic/ioapic - register "have_isa_interrupts" = "1" - register "base" = "(void *)0xfec00000" - device ioapic 2 on end - end - chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -180,11 +163,9 @@ end device pci 1f.2 on # SATA/IDE 1 subsystemid 0x17aa 0x20f8 - ioapic_irq 2 INTB 0x11 end device pci 1f.3 on # SMBus subsystemid 0x17aa 0x20f9 - ioapic_irq 2 INTC 0x12 # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end diff --git a/src/mainboard/roda/rk9/Kconfig b/src/mainboard/roda/rk9/Kconfig index 7ce5e5e..ca0a369 100644 --- a/src/mainboard/roda/rk9/Kconfig +++ b/src/mainboard/roda/rk9/Kconfig @@ -8,8 +8,6 @@ select SOUTHBRIDGE_INTEL_I82801IX select SUPERIO_SMSC_LPC47N227 select BOARD_ROMSIZE_KB_4096 - select DRIVERS_GENERIC_IOAPIC - select HAVE_MP_TABLE select CARDBUS_PLUGIN_SUPPORT select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index cc5d763..c9c1896 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -23,9 +23,7 @@ device domain 0 on subsystemid 0x4352 0x8986 device pci 00.0 on end # host bridge - device pci 02.0 on # VGA - ioapic_irq 2 INTA 0x10 - end + device pci 02.0 on end # VGA device pci 02.1 on end # Display device pci 03.0 off end # ME device pci 03.1 off end # ME @@ -69,62 +67,32 @@ register "gen1_dec" = "0x000c0601" device pci 19.0 off end # LAN - device pci 1a.0 on # UHCI - ioapic_irq 2 INTA 0x10 - end - device pci 1a.1 on # UHCI - ioapic_irq 2 INTB 0x11 - end - device pci 1a.2 on # UHCI - ioapic_irq 2 INTC 0x12 - end - device pci 1a.7 on # EHCI - ioapic_irq 2 INTC 0x12 - end - device pci 1b.0 on # HD Audio - ioapic_irq 2 INTA 0x10 - end - device pci 1c.0 on # PCIe Port #1 - ioapic_irq 2 INTA 0x10 - end + device pci 1a.0 on end # UHCI + device pci 1a.1 on end # UHCI + device pci 1a.2 on end # UHCI + device pci 1a.7 on end # EHCI + device pci 1b.0 on end # HD Audio + device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 off end # PCIe Port #2 device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 on # PCIe Port #5 - ioapic_irq 2 INTA 0x10 device pci 00.0 on end # Realtek 8168B end device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on # UHCI - ioapic_irq 2 INTA 0x10 - end - device pci 1d.1 on # UHCI - ioapic_irq 2 INTB 0x11 - end - device pci 1d.2 on # UHCI - ioapic_irq 2 INTC 0x12 - end - device pci 1d.7 on # EHCI - ioapic_irq 2 INTA 0x10 - end + device pci 1d.0 on end # UHCI + device pci 1d.1 on end # UHCI + device pci 1d.2 on end # UHCI + device pci 1d.7 on end # EHCI device pci 1e.0 on # PCI - device pci 03.0 on # TI Cardbus - ioapic_irq 2 INTA 0x10 - end - device pci 03.1 on # TI Cardbus - ioapic_irq 2 INTB 0x11 - end + # device 03 INTA 0x10, INTB 0x11 + device pci 03.0 on end # TI Cardbus + device pci 03.1 on end # TI Cardbus device pci 03.2 off end # TI FireWire OHC device pci 03.3 off end # unconnected FlashMedia device pci 03.4 off end # unconnected SD-Card end device pci 1f.0 on # LPC bridge - chip drivers/generic/ioapic - register "have_isa_interrupts" = "1" - register "base" = "(void *)0xfec00000" - device ioapic 2 on end - end - chip superio/smsc/lpc47n227 device pnp 2e.1 on # Parallel port io 0x60 = 0x378 @@ -142,12 +110,8 @@ end end end - device pci 1f.2 on # SATA/IDE 1 - ioapic_irq 2 INTB 0x11 - end - device pci 1f.3 on # SMBus - ioapic_irq 2 INTC 0x12 - end + device pci 1f.2 on end # SATA/IDE 1 + device pci 1f.3 on end # SMBus device pci 1f.5 off end # SATA/IDE 2 device pci 1f.6 off end # Thermal end diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index eb8643e..8d8f625 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -21,7 +21,6 @@ # LPC47N207 selected for external LPC card # not on board, should be made selectable. select SUPERIO_SMSC_LPC47N207 - select DRIVERS_GENERIC_IOAPIC select INTEL_INT15 select SANDYBRIDGE_VBOOT_IN_ROMSTAGE select HAVE_SPD_IN_CBFS diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 1aab76d..ff7f362 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -32,10 +32,6 @@ end device domain 0 on - ioapic_irq 4 INTA 0x10 - ioapic_irq 4 INTB 0x11 - ioapic_irq 4 INTC 0x12 - ioapic_irq 4 INTD 0x13 subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller @@ -61,28 +57,19 @@ device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on # USB2 EHCI #2 - ioapic_irq 4 INTA 0x11 - end - device pci 1b.0 on # High Definition Audio - ioapic_irq 4 INTA 0x16 - end + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio device pci 1c.0 on end # PCIe Port #1 (WLAN) device pci 1c.1 off end # PCIe Port #2 device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on # PCIe Port #4 (LAN) - # ioapic_irq 4 INTA 0x13 - end + device pci 1c.3 on end # PCIe Port #4 (LAN) device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on # USB2 EHCI #1 - ioapic_irq 4 INTA 0x13 - end + device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on # LPC bridge - ioapic_irq 4 INTA 0x10 chip superio/smsc/mec1308 device pnp 2e.1 on # PM1 io 0x60 = 0xb00 @@ -104,22 +91,12 @@ register "mailbox_port" = "0xa00" device pnp ff.1 off end end - - chip drivers/generic/ioapic - register "have_isa_interrupts" = "1" - register "base" = "(void *)0xfec00000" - device ioapic 4 on end - end chip drivers/pc80/tpm device pnp 0c31.0 on end end end - device pci 1f.2 on # SATA Controller 1 - ioapic_irq 4 INTA 0x10 - end - device pci 1f.3 on # SMBus - ioapic_irq 4 INTC 0x17 - end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 on end # Thermal end -- To view, visit https://review.coreboot.org/c/coreboot/+/69488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I383d55ba2bc0800423617215e0bfdfad5136e9ac Gerrit-Change-Number: 69488 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: drivers/generic/ioapic: Use register_new_ioapic_gsi0()
by Kyösti Mälkki (Code Review) 13 Nov '22

13 Nov '22

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/55315 ) Change subject: drivers/generic/ioapic: Use register_new_ioapic_gsi0() ...................................................................... Abandoned Driver dropped with CB:69488 -- To view, visit https://review.coreboot.org/c/coreboot/+/55315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b03d32fa16fb9eb8a035e58bb7e3e027904f076 Gerrit-Change-Number: 55315 Gerrit-PatchSet: 11 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

1 0

[L] Change in coreboot[master]: drivers/generic/ioapic: Drop poor implementation
by Angel Pons (Code Review) 13 Nov '22

13 Nov '22

Attention is currently required from: Stefan Ott, Nico Huber, Kyösti Mälkki, Alexander Couzens. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69488 ) Change subject: drivers/generic/ioapic: Drop poor implementation ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I383d55ba2bc0800423617215e0bfdfad5136e9ac Gerrit-Change-Number: 69488 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sun, 13 Nov 2022 18:46:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: util/abuild: check for PASSED_BOARDS before trying to show it
by Martin L Roth (Code Review) 13 Nov '22

13 Nov '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69520 ) Change subject: util/abuild: check for PASSED_BOARDS before trying to show it ...................................................................... util/abuild: check for PASSED_BOARDS before trying to show it If no boards are tested by abuild, an error is currently shown because no boards failed, but no boards passed either. Account for this possibility. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I097d3c728ca1acc652d5a1b7b49e57d01b0e513b --- M util/abuild/abuild 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/69520/1 diff --git a/util/abuild/abuild b/util/abuild/abuild index 43dd833..3326a21 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -945,8 +945,10 @@ if [ "$exitcode" != "0" ]; then failed=1 fi - else + elif [ -f "$PASSED_BOARDS" ]; then printf "All %s tested configurations passed.\n" "$( wc -l < "$PASSED_BOARDS" )" + else + printf "No boards tested.\n" fi fi -- To view, visit https://review.coreboot.org/c/coreboot/+/69520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I097d3c728ca1acc652d5a1b7b49e57d01b0e513b Gerrit-Change-Number: 69520 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: superio/fintek/f71808a: Add VT2 boundary registers
by Angel Pons (Code Review) 13 Nov '22

13 Nov '22

Attention is currently required from: Martin L Roth, Ravi Mistry, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62200 ) Change subject: superio/fintek/f71808a: Add VT2 boundary registers ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62200/comment/918b838f_0979736d PS3, Line 17: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html > Please post archive.org link - please make sure the PDF is archived as well. How would one do it? -- To view, visit https://review.coreboot.org/c/coreboot/+/62200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f6b50da073cb55e141d6bf5185433c21d3fb554 Gerrit-Change-Number: 62200 Gerrit-PatchSet: 3 Gerrit-Owner: Ravi Mistry Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ravi Mistry Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Ravi Mistry Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 13 Nov 2022 18:29:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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