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[S] Change in coreboot[master]: ACPI MADT: Add LINT1 as NMI source
by Kyösti Mälkki (Code Review) 13 Nov '22

13 Nov '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69528 ) Change subject: ACPI MADT: Add LINT1 as NMI source ...................................................................... ACPI MADT: Add LINT1 as NMI source Set of boards and platforms did not have LINT1 configured as NMI source. Change-Id: I65044125562bda363b3a0d92da6137c77a28b587 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/aopen/dxplplusu/acpi_tables.c M src/mainboard/emulation/qemu-i440fx/acpi_tables.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/southbridge/intel/common/madt.c 5 files changed, 18 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/69528/1 diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c index 5f0d943..13ddb3e 100644 --- a/src/mainboard/aopen/dxplplusu/acpi_tables.c +++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c @@ -8,7 +8,7 @@ struct device *bdev, *dev = NULL; struct resource *res = NULL; - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* Southbridge IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, 0xfec00000); diff --git a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c index 61771c7..e6262d1 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c +++ b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c @@ -11,7 +11,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 7589464..4406188 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -89,7 +89,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 1c9eb4e..46a8771 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -329,7 +329,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/southbridge/intel/common/madt.c b/src/southbridge/intel/common/madt.c index eb11c21..b85e110 100644 --- a/src/southbridge/intel/common/madt.c +++ b/src/southbridge/intel/common/madt.c @@ -7,7 +7,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); -- To view, visit https://review.coreboot.org/c/coreboot/+/69528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65044125562bda363b3a0d92da6137c77a28b587 Gerrit-Change-Number: 69528 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: ACPI: Use common code for MADT LAPIC NMIs
by Kyösti Mälkki (Code Review) 13 Nov '22

13 Nov '22

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Matt DeVillier, Tim Wawrzynczak, Fred Reitberger, Felix Held. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69527 ) Change subject: ACPI: Use common code for MADT LAPIC NMIs ...................................................................... ACPI: Use common code for MADT LAPIC NMIs Use the broadcast ID to deliver LINT1 as NMI to all CPUs, instead of listing individual LAPIC IDs. Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/northbridge/amd/pi/00730F01/acpi_tables.c M src/soc/amd/cezanne/acpi.c M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/morgana/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/madt.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/madt.c 14 files changed, 46 insertions(+), 100 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/69527/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index e1d4088..1bc3a04 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -240,6 +240,24 @@ return lapic_nmi->length; } +unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current) +{ + const u16 flags = MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH; + + current = acpi_create_madt_lapics(current); + + /* 1: LINT1 connect to NMI */ + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, + ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, flags, 1); + + if (!CONFIG(XAPIC_ONLY)) + current += acpi_create_madt_lx2apic_nmi((acpi_madt_lx2apic_nmi_t *)current, + ACPI_MADT_LX2APIC_NMI_ALL_PROCESSORS, flags, 1); + + return current; +} + void acpi_create_madt(acpi_madt_t *madt) { acpi_header_t *header = &(madt->header); diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index d7fc243..3734473 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -624,7 +624,8 @@ u8 lint; /* Local APIC LINT# */ } __packed acpi_madt_lapic_nmi_t; -#define ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS 0xff +#define ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS 0xff +#define ACPI_MADT_LX2APIC_NMI_ALL_PROCESSORS (-1UL) /* MADT: I/O APIC Structure */ typedef struct acpi_madt_ioapic { @@ -1270,6 +1271,7 @@ u16 flags, u8 lint); void acpi_create_madt(acpi_madt_t *madt); unsigned long acpi_create_madt_lapics(unsigned long current); +unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current); int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic); int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, u16 flags, u8 lint); diff --git a/src/northbridge/amd/pi/00730F01/acpi_tables.c b/src/northbridge/amd/pi/00730F01/acpi_tables.c index 1edabcc..26636ea 100644 --- a/src/northbridge/amd/pi/00730F01/acpi_tables.c +++ b/src/northbridge/amd/pi/00730F01/acpi_tables.c @@ -6,7 +6,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* Write SB800 IOAPIC, only one */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); @@ -23,9 +23,5 @@ /* 2: APIC 2 */ /* 5 mean: 0101 --> Edge-triggered, Active high */ - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - /* 1: LINT1 connect to NMI */ - return current; } diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 189e84e..802476e 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -24,7 +24,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); @@ -41,12 +41,6 @@ MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); current = acpi_fill_madt_irqoverride(current); - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, - ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 1 /* 1: LINT1 connect to NMI */); - return current; } diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 85430b9..0c95494 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -27,7 +27,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); @@ -44,12 +44,6 @@ MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); current = acpi_fill_madt_irqoverride(current); - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, - ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 1 /* 1: LINT1 connect to NMI */); - return current; } diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index b867930..d30fb85 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -26,7 +26,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); @@ -43,12 +43,6 @@ MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); current = acpi_fill_madt_irqoverride(current); - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, - ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 1 /* 1: LINT1 connect to NMI */); - return current; } diff --git a/src/soc/amd/morgana/acpi.c b/src/soc/amd/morgana/acpi.c index 5eb21ff..15b64c5 100644 --- a/src/soc/amd/morgana/acpi.c +++ b/src/soc/amd/morgana/acpi.c @@ -27,7 +27,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); @@ -44,12 +44,6 @@ MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); current = acpi_fill_madt_irqoverride(current); - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, - ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 1 /* 1: LINT1 connect to NMI */); - return current; } diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 2af6459..6d46698 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -31,7 +31,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); @@ -49,12 +49,6 @@ current = acpi_fill_madt_irqoverride(current); - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, - ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 1 /* 1: LINT1 connect to NMI */); - return current; } diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 20221d2..cc0194b 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -26,7 +26,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* Write Kern IOAPIC, only one */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); @@ -42,12 +42,6 @@ MP_BUS_ISA, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, - ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 1 /* 1: LINT1 connect to NMI */); - return current; } diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index c355c944..860c868 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -69,12 +69,6 @@ current += acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); - /* NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - - if (is_x2apic_mode()) - current += acpi_create_madt_lx2apic_nmi((acpi_madt_lx2apic_nmi_t *)current, - 0xffffffff, 0x5, 1); return current; } @@ -91,7 +85,7 @@ size_t ioapic_entries; /* Local APICs */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ ioapic_table = soc_get_ioapic_info(&ioapic_entries); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index ec0df27..362e5cf 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -352,20 +352,11 @@ unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); diff --git a/src/southbridge/intel/i82801ix/madt.c b/src/southbridge/intel/i82801ix/madt.c index 19d5d8c..009c9ea 100644 --- a/src/southbridge/intel/i82801ix/madt.c +++ b/src/southbridge/intel/i82801ix/madt.c @@ -7,20 +7,11 @@ unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 7dfc33f..39b662a 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -367,20 +367,11 @@ unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); diff --git a/src/southbridge/intel/ibexpeak/madt.c b/src/southbridge/intel/ibexpeak/madt.c index a1a28a1..26b1630 100644 --- a/src/southbridge/intel/ibexpeak/madt.c +++ b/src/southbridge/intel/ibexpeak/madt.c @@ -9,7 +9,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); @@ -24,19 +24,5 @@ MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 2, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 3, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/69527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9 Gerrit-Change-Number: 69527 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/aopen/dxplplusu: Iterate CPUs for ACPI MADT
by Kyösti Mälkki (Code Review) 13 Nov '22

13 Nov '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69526 ) Change subject: mb/aopen/dxplplusu: Iterate CPUs for ACPI MADT ...................................................................... mb/aopen/dxplplusu: Iterate CPUs for ACPI MADT Change-Id: I64e5f5ee59859564c31ebb6f73b91d3d36be7d77 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/aopen/dxplplusu/acpi_tables.c 1 file changed, 11 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/69526/1 diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c index 2a3a97e..5f0d943 100644 --- a/src/mainboard/aopen/dxplplusu/acpi_tables.c +++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c @@ -1,10 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Ported to Intel XE7501DEVKIT by Agami Aruma - * Ported to AOpen DXPL Plus-U by Kyösti Mälkki - */ - #include <acpi/acpi.h> #include <device/pci_def.h> @@ -13,11 +8,7 @@ struct device *bdev, *dev = NULL; struct resource *res = NULL; - /* SJM: Hard-code CPU LAPIC entries for now */ - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0); - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 6); - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 1); - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 7); + current = acpi_create_madt_lapics(current); /* Southbridge IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, 0xfec00000); -- To view, visit https://review.coreboot.org/c/coreboot/+/69526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64e5f5ee59859564c31ebb6f73b91d3d36be7d77 Gerrit-Change-Number: 69526 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/emulation/qemu-q35: Use ioapic helper functions
by Kyösti Mälkki (Code Review) 13 Nov '22

13 Nov '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69525 ) Change subject: mb/emulation/qemu-q35: Use ioapic helper functions ...................................................................... mb/emulation/qemu-q35: Use ioapic helper functions Change-Id: I1b7f4935b6901525b2f3b2a8405c5678aaee7515 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/emulation/qemu-i440fx/acpi_tables.c 1 file changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/69525/1 diff --git a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c index 1f10837..61771c7 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c +++ b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c @@ -14,8 +14,7 @@ current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) -- To view, visit https://review.coreboot.org/c/coreboot/+/69525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b7f4935b6901525b2f3b2a8405c5678aaee7515 Gerrit-Change-Number: 69525 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/emulation/qemu-q35: Cleanup includes
by Kyösti Mälkki (Code Review) 13 Nov '22

13 Nov '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69524 ) Change subject: mb/emulation/qemu-q35: Cleanup includes ...................................................................... mb/emulation/qemu-q35: Cleanup includes Change-Id: Ib36d855e1dce8eb800bc077c1e444768c444fef8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/emulation/qemu-q35/cpu.c 1 file changed, 15 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/69524/1 diff --git a/src/mainboard/emulation/qemu-q35/cpu.c b/src/mainboard/emulation/qemu-q35/cpu.c index 698cd9c..c84b756 100644 --- a/src/mainboard/emulation/qemu-q35/cpu.c +++ b/src/mainboard/emulation/qemu-q35/cpu.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <cpu/amd/amd64_save_state.h> +#include <cpu/intel/smm_reloc.h> +#include <cpu/x86/legacy_save_state.h> #include <cpu/x86/mp.h> +#include <cpu/x86/smm.h> +#include <mainboard/emulation/qemu-i440fx/fw_cfg.h> #include <stddef.h> #include <stdint.h> -#include <cpu/intel/smm_reloc.h> -#include <cpu/amd/amd64_save_state.h> -#include <cpu/x86/legacy_save_state.h> -#include <mainboard/emulation/qemu-i440fx/fw_cfg.h> static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) -- To view, visit https://review.coreboot.org/c/coreboot/+/69524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib36d855e1dce8eb800bc077c1e444768c444fef8 Gerrit-Change-Number: 69524 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/starlabs/starbook/kbl: Drop redundant option code
by Sean Rhodes (Code Review) 13 Nov '22

13 Nov '22

Attention is currently required from: Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69522 ) Change subject: mb/starlabs/starbook/kbl: Drop redundant option code ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I602452266a8465cced12454f800ea023f382ba6f Gerrit-Change-Number: 69522 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 13 Nov 2022 19:20:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mainboard: Drop invalid `hyper_threading` option
by Michael Niewöhner (Code Review) 13 Nov '22

13 Nov '22

Attention is currently required from: Angel Pons. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69523 ) Change subject: mainboard: Drop invalid `hyper_threading` option ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8980a951f4751bc2e1a5d0e88835f578259b256 Gerrit-Change-Number: 69523 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 13 Nov 2022 19:12:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/starlabs/starbook/kbl: Drop redundant option code
by Michael Niewöhner (Code Review) 13 Nov '22

13 Nov '22

Attention is currently required from: Sean Rhodes, Angel Pons. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69522 ) Change subject: mb/starlabs/starbook/kbl: Drop redundant option code ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: +2 but let others a chance -- To view, visit https://review.coreboot.org/c/coreboot/+/69522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I602452266a8465cced12454f800ea023f382ba6f Gerrit-Change-Number: 69522 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 13 Nov 2022 19:07:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/clevo/cml-u: Fix CMOS options
by Michael Niewöhner (Code Review) 13 Nov '22

13 Nov '22

Attention is currently required from: Felix Singer, Angel Pons. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69521 ) Change subject: mb/clevo/cml-u: Fix CMOS options ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56b0320f9210cde8ff58db176d2b7d2207c98aa9 Gerrit-Change-Number: 69521 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 13 Nov 2022 19:06:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mainboard: Drop invalid `hyper_threading` option
by Angel Pons (Code Review) 13 Nov '22

13 Nov '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69523 ) Change subject: mainboard: Drop invalid `hyper_threading` option ...................................................................... mainboard: Drop invalid `hyper_threading` option Drop the `hyper_threading` CMOS option from most boards, as it's most likely not working properly and causing problems. The main reasons to remove the option are: * The used enum is backwards (0 ---> Enable, 1 ---> Disable) * Platform/SoC code does not honor the `hyper_threading` option Also, remove the now-unused enum used by the `hyper_threading` option. Change-Id: Ia8980a951f4751bc2e1a5d0e88835f578259b256 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/h110m/cmos.layout M src/mainboard/bostentech/gbyt4/cmos.layout M src/mainboard/google/auron/cmos.layout M src/mainboard/google/beltino/cmos.layout M src/mainboard/google/butterfly/cmos.layout M src/mainboard/google/cyan/cmos.layout M src/mainboard/google/glados/cmos.layout M src/mainboard/google/jecht/cmos.layout M src/mainboard/google/link/cmos.layout M src/mainboard/google/parrot/cmos.layout M src/mainboard/google/rambi/cmos.layout M src/mainboard/google/slippy/cmos.layout M src/mainboard/google/stout/cmos.layout M src/mainboard/intel/baskingridge/cmos.layout M src/mainboard/intel/emeraldlake2/cmos.layout M src/mainboard/intel/kblrvp/cmos.layout M src/mainboard/intel/kunimitsu/cmos.layout M src/mainboard/intel/strago/cmos.layout M src/mainboard/intel/wtm2/cmos.layout M src/mainboard/kontron/ktqm77/cmos.layout M src/mainboard/roda/rv11/cmos.layout M src/mainboard/samsung/lumpy/cmos.layout M src/mainboard/sapphire/pureplatinumh61/cmos.default M src/mainboard/sapphire/pureplatinumh61/cmos.layout 24 files changed, 19 insertions(+), 110 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/69523/1 diff --git a/src/mainboard/asrock/h110m/cmos.layout b/src/mainboard/asrock/h110m/cmos.layout index 80a4d21..cff042a 100644 --- a/src/mainboard/asrock/h110m/cmos.layout +++ b/src/mainboard/asrock/h110m/cmos.layout @@ -17,9 +17,6 @@ # coreboot config options: console 395 4 e 6 debug_level -# coreboot config options: cpu -400 1 e 2 hyper_threading - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail @@ -38,8 +35,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/bostentech/gbyt4/cmos.layout b/src/mainboard/bostentech/gbyt4/cmos.layout index 018db31..2b8e1a2 100644 --- a/src/mainboard/bostentech/gbyt4/cmos.layout +++ b/src/mainboard/bostentech/gbyt4/cmos.layout @@ -11,8 +11,6 @@ # ----------------------------------------------------------------- # coreboot config options: console 395 4 e 6 debug_level -# coreboot config options: cpu -400 1 e 2 hyper_threading # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail @@ -26,8 +24,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/google/auron/cmos.layout b/src/mainboard/google/auron/cmos.layout index 77ff743..78d44c1 100644 --- a/src/mainboard/google/auron/cmos.layout +++ b/src/mainboard/google/auron/cmos.layout @@ -15,9 +15,6 @@ # coreboot config options: console 395 4 e 6 debug_level -# coreboot config options: cpu -400 1 e 2 hyper_threading - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail @@ -36,8 +33,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout index 77ff743..78d44c1 100644 --- a/src/mainboard/google/beltino/cmos.layout +++ b/src/mainboard/google/beltino/cmos.layout @@ -15,9 +15,6 @@ # coreboot config options: console 395 4 e 6 debug_level -# coreboot config options: cpu -400 1 e 2 hyper_threading - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail @@ -36,8 +33,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout index 057f6a5..478af54 100644 --- a/src/mainboard/google/butterfly/cmos.layout +++ b/src/mainboard/google/butterfly/cmos.layout @@ -16,10 +16,6 @@ # No serial port on this motherboard 395 4 e 6 debug_level -# coreboot config options: cpu -# hyper_threading not supported by the Celeron 847 on this board -#400 1 e 2 hyper_threading - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail @@ -47,8 +43,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/google/cyan/cmos.layout b/src/mainboard/google/cyan/cmos.layout index 80a4d21..cff042a 100644 --- a/src/mainboard/google/cyan/cmos.layout +++ b/src/mainboard/google/cyan/cmos.layout @@ -17,9 +17,6 @@ # coreboot config options: console 395 4 e 6 debug_level -# coreboot config options: cpu -400 1 e 2 hyper_threading - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail @@ -38,8 +35,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/google/glados/cmos.layout b/src/mainboard/google/glados/cmos.layout index 80a4d21..cff042a 100644 --- a/src/mainboard/google/glados/cmos.layout +++ b/src/mainboard/google/glados/cmos.layout @@ -17,9 +17,6 @@ # coreboot config options: console 395 4 e 6 debug_level -# coreboot config options: cpu -400 1 e 2 hyper_threading - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail @@ -38,8 +35,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/google/jecht/cmos.layout b/src/mainboard/google/jecht/cmos.layout index 80a4d21..cff042a 100644 --- a/src/mainboard/google/jecht/cmos.layout +++ b/src/mainboard/google/jecht/cmos.layout @@ -17,9 +17,6 @@ # coreboot config options: console 395 4 e 6 debug_level -# coreboot config options: cpu -400 1 e 2 hyper_threading - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail @@ -38,8 +35,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout index 5cfca4f..a3b8b9f 100644 --- a/src/mainboard/google/link/cmos.layout +++ b/src/mainboard/google/link/cmos.layout @@ -15,9 +15,6 @@ # coreboot config options: console 395 4 e 6 debug_level -# coreboot config options: cpu -400 1 e 2 hyper_threading - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail @@ -44,8 +41,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout index 5cfca4f..a3b8b9f 100644 --- a/src/mainboard/google/parrot/cmos.layout +++ b/src/mainboard/google/parrot/cmos.layout @@ -15,9 +15,6 @@ # coreboot config options: console 395 4 e 6 debug_level -# coreboot config options: cpu -400 1 e 2 hyper_threading - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail @@ -44,8 +41,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/google/rambi/cmos.layout b/src/mainboard/google/rambi/cmos.layout index 77ff743..78d44c1 100644 --- a/src/mainboard/google/rambi/cmos.layout +++ b/src/mainboard/google/rambi/cmos.layout @@ -15,9 +15,6 @@ # coreboot config options: console 395 4 e 6 debug_level -# coreboot config options: cpu -400 1 e 2 hyper_threading - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail @@ -36,8 +33,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout index 77ff743..78d44c1 100644 --- a/src/mainboard/google/slippy/cmos.layout +++ b/src/mainboard/google/slippy/cmos.layout @@ -15,9 +15,6 @@ # coreboot config options: console 395 4 e 6 debug_level -# coreboot config options: cpu -400 1 e 2 hyper_threading - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail @@ -36,8 +33,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout index 5cfca4f..a3b8b9f 100644 --- a/src/mainboard/google/stout/cmos.layout +++ b/src/mainboard/google/stout/cmos.layout @@ -15,9 +15,6 @@ # coreboot config options: console 395 4 e 6 debug_level -# coreboot config options: cpu -400 1 e 2 hyper_threading - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail @@ -44,8 +41,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout index 77ff743..78d44c1 100644 --- a/src/mainboard/intel/baskingridge/cmos.layout +++ b/src/mainboard/intel/baskingridge/cmos.layout @@ -15,9 +15,6 @@ # coreboot config options: console 395 4 e 6 debug_level -# coreboot config options: cpu -400 1 e 2 hyper_threading - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail @@ -36,8 +33,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/intel/emeraldlake2/cmos.layout b/src/mainboard/intel/emeraldlake2/cmos.layout index 7301ef9d..935557c 100644 --- a/src/mainboard/intel/emeraldlake2/cmos.layout +++ b/src/mainboard/intel/emeraldlake2/cmos.layout @@ -15,9 +15,6 @@ # coreboot config options: console 395 4 e 6 debug_level -# coreboot config options: cpu -400 1 e 2 hyper_threading - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail @@ -44,8 +41,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/intel/kblrvp/cmos.layout b/src/mainboard/intel/kblrvp/cmos.layout index 80a4d21..cff042a 100644 --- a/src/mainboard/intel/kblrvp/cmos.layout +++ b/src/mainboard/intel/kblrvp/cmos.layout @@ -17,9 +17,6 @@ # coreboot config options: console 395 4 e 6 debug_level -# coreboot config options: cpu -400 1 e 2 hyper_threading - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail @@ -38,8 +35,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/intel/kunimitsu/cmos.layout b/src/mainboard/intel/kunimitsu/cmos.layout index 80a4d21..cff042a 100644 --- a/src/mainboard/intel/kunimitsu/cmos.layout +++ b/src/mainboard/intel/kunimitsu/cmos.layout @@ -17,9 +17,6 @@ # coreboot config options: console 395 4 e 6 debug_level -# coreboot config options: cpu -400 1 e 2 hyper_threading - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail @@ -38,8 +35,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/intel/strago/cmos.layout b/src/mainboard/intel/strago/cmos.layout index 80a4d21..cff042a 100644 --- a/src/mainboard/intel/strago/cmos.layout +++ b/src/mainboard/intel/strago/cmos.layout @@ -17,9 +17,6 @@ # coreboot config options: console 395 4 e 6 debug_level -# coreboot config options: cpu -400 1 e 2 hyper_threading - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail @@ -38,8 +35,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/intel/wtm2/cmos.layout b/src/mainboard/intel/wtm2/cmos.layout index 77ff743..78d44c1 100644 --- a/src/mainboard/intel/wtm2/cmos.layout +++ b/src/mainboard/intel/wtm2/cmos.layout @@ -15,9 +15,6 @@ # coreboot config options: console 395 4 e 6 debug_level -# coreboot config options: cpu -400 1 e 2 hyper_threading - # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail @@ -36,8 +33,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index 914ad6d..67887ce 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -16,7 +16,6 @@ 395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading 401 3 e 12 gfx_uma_size # coreboot config options: southbridge diff --git a/src/mainboard/roda/rv11/cmos.layout b/src/mainboard/roda/rv11/cmos.layout index 8a48366..5595b85 100644 --- a/src/mainboard/roda/rv11/cmos.layout +++ b/src/mainboard/roda/rv11/cmos.layout @@ -17,7 +17,6 @@ 395 4 e 5 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading 401 3 e 9 gfx_uma_size # coreboot config options: southbridge @@ -46,8 +45,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 3 0 Fallback 3 1 Normal 5 0 Emergency diff --git a/src/mainboard/samsung/lumpy/cmos.layout b/src/mainboard/samsung/lumpy/cmos.layout index 60accd7..0dcd09d 100644 --- a/src/mainboard/samsung/lumpy/cmos.layout +++ b/src/mainboard/samsung/lumpy/cmos.layout @@ -15,9 +15,6 @@ # coreboot config options: console 395 4 e 6 debug_level -# coreboot config options: cpu -400 1 e 2 hyper_threading - # coreboot config options: southbridge 408 1 e 1 nmi #409 2 e 7 power_on_after_fail @@ -44,8 +41,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency diff --git a/src/mainboard/sapphire/pureplatinumh61/cmos.default b/src/mainboard/sapphire/pureplatinumh61/cmos.default index 7cd30cc..38f2bd3 100644 --- a/src/mainboard/sapphire/pureplatinumh61/cmos.default +++ b/src/mainboard/sapphire/pureplatinumh61/cmos.default @@ -3,4 +3,3 @@ power_on_after_fail=Enable nmi=Enable sata_mode=AHCI -hyper_threading=Enable diff --git a/src/mainboard/sapphire/pureplatinumh61/cmos.layout b/src/mainboard/sapphire/pureplatinumh61/cmos.layout index 979c8e2..fabafef 100644 --- a/src/mainboard/sapphire/pureplatinumh61/cmos.layout +++ b/src/mainboard/sapphire/pureplatinumh61/cmos.layout @@ -21,9 +21,6 @@ 421 1 e 9 sata_mode -# coreboot config options: cpu -424 1 e 2 hyper_threading - # coreboot config options: northbridge 432 3 e 11 gfx_uma_size @@ -42,8 +39,6 @@ #ID value text 1 0 Disable 1 1 Enable -2 0 Enable -2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency -- To view, visit https://review.coreboot.org/c/coreboot/+/69523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8980a951f4751bc2e1a5d0e88835f578259b256 Gerrit-Change-Number: 69523 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2022