coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: intel/haswell,lynxpoint: Fix out() parameter order
by Angel Pons (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Nico Huber, Kyösti Mälkki. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69677 ) Change subject: intel/haswell,lynxpoint: Fix out() parameter order ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > CB:69703 pmutil.c is still used by Broadwell code. It's just that unifying the codebases got put on indefinite hold after CB:54976 and CB:54977, combined with the lack of an in-tree Broadwell mainboard to comfortably test stuff with (CB:37568 and CB:52475 exist but are out-of-tree for now...). Or maybe it's the frustration arising from these things. -- To view, visit https://review.coreboot.org/c/coreboot/+/69677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife134ef6d508113e3cd27b6352ee5044aee43744 Gerrit-Change-Number: 69677 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 16 Nov 2022 15:57:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/broadwell: Fix out() parameter order
by Elyes Haouas (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Kyösti Mälkki. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69703 ) Change subject: soc/intel/broadwell: Fix out() parameter order ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0897acddd00bad89a5fd784f82380ed0d0d2c06e Gerrit-Change-Number: 69703 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 16 Nov 2022 15:47:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: intel/haswell,lynxpoint: Fix out() parameter order
by Kyösti Mälkki (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Nico Huber. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69677 ) Change subject: intel/haswell,lynxpoint: Fix out() parameter order ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Thanks! […] CB:69703 -- To view, visit https://review.coreboot.org/c/coreboot/+/69677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife134ef6d508113e3cd27b6352ee5044aee43744 Gerrit-Change-Number: 69677 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 16 Nov 2022 15:46:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/broadwell: Fix out() parameter order
by Kyösti Mälkki (Code Review) 16 Nov '22

16 Nov '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69703 ) Change subject: soc/intel/broadwell: Fix out() parameter order ...................................................................... soc/intel/broadwell: Fix out() parameter order Change-Id: I0897acddd00bad89a5fd784f82380ed0d0d2c06e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/broadwell/pch/pmutil.c 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/69703/1 diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/soc/intel/broadwell/pch/pmutil.c index 59ae72f..3da6bce 100644 --- a/src/soc/intel/broadwell/pch/pmutil.c +++ b/src/soc/intel/broadwell/pch/pmutil.c @@ -309,7 +309,7 @@ void enable_tco_sci(void) { /* Clear pending events */ - outl(get_pmbase() + GPE0_STS(3), TCOSCI_STS); + outl(TCOSCI_STS, get_pmbase() + GPE0_STS(3)); /* Enable TCO SCI events */ enable_gpe(TCOSCI_EN); -- To view, visit https://review.coreboot.org/c/coreboot/+/69703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0897acddd00bad89a5fd784f82380ed0d0d2c06e Gerrit-Change-Number: 69703 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: cpu/intel/haswell: Move chip_ops to cpu cluster
by Angel Pons (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Arthur Heymans, Raul Rangel, Tristan Corrick, Tim Wawrzynczak, Alexander Couzens, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59314 ) Change subject: cpu/intel/haswell: Move chip_ops to cpu cluster ...................................................................... Patch Set 14: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/59314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786 Gerrit-Change-Number: 59314 Gerrit-PatchSet: 14 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 16 Nov 2022 15:42:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/aopen/dxplplusu: Iterate CPUs for ACPI MADT
by Kyösti Mälkki (Code Review) 16 Nov '22

16 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69526 ) Change subject: mb/aopen/dxplplusu: Iterate CPUs for ACPI MADT ...................................................................... mb/aopen/dxplplusu: Iterate CPUs for ACPI MADT Change-Id: I64e5f5ee59859564c31ebb6f73b91d3d36be7d77 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69526 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/aopen/dxplplusu/acpi_tables.c 1 file changed, 15 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c index 2a3a97e..5f0d943 100644 --- a/src/mainboard/aopen/dxplplusu/acpi_tables.c +++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c @@ -1,10 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Ported to Intel XE7501DEVKIT by Agami Aruma - * Ported to AOpen DXPL Plus-U by Kyösti Mälkki - */ - #include <acpi/acpi.h> #include <device/pci_def.h> @@ -13,11 +8,7 @@ struct device *bdev, *dev = NULL; struct resource *res = NULL; - /* SJM: Hard-code CPU LAPIC entries for now */ - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0); - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 6); - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 1); - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 7); + current = acpi_create_madt_lapics(current); /* Southbridge IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, 0xfec00000); -- To view, visit https://review.coreboot.org/c/coreboot/+/69526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64e5f5ee59859564c31ebb6f73b91d3d36be7d77 Gerrit-Change-Number: 69526 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: cpu/x86/smm: Use common SMM_ASEG region
by Kyösti Mälkki (Code Review) 16 Nov '22

16 Nov '22

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69665 ) Change subject: cpu/x86/smm: Use common SMM_ASEG region ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Oops, not yet 24h -- To view, visit https://review.coreboot.org/c/coreboot/+/69665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idca56583c1c8dc41ad11d915ec3e8be781fb4e48 Gerrit-Change-Number: 69665 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Nov 2022 15:35:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/x86/smm: Use common SMM_ASEG region
by Kyösti Mälkki (Code Review) 16 Nov '22

16 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69665 ) Change subject: cpu/x86/smm: Use common SMM_ASEG region ...................................................................... cpu/x86/smm: Use common SMM_ASEG region Change-Id: Idca56583c1c8dc41ad11d915ec3e8be781fb4e48 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69665 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/Makefile.inc M src/cpu/x86/smm/smm_module_loader.c M src/cpu/x86/smm/tseg_region.c M src/include/cpu/x86/smm.h M src/mainboard/emulation/qemu-q35/cpu.c 5 files changed, 28 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index da93827..327b6c6 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -29,14 +29,10 @@ smm-y += save_state.c -ifeq ($(CONFIG_SMM_TSEG),y) - ramstage-y += tseg_region.c romstage-y += tseg_region.c postcar-y += tseg_region.c -endif - ifeq ($(CONFIG_PARALLEL_MP),y) smmstub-y += smm_stub.S diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 6f334a2..6924f08 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -409,11 +409,6 @@ int smm_load_module(const uintptr_t smram_base, const size_t smram_size, struct smm_loader_params *params) { - if (CONFIG(SMM_ASEG) && (smram_base != SMM_BASE || smram_size != SMM_CODE_SEGMENT_SIZE)) { - printk(BIOS_ERR, "SMM base & size are 0x%lx, 0x%zx, but must be 0x%x, 0x%x\n", - smram_base, smram_size, SMM_BASE, SMM_CODE_SEGMENT_SIZE); - return -1; - } /* * Place in .bss to reduce stack usage. * TODO: once CPU_INFO_V2 is used everywhere, use smaller stack for APs and move diff --git a/src/cpu/x86/smm/tseg_region.c b/src/cpu/x86/smm/tseg_region.c index f6aecd0..413d5fc 100644 --- a/src/cpu/x86/smm/tseg_region.c +++ b/src/cpu/x86/smm/tseg_region.c @@ -26,7 +26,12 @@ const size_t ied_size = CONFIG_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; - smm_region(&sub_base, &sub_size); + if (CONFIG(SMM_TSEG)) + smm_region(&sub_base, &sub_size); + else if (CONFIG(SMM_ASEG)) + aseg_region(&sub_base, &sub_size); + else + return -1; ASSERT(IS_ALIGNED(sub_base, sub_size)); ASSERT(sub_size > (cache_size + ied_size)); diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index b6d778b..7283a6b 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -165,6 +165,12 @@ */ void smm_region(uintptr_t *start, size_t *size); +static inline void aseg_region(uintptr_t *start, size_t *size) +{ + *start = SMM_BASE; + *size = SMM_DEFAULT_SIZE; /* SMM_CODE_SEGMENT_SIZE ? */ +} + enum { /* SMM handler area. */ SMM_SUBREGION_HANDLER, diff --git a/src/mainboard/emulation/qemu-q35/cpu.c b/src/mainboard/emulation/qemu-q35/cpu.c index c84b756..58b1fa5 100644 --- a/src/mainboard/emulation/qemu-q35/cpu.c +++ b/src/mainboard/emulation/qemu-q35/cpu.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <commonlib/helpers.h> #include <console/console.h> #include <cpu/amd/amd64_save_state.h> #include <cpu/intel/smm_reloc.h> @@ -15,14 +16,10 @@ { printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); - if (CONFIG(SMM_TSEG)) - smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); + smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize); - if (CONFIG(SMM_ASEG)) { + if (CONFIG(SMM_ASEG)) smm_open_aseg(); - *perm_smbase = 0xa0000; - *perm_smsize = 0x10000; - } /* FIXME: on X86_64 the save state size is smaller than the size of the SMM stub */ *smm_save_state_size = sizeof(amd64_smm_state_save_area_t); -- To view, visit https://review.coreboot.org/c/coreboot/+/69665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idca56583c1c8dc41ad11d915ec3e8be781fb4e48 Gerrit-Change-Number: 69665 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices
by Subrata Banik (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69680 ) Change subject: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69680/comment/1468ac50_ed63f53b PS2, Line 10: : The learning being made from Alder Lake platform showed that the CSE : EOP cmd response time is highly nondeterministic and letting the EOP : cmd issued by FSP makes the response time even worse. : : The idea being pursued during Alder Lake platform is to let FSP skip sending the EOP cmd and coreboot sends it at the last minute : (late sending of EOP) to ensure there is ample time for CSE to come : to a state where the response to the EOP is almost immediate. > Thanks for commit update. Since architectural change from ADL to MTL, I'm not sure if this is applicable to MTL. Can you please elaborate how the EOP cmd receiving arch is different between ADL and MTL? We would like to get rid of FSP sending EOP and taking control of things inside coreboot and for that matter, we need to make some changes (this CL is one of those changes). we don't want FSP to send the EOP hence, it's important that we make sure FSP is not touching the D0i3 bit even for HECI devices. I don't see any concern about letting this CL in. -- To view, visit https://review.coreboot.org/c/coreboot/+/69680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c3765ce41f192ab5f5ff176e0a2b49b312d18d2 Gerrit-Change-Number: 69680 Gerrit-PatchSet: 3 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Wed, 16 Nov 2022 15:31:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/amdfwutil: Add some types to both LVL
by Marvin Drees (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Arthur Heymans, Karthik Ramasubramanian. Marvin Drees has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68120 ) Change subject: util/amdfwutil: Add some types to both LVL ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/68120/comment/de263f05_4ecd6dc6 PS2, Line 239: PSP_BOTH_AB > If I understand correctly, only ISH tables are expected to be LVL1 on the SoCs with recovery A/B lay […] I think most things are rather expected in level 2 and not both as level 1 is meant to house sane defaults, but the way we currently build and deploy coreboot for those platforms is already not fully in spec. I think level 2 already has priority over level 1 anyways so considering the entries in level 2 are sane doesn't hurt having them in level 1 as well. We don't have multi-soc support as well so I guess it's fine for now putting these entries in both. Are you aware of a platform which breaks when putting these entries in both? -- To view, visit https://review.coreboot.org/c/coreboot/+/68120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb838396baf79f32823ca271f55456570ba40c20 Gerrit-Change-Number: 68120 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 16 Nov 2022 15:30:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2022