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Change subject: mb/google/skyrim/var/winterhold: Update touchscreen devicetree setting
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Patch Set 1: Code-Review+2
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Change subject: mb/google/brya/var/agah: Add Power Limits for RPL SKU
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Patch Set 3: Code-Review+2
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Change subject: mb/google/skyrim/var/winterhold: Update touchscreen devicetree setting
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Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69559 )
Change subject: mb/google/brya/variants/volmar: Update ELAN touchscreen timing
......................................................................
mb/google/brya/variants/volmar: Update ELAN touchscreen timing
ELAN updated the datasheet, the HID/I2C protocol's T3 delay
time is 150ms now. Modify the volmar's delay time to follow
the requiremnet.
BUG=b:257073343
TEST=Build firmware and measure the …
[View More]T3 timing of resume
and boot up on volmar DUT.
Run Suspend/Resume with UI test and got pass.
Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>
Change-Id: I40a30ed567cd676d0a9373527d93fe51f89d39e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69559
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---
M src/mainboard/google/brya/variants/volmar/overridetree.cb
1 file changed, 24 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Nick Vaccaro: Looks good to me, approved
Ren Kuo: Looks good to me, but someone else must approve
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/volmar/overridetree.cb b/src/mainboard/google/brya/variants/volmar/overridetree.cb
index 056467c..b7ce0a3 100644
--- a/src/mainboard/google/brya/variants/volmar/overridetree.cb
+++ b/src/mainboard/google/brya/variants/volmar/overridetree.cb
@@ -262,7 +262,7 @@
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
- register "generic.reset_delay_ms" = "20"
+ register "generic.reset_delay_ms" = "150"
register "generic.reset_off_delay_ms" = "1"
register "generic.enable_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
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Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69384 )
Change subject: drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS2:
> A short discussion on IRC showed that drivers/net/phy/ is a good location for this driver. […]
I will change this tomorrow …
[View More]morning.
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Change subject: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69680/comment/ca4d3fbd_ea3e21f8
PS2, Line 10:
: The learning …
[View More]being made from Alder Lake platform showed that the CSE
: EOP cmd response time is highly nondeterministic and letting the EOP
: cmd issued by FSP makes the response time even worse.
:
: The idea being pursued during Alder Lake platform is to let FSP skip sending the EOP cmd and coreboot sends it at the last minute
: (late sending of EOP) to ensure there is ample time for CSE to come
: to a state where the response to the EOP is almost immediate.
> > Thanks for commit update. Since architectural change from ADL to MTL, I'm not sure if this is applicable to MTL.
>
> Can you please elaborate how the EOP cmd receiving arch is different between ADL and MTL?
>
> We would like to get rid of FSP sending EOP and taking control of things inside coreboot and for that matter, we need to make some changes (this CL is one of those changes).
>
> we don't want FSP to send the EOP hence, it's important that we make sure FSP is not touching the D0i3 bit even for HECI devices. I don't see any concern about letting this CL in.
I took a further looks and noticed that, we have dropped FSP Notify Phase since ADL hence, the only possibility about sending EOP is from coreboot.
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69470 )
Change subject: WIP:soc/amd/morgana: Move PSP FWs to 0x20000
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/amd/birman/Kconfig:
https://review.coreboot.org/c/coreboot/+/69470/comment/304b79c5_9fc5aa11
PS2,…
[View More] Line 31: default 5
> Ack. […]
i was told the same for mendocino, but it turned out that the mendocino hardware does support other efs offsets than the first possible one. right now, the primary efs is supposed to be within the RO fmap partition that is at the end of the image. while this probably could be changed, it's something that should be discussed with Google
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