coreboot-gerrit November 2022

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[S] Change in coreboot[master]: mb/google/skyrim: Enable STB Spill-to-DRAM by default
by Martin L Roth (Code Review) 16 Nov '22

16 Nov '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69707 ) Change subject: mb/google/skyrim: Enable STB Spill-to-DRAM by default ...................................................................... mb/google/skyrim: Enable STB Spill-to-DRAM by default Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ib60b7fc2ba85c7a8025c9f8c6495e94049499f56 --- M src/mainboard/google/skyrim/Kconfig 1 file changed, 19 insertions(+), 0 deletions(-)… [View More]

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[S] Change in coreboot[master]: cpu/x86/smm: Use common SMM_ASEG region
by 9elements QA (Code Review) 16 Nov '22

16 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69665 ) Change subject: cpu/x86/smm: Use common SMM_ASEG region ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/136607 PASS: x86_32 "Hermes CFL" , build config … [View More]PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/136606 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/136605 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/136604 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/136603 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/136602 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/136601 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/136600 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/136599 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/136598 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/136597 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/136596 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/136595 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/136594 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/136593 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/136592 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idca56583c1c8dc41ad11d915ec3e8be781fb4e48 Gerrit-Change-Number: 69665 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 16 Nov 2022 19:06:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment [View Less]

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[S] Change in coreboot[master]: vc/amd/fsp/glinda/platform_descriptors.h: Update for glinda
by Fred Reitberger (Code Review) 16 Nov '22

16 Nov '22

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69706 ) Change subject: vc/amd/fsp/glinda/platform_descriptors.h: Update for glinda ...................................................................... vc/amd/fsp/glinda/platform_descriptors.h: Update for glinda Update definitions on glinda used by birman. Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I03065011581489b5345c16e225edc341e1d7811c --- M src/… [View More]

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[S] Change in coreboot[master]: soc/intel/meteorlake: Enable FSP multiphase
by Subrata Banik (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, John Zhao, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67741 ) Change subject: soc/intel/meteorlake: Enable FSP multiphase ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67741 To unsubscribe, or for help writing mail filters, visit https://review.… [View More]

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[S] Change in coreboot[master]: soc/intel/meteorlake: Enable FSP multiphase
by Jamie Ryu (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, John Zhao, Sridhar Siricilla. Jamie Ryu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67741 ) Change subject: soc/intel/meteorlake: Enable FSP multiphase ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/67741 To unsubscribe, or for help writing mail filters, visit https:/… [View More]

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[M] Change in coreboot[master]: mb/amd/birman/port_descriptors.c: Update DXIO for birman
by Fred Reitberger (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Jason Glenesk, Felix Held. Hello Jason Glenesk, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69705 to look at the new patch set (#2). Change subject: mb/amd/birman/port_descriptors.c: Update DXIO for birman ...................................................................... mb/amd/birman/port_descriptors.c: Update DXIO for birman Update DXIO descriptors for birman per schematic 105-… [View More]

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[M] Change in coreboot[master]: mb/amd/birman/port_descriptors.c: Update DXIO for birman
by build bot (Jenkins) (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Jason Glenesk, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69705 ) Change subject: mb/amd/birman/port_descriptors.c: Update DXIO for birman ...................................................................... Patch Set 1: (1 comment) File src/mainboard/amd/birman/port_descriptors.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163804): https://review.coreboot.… [View More]

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[M] Change in coreboot[master]: mb/amd/birman/port_descriptors.c: Update DXIO for birman
by Fred Reitberger (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Jason Glenesk, Felix Held. Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69705 ) Change subject: mb/amd/birman/port_descriptors.c: Update DXIO for birman ...................................................................... mb/amd/birman/port_descriptors.c: Update DXIO for birman Update DXIO descriptors for birman per schematic 105-D67000-00B v0.7 Signed-off-by: Fred Reitberger <reitbergerfred(a)… [View More]gmail.com> Change-Id: I76cf6715b60a1857bf58349d70a623bf043594fe --- M src/mainboard/amd/birman/port_descriptors.c 1 file changed, 90 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/69705/1 diff --git a/src/mainboard/amd/birman/port_descriptors.c b/src/mainboard/amd/birman/port_descriptors.c index f2ed5c5..b223dc1 100644 --- a/src/mainboard/amd/birman/port_descriptors.c +++ b/src/mainboard/amd/birman/port_descriptors.c @@ -6,48 +6,100 @@ #include <soc/platform_descriptors.h> #include <types.h> -/* TODO: Update for birman */ - static const fsp_dxio_descriptor birman_dxio_descriptors[] = { - { + { /* MXM */ .engine_type = PCIE_ENGINE, .port_present = true, .start_logical_lane = 0, - .end_logical_lane = 0, - .device_number = 2, + .end_logical_lane = 3, + .device_number = 1, .function_number = 1, .link_speed_capability = GEN3, .turn_off_unused_lanes = true, - .link_aspm = 2, - .link_hotplug = 3, - .clk_req = CLK_REQ3, + .link_aspm = ASPM_L1, + .link_hotplug = 0, + .gpio_group_id = GPIO_26, + .clk_req = CLK_REQ0, }, - { + { /* NVMe SSD0 */ .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 1, - .end_logical_lane = 1, + .start_logical_lane = 16, + .end_logical_lane = 19, + .device_number = 2, + .function_number = 4, + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_hotplug = 0, + .gpio_group_id = GPIO_27, + .clk_req = CLK_REQ2, + }, + { /* WLAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 15, + .end_logical_lane = 15, .device_number = 2, .function_number = 2, .link_speed_capability = GEN3, .turn_off_unused_lanes = true, - .link_aspm = 2, - .link_hotplug = 3, - .clk_req = CLK_REQ1, + .link_aspm = ASPM_L1, + .link_hotplug = 0, + .clk_req = CLK_REQ3, }, - { + { /* SD */ .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 2, - .end_logical_lane = 3, + .start_logical_lane = 13, + .end_logical_lane = 13, + .device_number = 2, + .function_number = 1, + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_hotplug = 0, + .clk_req = CLK_REQ5, + }, + { /* NVMe SSD1 */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 8, + .end_logical_lane = 11, + .device_number = 1, + .function_number = 2, + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_hotplug = 0, + .gpio_group_id = GPIO_26, + .clk_req = CLK_REQ1, + }, + { /* GBE */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 12, + .end_logical_lane = 12, + .device_number = 1, + .function_number = 3, + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = ASPM_L1, + .link_hotplug = 0, + .clk_req = CLK_REQ3, + }, + { /* WWAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 14, + .end_logical_lane = 14, .device_number = 2, .function_number = 3, .link_speed_capability = GEN3, .turn_off_unused_lanes = true, - .link_aspm = 2, - .link_hotplug = 3, - .gpio_group_id = GPIO_27, - .clk_req = CLK_REQ0, + .link_aspm = ASPM_L1, + .link_hotplug = 0, + .clk_req = CLK_REQ4, }, }; @@ -98,7 +150,7 @@ connector_type = eeprom_connector_type_data[1] | eeprom_connector_type_data[0] << 8; switch (connector_type) { - case 0xc: + case 0x0c: printk(BIOS_DEBUG, "Configuring DDI1 as HDMI.\n"); return DDI_HDMI; break; @@ -110,6 +162,10 @@ printk(BIOS_DEBUG, "Configuring DDI1 as eDP.\n"); return DDI_EDP; break; + case 0x17: + printk(BIOS_DEBUG, "Configuring DDI1 as USB-C.\n"); + return DDI_DP_W_TYPEC; + break; default: printk(BIOS_WARNING, "Unexpected display connector type %x. Disabling DDI1.\n", connector_type); -- To view, visit https://review.coreboot.org/c/coreboot/+/69705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76cf6715b60a1857bf58349d70a623bf043594fe Gerrit-Change-Number: 69705 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange [View Less]

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[S] Change in coreboot[master]: vc/amd/fsp/morgana/platform_descriptors.h: Update for morgana
by Fred Reitberger (Code Review) 16 Nov '22

16 Nov '22

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69704 ) Change subject: vc/amd/fsp/morgana/platform_descriptors.h: Update for morgana ...................................................................... vc/amd/fsp/morgana/platform_descriptors.h: Update for morgana Update definitions to match morgana FSP. Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: Ic893526789c05a298965702114d4a814466a5742 --- M src/… [View More]vendorcode/amd/fsp/morgana/platform_descriptors.h 1 file changed, 30 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/69704/1 diff --git a/src/vendorcode/amd/fsp/morgana/platform_descriptors.h b/src/vendorcode/amd/fsp/morgana/platform_descriptors.h index 75bf3ad..829170d 100644 --- a/src/vendorcode/amd/fsp/morgana/platform_descriptors.h +++ b/src/vendorcode/amd/fsp/morgana/platform_descriptors.h @@ -10,6 +10,8 @@ #ifndef PI_PLATFORM_DESCRIPTORS_H #define PI_PLATFORM_DESCRIPTORS_H +#include <stdint.h> + #define NUM_DXIO_PHY_PARAMS 6 #define NUM_DXIO_PORT_PARAMS 6 @@ -55,7 +57,7 @@ CLK_REQ1, CLK_REQ2, CLK_REQ3, - CLK_REQ4_GFX, + CLK_REQ4, CLK_REQ5, CLK_REQ6, CLK_ENABLE = 0xff, @@ -144,8 +146,8 @@ DDI_DP_TO_LVDS, // DP-to-LVDS DDI_NUTMEG_DP_TO_VGA, // Hudson-2 NutMeg DP-to-VGA DDI_SINGLE_LINK_DVI_I, // Single Link DVI-I - DDI_CRT, // CRT (VGA) - DDI_LVDS, // LVDS + DDI_DP_W_TYPEC, // DP with USB type C + DDI_DP_WO_TYPEC, // DP without USB type C DDI_EDP_TO_LVDS, // eDP-to-LVDS translator chip without AMD SW init DDI_EDP_TO_LVDS_SW, // eDP-to-LVDS translator which requires AMD SW init DDI_AUTO_DETECT, // VBIOS auto detect connector type @@ -162,15 +164,17 @@ } fsp_ddi_descriptor; /* - * Mendocino DXIO Descriptor: Used for assigning lanes to PCIe engines, configure + * Morgana DXIO Descriptor: Used for assigning lanes to PCIe engines, configure * bifurcation and other settings. Beware that the lane numbers in here are the * logical and not the physical lane numbers! * - * Mendocino DXIO logical lane to physical PCIe lane mapping: + * Morgana DXIO logical lane to physical PCIe lane mapping: * * logical | physical * --------|------------ * [00:03] | GPP[03:00] + * [08:09] | GPP[08:09] + * [12:19] | GPP[12:19] * * Different ports mustn't overlap or be assigned to the same lane(s). Within * ports with the same width the one with a higher start logical lane number @@ -183,7 +187,7 @@ uint8_t end_logical_lane; // End lane of the pci device uint8_t gpio_group_id; // GPIO number used as reset uint32_t port_present :1; // Should be TRUE if train link - uint32_t reserved_3 :7; + uint32_t :7; uint32_t device_number :5; // Desired root port device number uint32_t function_number :3; // Desired root port function number uint32_t link_speed_capability :2; // See dxio_link_speed_cap @@ -193,14 +197,14 @@ uint32_t link_aspm_L1_1 :1; // En/Dis root port capabilities for L1.1 uint32_t link_aspm_L1_2 :1; // En/Dis root port capabilities for L1.2 uint32_t clk_req :4; // See cpm_clk_req - uint8_t link_hotplug; // Currently unused by FSP - uint8_t slot_power_limit; // Currently unused by FSP - uint32_t slot_power_limit_scale :2; // Currently unused by FSP - uint32_t reserved_4 :6; - uint32_t link_compliance_mode :1; // Currently unused by FSP - uint32_t link_safe_mode :1; // Currently unused by FSP - uint32_t sb_link :1; // Currently unused by FSP - uint32_t clk_pm_support :1; // Currently unused by FSP + uint8_t link_hotplug; // Hotplug control + uint8_t slot_power_limit; // PCIe slot power limit + uint32_t slot_power_limit_scale :2; // PCIe slot power limit scale + uint32_t :6; + uint32_t link_compliance_mode :1; // Force port into compliance mode + uint32_t link_safe_mode :1; // Safe mode capability + uint32_t sb_link :1; // Link type + uint32_t clk_pm_support :1; // Clock power management support uint32_t channel_type :3; // See dxio_sata_channel_type uint32_t turn_off_unused_lanes :1; // Power down lanes if device not present uint8_t reserved[4]; -- To view, visit https://review.coreboot.org/c/coreboot/+/69704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic893526789c05a298965702114d4a814466a5742 Gerrit-Change-Number: 69704 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange [View Less]

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[S] Change in coreboot[master]: util/amdfwutil: Add some types to both LVL
by Karthik Ramasubramanian (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Arthur Heymans, Marvin Drees. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68120 ) Change subject: util/amdfwutil: Add some types to both LVL ...................................................................... Patch Set 2: (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/68120/comment/dcaa661e_f7fe9dc6 PS2, Line 239: PSP_BOTH_AB > I think most things … [View More]

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coreboot-gerrit November 2022