coreboot-gerrit November 2022

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[S] Change in coreboot[master]: arch/x86: Disable clang build if using verstage_before_bootblock
by Martin Roth (Code Review) 16 Nov '22

16 Nov '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69701 ) Change subject: arch/x86: Disable clang build if using verstage_before_bootblock ...................................................................... arch/x86: Disable clang build if using verstage_before_bootblock Clang isn't working so well with the ARM code yet. This is still breaking builders after fixing the compiler warnings. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I2653edae0b89f75ef7d06a1be523585ff66a3b89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69701 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/arch/x86/Kconfig 1 file changed, 19 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Fred Reitberger: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index f7b9250..ef08f56 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -33,7 +33,7 @@ select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select ARCH_SUPPORTS_CLANG + select ARCH_SUPPORTS_CLANG if !VBOOT_STARTS_BEFORE_BOOTBLOCK # stage selectors for x64 -- To view, visit https://review.coreboot.org/c/coreboot/+/69701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2653edae0b89f75ef7d06a1be523585ff66a3b89 Gerrit-Change-Number: 69701 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: arch/x86: Disable clang build if using verstage_before_bootblock
by Martin Roth (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Martin L Roth. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69701 ) Change subject: arch/x86: Disable clang build if using verstage_before_bootblock ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Submitting early as final fix for the coreboot build. -- To view, visit https://review.coreboot.org/c/coreboot/+/69701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2653edae0b89f75ef7d06a1be523585ff66a3b89 Gerrit-Change-Number: 69701 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Wed, 16 Nov 2022 15:22:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Documentation: Add some more acronyms to the list
by Felix Held (Code Review) 16 Nov '22

16 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67330 ) Change subject: Documentation: Add some more acronyms to the list ...................................................................... Documentation: Add some more acronyms to the list Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I417bb151afcb3e996d9a12b2274ef02f2126bc7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67330 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M Documentation/acronyms.md 1 file changed, 59 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Nicholas Chin: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/Documentation/acronyms.md b/Documentation/acronyms.md index 83b61a3..6b88b4c 100644 --- a/Documentation/acronyms.md +++ b/Documentation/acronyms.md @@ -11,6 +11,7 @@ `acpihelp _XXX` * 2FA - [**Two-factor Authentication**](https://en.wikipedia.org/wiki/Multi-factor_authentication) * 4G - In coreboot, this typically refers to the 4 gibibyte boundary of 32-bit addressable memory space. + Better abbreviated as 4GiB * 5G - Telecommunication: [**Fifth-Generation Cellular Network**](https://en.wikipedia.org/wiki/5G) ## A @@ -45,6 +46,10 @@ * ALIB - AMD: ACPI-ASL Library * ALS - [**Ambient Light Sensor**](https://en.wikipedia.org/wiki/Ambient_light_sensor) * ALU - [**Arithmetic Logic Unit**](https://en.wikipedia.org/wiki/Arithmetic_logic_unit) +* AMBA - ARM: [**Advanced Microcontroller Bus + Architecture**](https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_…: + An open standard to connect and manage functional blocks in an SoC + (System on a Chip) * AMD64 - Another name for [**x86-64**](https://en.wikipedia.org/wiki/X86-64) * AMPL - AMD: [**Advanced Platform Management Link**](https://web.archive.org/web/20220509053546/https://developer.amd.co… - Also referred to as SBI: Sideband Interface @@ -53,8 +58,8 @@ * AOAC - AMD: Always On, Always Connected * AP - Application processor - The main processor on the board (as opposed to the embedded controller or other processors that may be on - the system), any cores in processor chip that isn’t the BSP - Boot - Strap Processor. + the system), any cores in the processor chip that aren't the BSP (Boot + Strap Processor). * APCB - AMD: AMD PSP Customization Block * API - [**Application Programming Interface**](https://en.wikipedia.org/wiki/API) * APIC - [**Advanced Programmable Interrupt @@ -123,6 +128,7 @@ stored as a single object, this was co-opted by the open source communities to mean any proprietary binary file that is not available as source code. +* BM - [**Bus Master**](https://en.wikipedia.org/wiki/Bus_mastering) * BMC - [**Baseboard Management Controller**](https://en.wikipedia.org/wiki/Intelligent_Platform_Management… * BMP - [**Bitmap**](https://en.wikipedia.org/wiki/BMP_file_format) * BOM - [**Bill of Materials**](https://en.wikipedia.org/wiki/Bill_of_materials) @@ -165,7 +171,8 @@ * CID - [**Coverity ID**](https://en.wikipedia.org/wiki/Coverity) * CIM - [**Common Information Model**](https://www.dmtf.org/standards/cim) * CISC - [**Complex Instruction Set Computer**](https://en.wikipedia.org/wiki/Complex_instruction_set_computer) -* CL - Change List - A git patch in gerrit +* CL - ChangeList - Another name for a patch or commit. This seems to be + Perforce notation. * CLK - Clock - Used when there isn't enough room for 2 additional characters - similar to RST, for people who hate vowels. * CML - Intel: [**Comet Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/comet_lake) @@ -180,6 +187,7 @@ * CNVi - Intel: [**Connectivity Integration**](https://en.wikipedia.org/wiki/CNVi) * CPL - x86: Current Privilege Level - Privilege levels range from 0-3; lower numbers are more privileged. * CPLD - [**Complex Programmable Logic Device**](https://en.wikipedia.org/wiki/Complex_programmable_logic_device) +* CPPC - AMD: Collaborative Processor Performance Controls * CPS - Characters Per Second * CPU - [**Central Processing Unit**](http://en.wikipedia.org/wiki/Central_processing_unit) @@ -196,12 +204,14 @@ * CSI - MIPI: [**Camera Serial Interface**](https://en.wikipedia.org/wiki/Camera_Serial_Interface) * CSME - Intel: Converged Security and Management Engine +* CTLE - Intel: Continuous Time Linear Equalization * CVE - [**Common Vulnerabilities and Exposures**](https://en.wikipedia.org/wiki/Common_Vulnerabilities_and_Expos… -* CZN - AMD: Cezanne - CPU Family 19h, Model 50h +* CZN - AMD: [**Cezanne**](https://en.wikichip.org/wiki/amd/cores/cezanne) - CPU Family 19h, Model 50h ## D +* D$ - Data Cache * D-States - [**ACPI Device power states**](https://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_In… D0-D3 - These are device specific power states, with each higher @@ -223,6 +233,8 @@ * DDC - [**Display Data Channel**](https://en.wikipedia.org/wiki/Display_Data_Channel) * DDI - Intel: Digital Display Interface * DDR - [**Double Data Rate**](https://en.wikipedia.org/wiki/Double_data_rate) +* DEVAPC - Mediatek: Device Access Permission Control +* DFP - USB: Downstream Facing port * DHCP - [**Dynamic Host Configuration Protocol**](https://en.wikipedia.org/wiki/Dynamic_Host_Configuration_Protoc… * DID - Device Identifier * DIMM - [**Dual Inline Memory Module**](https://en.wikipedia.org/wiki/DIMM) @@ -243,6 +255,7 @@ * DNV - Intel: [**Denverton**](https://en.wikichip.org/wiki/intel/cores/denverton) * DOS - Disk Operating System * DP - DisplayPort +* DPM - Mediatek: DRAM Power Manager * DPTF - Intel: Dynamic Power and Thermal Framework * DRAM - Memory: [**Dynamic Random Access Memory**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory) * DRTM - Dynamic Root of Trust for Measurement @@ -250,7 +263,10 @@ data-in pin is generally referred to as D, and the data-out pin is Q, thus the IO Data signal lines are referred to as DQ lines. * DQS - Memory: Data Q Strobe - Data valid signal for DDR memory. -* DRM - [**Digital Rights Management**](https://en.wikipedia.org/wiki/Digital_rights_management) +* DRM - [**Digital Rights + Management**](https://en.wikipedia.org/wiki/Digital_rights_management) +* DRP - USB: Port than can be switched between either a Downstream facing (DFP) or + an Upstream Facing (UFP). * DRQ - DMA Request * DRTU - Intel: Diagnostics and Regulatory Testing Utility * DSDT - The [**Differentiated System Descriptor @@ -262,12 +278,15 @@ * DSL - [**Digital subscriber line**](https://en.wikipedia.org/wiki/Digital_subscriber_line) * DSP - [**Digital Signal Processor**](https://en.wikipedia.org/wiki/Digital_signal_processor) * DTB - U-Boot: Device Tree Binary -* dTPM - Discrete Trusted Platform Module +* dTPM - Discrete TPM (Trusted Platform Module) - A separate TPM chip, + vs Integrated TPMs or fTPMs (Firmware TPMs). * DTS - U-Boot: Device Tree Source * DVFS - ARM: Dynamic Voltage and Frequency Scaling * DVI - [**Digital Video Interface**](https://en.wikipedia.org/wiki/Digital_Visual_Interface) * DVT - Production Timeline: Design Validation Test -* DW - DesignWare +* DW - DesignWare: A portfolio of silicon IP blocks for sale by the + Synopsys company. Includes blocks like USB, MIPI, PCIe, HDMI, SATA, + I2c, memory controllers and more. * DXE - UEFI: [**Driver Execution Environment**](https://en.wikipedia.org/wiki/Unified_Extensible_Firmware_In… * DXIO - AMD: Distributed CrossBar I/O @@ -283,7 +302,7 @@ Out**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Extended_… - A DRAM standard introduced in 1994 that improved upon, but was backwards compatible with FPM (Fast Page Mode) memory. -* EDP - [**Embedded DisplayPort**](DisplayPort) +* eDP - [**Embedded DisplayPort**](https://en.wikipedia.org/wiki/DisplayPort#eDP) * EDS - Intel: External Design Specification * EEPROM - [**Electrically Erasable Programmable ROM**](https://en.wikipedia.org/wiki/EEPROM) (common mistake: electrical erasable programmable ROM). @@ -340,7 +359,9 @@ * FSB - [**Front-Side Bus**](https://en.wikipedia.org/wiki/Front-side_bus) * FSP - Intel: Firmware Support Package * FTP - Network Protocol: [**File Transfer Protocol**](https://en.wikipedia.org/wiki/File_Transfer_Protocol) -* FTPM - Firmware TPM +* fTPM - Firmware TPM (Trusted Platform Module). This is a TPM that is + based in firmware instead of actual hardware. It typically runs in + some sort of TEE (Trusted Execution Environment). ## G @@ -407,6 +428,7 @@ ## I +* I$ - Instruction Cache * I2C - **Inter-Integrated Circuit** is a bidirectional 2-wire bus for communication generally between different ICs on a circuit board. * [https://www.esacademy.com/en/library/technical-articles-and-documents/misce… @@ -540,6 +562,7 @@ * MCU - [**MicroController Unit**](https://en.wikipedia.org/wiki/Microcontroller) * MDFIO - Intel: Multi-Die Fabric IO +* MDN - AMD: Mendocino * ME - Intel: Management Engine * MEI - Intel: ME Interface (Previously known as HECI) * Memory training - the process of finding the best speeds, voltages, @@ -578,9 +601,7 @@ OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. Version 1.1 of the spec was released in 1994, and the 1.4 version was released in 1995. This has been - generally been - https://en.wikipedia.org/wiki/MultiProcessor_Specification by the ACPI - tables. + generally superseded by the ACPI tables. * MRC - Intel: Memory Reference Code * MSB - Most Significant Bit * MSI - Message Signaled Interrupt @@ -621,8 +642,8 @@ * ODH - GPIOs: Open Drain High - High is driven to the reference voltage, low is a high-impedance state * ODL - GPIOs: Open Drain Low - Low is driven to ground, High is a high-impedance state. -* ODM - Original Design Manufacturer -* OEM - Original Equipment Manufacturer +* ODM - [**Original Design Manufacturer**](https://en.wikipedia.org/wiki/Original_design_manufacturer) +* OEM - [**Original Equipment Manufacturer**](https://en.wikipedia.org/wiki/Original_equipment_manufactur… * OHCI - [**Open Host Controller Interface**](https://en.wikipedia.org/wiki/Host_Controller_Interface_%28USB… - non-proprietary USB Host controller for USB 1.1 (May also refer to @@ -669,7 +690,7 @@ function's configuration space from 256 bytes to 4K. * PCIe - [**PCI Express**](http://en.wikipedia.org/wiki/Pci_express) * PCMCIA: Personal Computer Memory Card International Association -* PCO - AMD: Picasso +* PCO - AMD: [**Picasso**](https://en.wikichip.org/wiki/amd/cores/picasso) * PCR: TPM: Platform Configuration Register * PD - GPIOs: Pull-Down - Setting the pin high drives it to the reference voltage. Setting it low drives it to ground through a resistor. * PD - Power Delivery - This is a specification for communicating power @@ -873,6 +894,7 @@ * SPI - [**Serial Peripheral Interface**](https://en.wikipedia.org/wiki/Serial_Peripheral_Interface) * SPL - AMD: Security Patch Level +* SPM - Mediatek: System Power Manager * SPMI - MIPI: System Power Management Interface * SRAM - Static Random Access Memory * SSD - Solid State Drive @@ -889,7 +911,9 @@ Bay**](https://en.wikipedia.org/wiki/SSI_CEB) * SSI-TEB - Physical board format: [**SSI Thin Electronics Bay**](https://en.wikipedia.org/wiki/SSI_CEB) +* SSP - [**Speech Signal Processor**](https://en.wikipedia.org/wiki/Speech_processing) * STAPM - AMD: Skin Temperature Aware Power Management +* STB - AMD: Smart Trace Buffer * SuperIO - The [**Super I/O**](https://en.wikipedia.org/wiki/Super_I/O) (SIO) device provides a system with any of a number of different peripherals. Most common are: A PS/2 Keyboard and mouse port, LPT @@ -909,7 +933,8 @@ * TDMA - Time-Division Multiple Access * TDP - [**Thermal Design Power**](https://en.wikipedia.org/wiki/Thermal_design_power) -* TEE - Trusted Execution Environment +* TEE - [**Trusted Execution + Environment**](https://en.wikipedia.org/wiki/Trusted_execution_environment) * TFTP - Network Protocol: Trivial File Transfer Protocol * TGL - Intel: Tigerlake * THC - Touch Host Controller @@ -919,6 +944,7 @@ * TLA - Three Letter Acronym * TLB - [**Translation Lookside Buffer**](https://en.wikipedia.org/wiki/Translation_lookaside_buffer) +* TME - Intel: Total Memory Encryption * TOCTOU - Time-Of-Check to Time-Of-Use * TOLUM - Top of Low Usable Memory * ToM - Top of Memory @@ -927,6 +953,7 @@ * TSC - [**Time Stamp Counter**](https://en.wikipedia.org/wiki/Time_Stamp_Counter) * TSEG - TOM (Top of Memory) Segment +* TSR - Temperature Sensor * TWAIN - Technology without an interesting name. * TX - Transmit * TXE - Intel: Trusted eXecution Engine @@ -940,6 +967,7 @@ * UDK - UEFI: UEFI Development Kit * UDP - User Datagram Protocol * UEFI - Unified Extensible Firmware Interface +* UFP - USB: Upstream Facing Port * UFS - Universal Flash storage * UHCI - USB: [**Universal Host Controller Interface**](https://en.wikipedia.org/wiki/Host_controller_interface_%28USB… @@ -989,6 +1017,7 @@ tablets, it's on the the side away from the screen. * WDT - [**WatchDog Timer**](https://en.wikipedia.org/wiki/Watchdog_timer) * WLAN - Wireless LAN (Local Area Network) +* WWAN - Telecommunication: Wireless WAN (Wide Area Network) * WP - Cache policy: [**Write-Protected**](https://en.wikipedia.org/wiki/Cache_%28computing%29) * WO - Write-only * WOL - [**Wake-on-LAN**](https://en.wikipedia.org/wiki/Wake-on-LAN) -- To view, visit https://review.coreboot.org/c/coreboot/+/67330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I417bb151afcb3e996d9a12b2274ef02f2126bc7d Gerrit-Change-Number: 67330 Gerrit-PatchSet: 5 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: arch/x86: Disable clang build if using verstage_before_bootblock
by Fred Reitberger (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Martin L Roth. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69701 ) Change subject: arch/x86: Disable clang build if using verstage_before_bootblock ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2653edae0b89f75ef7d06a1be523585ff66a3b89 Gerrit-Change-Number: 69701 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Wed, 16 Nov 2022 15:17:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: arch/arm/armv7: Don't set gcc specific options for clang builds
by Martin Roth (Code Review) 16 Nov '22

16 Nov '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69672 ) Change subject: arch/arm/armv7: Don't set gcc specific options for clang builds ...................................................................... arch/arm/armv7: Don't set gcc specific options for clang builds Clang doesn't understand the -Wa,-mno-warn-deprecated option. Remove it for now. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I9f91d6ec2db247e901ba9bc41bc4b888bbe43236 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69672 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/arch/arm/armv7/Makefile.inc 1 file changed, 22 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Arthur Heymans: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 66ddc98..5675a26 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -5,7 +5,10 @@ armv7-m_flags = -march=armv7-m $(armv7_flags) -D__COREBOOT_ARM_V7_M__ armv7-r_flags = -march=armv7-r $(armv7_flags) -D__COREBOOT_ARM_V7_R__ -armv7_asm_flags = -Wa,-mthumb -Wa,-mimplicit-it=always -Wa,-mno-warn-deprecated +armv7_asm_flags = -Wa,-mthumb -Wa,-mimplicit-it=always +ifeq ($(CONFIG_COMPILER_GCC),y) +armv7_asm_flags += -Wa,-mno-warn-deprecated +endif armv7-r_asm_flags = $(armv7-r_flags) $(armv7_asm_flags) ############################################################################### -- To view, visit https://review.coreboot.org/c/coreboot/+/69672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f91d6ec2db247e901ba9bc41bc4b888bbe43236 Gerrit-Change-Number: 69672 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices
by Sridhar Siricilla (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69680 ) Change subject: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69680/comment/756a0aba_c1a6b5ea PS1, Line 9: This patch skips setting D0I3 bit for all HECI devices by FSP. > > I don't have access to crosbug:200644229. […] Thanks for commit update and pushing the CL. I'm wondering how this CL applicable to MTL a https://review.coreboot.org/c/coreboot/+/69680/comment/a915aa0a_68f05bf0 PS1, Line 9: This patch skips setting D0I3 bit for all HECI devices by FSP. > > I don't have access to crosbug:200644229. […] Thanks for update. Considering the Arch change from ADL to MTL, the reported issue on ADL may not be applicable to MTL. We need to relook at the issue again on MTL. Commit Message: https://review.coreboot.org/c/coreboot/+/69680/comment/797d2206_3fa2a0b0 PS2, Line 10: : The learning being made from Alder Lake platform showed that the CSE : EOP cmd response time is highly nondeterministic and letting the EOP : cmd issued by FSP makes the response time even worse. : : The idea being pursued during Alder Lake platform is to let FSP skip sending the EOP cmd and coreboot sends it at the last minute : (late sending of EOP) to ensure there is ample time for CSE to come : to a state where the response to the EOP is almost immediate. Thanks for commit update. Since architectural change from ADL to MTL, I'm not sure if this is applicable to MTL. -- To view, visit https://review.coreboot.org/c/coreboot/+/69680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c3765ce41f192ab5f5ff176e0a2b49b312d18d2 Gerrit-Change-Number: 69680 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 16 Nov 2022 15:14:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512
by Werner Zeh (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Mario Scheithauer, Arthur Heymans. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69384 ) Change subject: drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512 ...................................................................... Patch Set 10: (1 comment) Patchset: PS2: > The chosen subdirectory 'phy' might cause confusions as we are here dealing with an ethernet PHY. […] A short discussion on IRC showed that drivers/net/phy/ is a good location for this driver. Mario, would you please move accordingly? -- To view, visit https://review.coreboot.org/c/coreboot/+/69384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24011860caa7bb206770f9779eb34b689293db10 Gerrit-Change-Number: 69384 Gerrit-PatchSet: 10 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 16 Nov 2022 15:10:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/ehl: Add MDIO operation to TSN GbE device
by Mario Scheithauer (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Angel Pons, Arthur Heymans, Lean Sheng Tan. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69383 ) Change subject: soc/intel/ehl: Add MDIO operation to TSN GbE device ...................................................................... Patch Set 10: (2 comments) File src/soc/intel/elkhartlake/mdio.c: https://review.coreboot.org/c/coreboot/+/69383/comment/f15dee45_26ebf60b PS7, Line 68: == CB_ERR > nit: != CB_SUCCESS is preferable as it handles the other options in enum cb_err (even though they ar […] Done File src/soc/intel/elkhartlake/tsn_gbe.c: https://review.coreboot.org/c/coreboot/+/69383/comment/48934118_33b8c37b PS10, Line 144: phy_gmii_ready(mmio_base) != CB_SUCCESS > Sorry, I had overlooked that. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa Gerrit-Change-Number: 69383 Gerrit-PatchSet: 10 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 16 Nov 2022 15:08:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/ehl: Add MDIO operation to TSN GbE device
by Mario Scheithauer (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Angel Pons, Arthur Heymans, Lean Sheng Tan. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69383 ) Change subject: soc/intel/ehl: Add MDIO operation to TSN GbE device ...................................................................... Patch Set 10: (1 comment) File src/soc/intel/elkhartlake/tsn_gbe.c: https://review.coreboot.org/c/coreboot/+/69383/comment/67924cb2_f02ce802 PS10, Line 144: phy_gmii_ready(mmio_base) != CB_SUCCESS Sorry, I had overlooked that. -- To view, visit https://review.coreboot.org/c/coreboot/+/69383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa Gerrit-Change-Number: 69383 Gerrit-PatchSet: 10 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 16 Nov 2022 15:07:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/phy/m88e1512: Provide functionality to customize LED status
by build bot (Jenkins) (Code Review) 16 Nov '22

16 Nov '22

Attention is currently required from: Mario Scheithauer, Werner Zeh. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69386 ) Change subject: drivers/phy/m88e1512: Provide functionality to customize LED status ...................................................................... Patch Set 13: Verified+1 (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163788): https://review.coreboot.org/c/coreboot/+/69386/comment/539c4b35_64df866e PS13, Line 14: https://web.archive.org/web/20221109080111/https://www.marvell.com/content/… Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia71c43f4286f9201f03cb759252ebb405ab81904 Gerrit-Change-Number: 69386 Gerrit-PatchSet: 13 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 16 Nov 2022 15:05:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2022