coreboot-gerrit November 2022

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[S] Change in coreboot[master]: soc/intel/meteorlake: Check MANUF_LOCK when logging manufacturing mode
by Ivy Jian (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Tarun Tuli, Ravishankar Sarawadi, Sridhar Siricilla. Ivy Jian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69578 ) Change subject: soc/intel/meteorlake: Check MANUF_LOCK when logging manufacturing mode ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I495a7d8730716fc92e8c57b2caef73e8bb44d30b Gerrit-Change-Number: 69578 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 00:54:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/meteorlake: Update CSE firmware status registers
by Eric Lai (Code Review) 17 Nov '22

17 Nov '22

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69577 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/meteorlake: Update CSE firmware status registers ...................................................................... soc/intel/meteorlake: Update CSE firmware status registers The patch updates HFSTS4, HFSTS5 & HFSTS6 register definitions as per MTL Intel CSME BIOS Specification (doc# 729124). Also, the patch logs the firmware status details as per the new register definition. TEST=Build and boot the coreboot on Rex Snippet from coreboot log with the patch: [DEBUG] ME: CPU Debug Disabled : NO [DEBUG] ME: TXT Support : NO Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ibee9a0955efc22ea0d9fdbba2d09e57d8851e22e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69577 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/meteorlake/me.c 1 file changed, 44 insertions(+), 31 deletions(-) Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved Jamie Ryu: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/me.c b/src/soc/intel/meteorlake/me.c index ea94902..7d89590 100644 --- a/src/soc/intel/meteorlake/me.c +++ b/src/soc/intel/meteorlake/me.c @@ -34,15 +34,9 @@ union me_hfsts4 { uint32_t data; struct { - uint32_t rsvd0 : 9; - uint32_t enforcement_flow : 1; - uint32_t sx_resume_type : 1; - uint32_t rsvd1 : 1; - uint32_t tpms_disconnected : 1; - uint32_t rvsd2 : 1; - uint32_t fwsts_valid : 1; - uint32_t boot_guard_self_test : 1; - uint32_t rsvd3 : 16; + uint32_t rsvd0 : 1; + uint32_t flash_log_exist : 1; + uint32_t rsvd1 : 30; } __packed fields; }; @@ -57,9 +51,14 @@ uint32_t acm_done_sts : 1; uint32_t timeout_count : 7; uint32_t scrtm_indicator : 1; - uint32_t inc_boot_guard_acm : 4; - uint32_t inc_key_manifest : 4; - uint32_t inc_boot_policy : 4; + uint32_t txt_support : 1; + uint32_t btg_profile : 3; + uint32_t cpu_debug_disabled : 1; + uint32_t bsp_init_disabled : 1; + /* BSP Boot Policy Manifest Execution Status */ + uint32_t bsp_bpm_exe_sts : 1; + uint32_t btg_token_applied : 1; + uint32_t btg_status : 4; uint32_t rsvd0 : 2; uint32_t start_enforcement : 1; } __packed fields; @@ -69,24 +68,11 @@ union me_hfsts6 { uint32_t data; struct { - uint32_t force_boot_guard_acm : 1; - uint32_t cpu_debug_disable : 1; - uint32_t bsp_init_disable : 1; - uint32_t protect_bios_env : 1; - uint32_t rsvd0 : 2; - uint32_t error_enforce_policy : 2; - uint32_t measured_boot : 1; - uint32_t verified_boot : 1; - uint32_t boot_guard_acmsvn : 4; - uint32_t kmsvn : 4; - uint32_t bpmsvn : 4; - uint32_t key_manifest_id : 4; - uint32_t boot_policy_status : 1; - uint32_t error : 1; - uint32_t boot_guard_disable : 1; - uint32_t fpf_disable : 1; + uint32_t rsvd0 : 21; + uint32_t manuf_lock : 1; + uint32_t rsvd2 : 8; uint32_t fpf_soc_lock : 1; - uint32_t txt_support : 1; + uint32_t sx_resume_type : 1; } __packed fields; }; @@ -158,9 +144,9 @@ printk(BIOS_DEBUG, "ME: Enhanced Debug Mode : %s\n", hfsts1.fields.invoke_enhance_dbg_mode ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: CPU Debug Disabled : %s\n", - hfsts6.fields.cpu_debug_disable ? "YES" : "NO"); + hfsts5.fields.cpu_debug_disabled ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: TXT Support : %s\n", - hfsts6.fields.txt_support ? "YES" : "NO"); + hfsts5.fields.txt_support ? "YES" : "NO"); } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/69577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibee9a0955efc22ea0d9fdbba2d09e57d8851e22e Gerrit-Change-Number: 69577 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices
by Eric Lai (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Sridhar Siricilla. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69680 ) Change subject: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c3765ce41f192ab5f5ff176e0a2b49b312d18d2 Gerrit-Change-Number: 69680 Gerrit-PatchSet: 3 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 00:52:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: Documentation/sbom: Add SBOM Documentation
by Maximilian Brune (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Patrick Rudolph, Richard Hughes, Maximilian Brune, Angel Pons. Hello build bot (Jenkins), Richard Hughes, Nicholas Chin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68995 to look at the new patch set (#9). Change subject: Documentation/sbom: Add SBOM Documentation ...................................................................... Documentation/sbom: Add SBOM Documentation Change-Id: I39fbcba60a0fbdbed9f662119ed7692c0a0fd30e Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M Documentation/index.md A Documentation/sbom/sbom.md A Documentation/sbom/sbom_generation.plantuml A Documentation/sbom/sbom_generation.svg 4 files changed, 289 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/68995/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/68995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39fbcba60a0fbdbed9f662119ed7692c0a0fd30e Gerrit-Change-Number: 68995 Gerrit-PatchSet: 9 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Richard Hughes <richard(a)hughsie.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Richard Hughes <richard(a)hughsie.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Enable FSP multiphase
by Tarun Tuli (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Kapil Porwal, John Zhao, Sridhar Siricilla. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67741 ) Change subject: soc/intel/meteorlake: Enable FSP multiphase ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I759c0ecee29c07bae4abe6b56d015e7253bd49fe Gerrit-Change-Number: 67741 Gerrit-PatchSet: 3 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 00:44:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Enable FSP multiphase
by Eric Lai (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, John Zhao, Sridhar Siricilla. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67741 ) Change subject: soc/intel/meteorlake: Enable FSP multiphase ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I759c0ecee29c07bae4abe6b56d015e7253bd49fe Gerrit-Change-Number: 67741 Gerrit-PatchSet: 3 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 00:44:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/acpi: Implement DTTS Proposal
by Tim Van Patten (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, Matt DeVillier, Paul Menzel, Eric Lai, Martin Roth, Eric Peers, LeilaCY Lin, Jason Glenesk, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 ) Change subject: soc/amd/common/acpi: Implement DTTS Proposal ...................................................................... Patch Set 53: (10 comments) Patchset: PS53: Thanks for bearing with us. I think this is getting pretty close now. File src/soc/amd/common/acpi/DTTS.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/8bc003d9_e4aac501 PS39, Line 15: /* If _SB.DDEF is not present, DPTC is not enabled so return early. */ : If (!CondRefOf (\_SB.DDEF)) : { : Return (Zero) : } > Based on your suggestion, I need your help to clarify the design thinking as below. […] Yes, I think what you have is close to what I was describing. I do have a comment above about your implementation though. I'm going to close this comment, and we can discuss the details further in the other comment. https://review.coreboot.org/c/coreboot/+/68471/comment/4876def3_36fedc58 PS39, Line 21: //Set table A as default table after power on SUT : If (\_SB.PRTN == 7) : { : \_SB.DDEF() : Store(0,\_SB.PRTN) : Return (Zero) : } > As thermal team's request, table A would be the first table during power on. […] Is it possible to power on with the lid closed, in laptop mode, or with the sensor >45C? If so, the only signal that would be received again (while still in that state) is the temperature changing, since the "lid closed" or "laptop mode" values won't be sent again if they aren't changing. It's also unknown how long it would take for the temperature to change (though it may not matter). For example, that would mean the device could possibly be running with Table A when powered on with the lid closed until the temperature changes, in which case Table C will be loaded regardless of what the current temperature is since the previous table was A. Since the design is for the EC to always send a signal when the temperate changes by 1 deg (as for as I know, anyway), this may be a non-issue because the DPTC values will be updated before anything gets too hot. Do you know how the EC temperature signals working? Are there CLs to enable this signalling to the AP, or is that unnecessary? File src/soc/amd/common/acpi/dptc.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/36e3ede9_42e21c57 PS12, Line 44: TIN4 > I created DTTS.asl and put it under src/soc/amd/common/acpi/. […] Done File src/soc/amd/common/acpi/dptc.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/60640f38_78394a59 PS21, Line 47: 123 > There is an offset of temperature value stored in mapped memory. […] Ack https://review.coreboot.org/c/coreboot/+/68471/comment/eb9cd23d_03095be5 PS21, Line 47: 123 > There is an offset of temperature value stored in mapped memory. […] Ack https://review.coreboot.org/c/coreboot/+/68471/comment/1f7db687_c993a3e2 PS21, Line 48: (\_SB.PCI0.LPCB.EC0.PRTN == 3) || // Previous table is D : (\_SB.PCI0.LPCB.EC0.PRTN == 5)) // Previous table is F > Follow thermal team's proposal, A C E are temperature release table, B D E are temperature over tabl […] Ack https://review.coreboot.org/c/coreboot/+/68471/comment/2148384d_aacbe59d PS21, Line 56: 118 > Add a comment indicating this offset is how the temperature values here are determined on the first […] Ack https://review.coreboot.org/c/coreboot/+/68471/comment/356f5ab8_40899581 PS21, Line 57: (\_SB.PCI0.LPCB.EC0.PRTN == 2) || // Previous table is C : (\_SB.PCI0.LPCB.EC0.PRTN == 4)) // Previous table is E > Follow thermal team's proposal. […] Ack File src/soc/amd/common/acpi/dptc.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/17ddc4f6_60a3da2f PS53, Line 42: #if CONFIG(FEATURE_DYNAMIC_DPTC) : #include <soc/amd/common/acpi/DTTS.asl> : #endif Can this `#include` be moved to the top of the file? I would then expect this to just be: ``` If (CondRefOf (\_SB.DTTS)) { \_SB.DTTS() Return (Zero) } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 53 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 17 Nov 2022 00:44:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/herobrine: Remove NVMe from device tree
by Shelley Chen (Code Review) 17 Nov '22

17 Nov '22

Shelley Chen has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/68571 ) Change subject: mb/google/herobrine: Remove NVMe from device tree ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/68571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I802dd1361bc56a24ab3d65e6782bc611b7b75ee3 Gerrit-Change-Number: 68571 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-MessageType: revert

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[S] Change in coreboot[master]: Revert "mb/google/herobrine: Remove NVMe from device tree"
by Shelley Chen (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Julius Werner. Hello build bot (Jenkins), Julius Werner, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/69720 to review the following change. Change subject: Revert "mb/google/herobrine: Remove NVMe from device tree" ...................................................................... Revert "mb/google/herobrine: Remove NVMe from device tree" This reverts commit d164feb72602da958b644643b44e754f04a1f281. Reason for revert: Herobrine program decided that we wanted to be able to boot from NVMe if one exists. Change-Id: I2d3217c514734608e2ff049b620f4c7acf86de89 --- M src/mainboard/google/herobrine/devicetree.cb 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/69720/1 diff --git a/src/mainboard/google/herobrine/devicetree.cb b/src/mainboard/google/herobrine/devicetree.cb index e23782f..34360b7 100644 --- a/src/mainboard/google/herobrine/devicetree.cb +++ b/src/mainboard/google/herobrine/devicetree.cb @@ -2,4 +2,7 @@ chip soc/qualcomm/sc7280 device cpu_cluster 0 on end + device domain 0 on + device pci 00.0 on end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/69720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d3217c514734608e2ff049b620f4c7acf86de89 Gerrit-Change-Number: 69720 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: Revert "soc/qualcomm/sc7280: Remove NVMe init"
by Shelley Chen (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Julius Werner. Hello build bot (Jenkins), Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69719 to look at the new patch set (#2). Change subject: Revert "soc/qualcomm/sc7280: Remove NVMe init" ...................................................................... Revert "soc/qualcomm/sc7280: Remove NVMe init" This reverts commit 1b07797a7b79ea6c11421b61b9cf14b92cb91c66. Reason for revert: Herobrine program decided that we wanted to be able to boot from NVMe if one exists. Change-Id: If675947026095d16b72bdb0f3ec790e583523465 --- M src/soc/qualcomm/sc7280/Kconfig M src/soc/qualcomm/sc7280/soc.c 2 files changed, 19 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/69719/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If675947026095d16b72bdb0f3ec790e583523465 Gerrit-Change-Number: 69719 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2022