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[M] Change in coreboot[master]: [TEST] test firmware for crasskneto
by Ren Kuo (Code Review) 17 Nov '22

17 Nov '22

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69693 ) Change subject: [TEST] test firmware for crasskneto ...................................................................... [TEST] test firmware for crasskneto Change-Id: I6b9c90abe562768ea2afff5608a8cfac764569d5 --- M src/mainboard/google/brya/variants/craask/fw_config.c M src/mainboard/google/brya/variants/craask/gpio.c M src/mainboard/google/brya/variants/craask/overridetree.cb 3 files changed, 151 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/69693/1 diff --git a/src/mainboard/google/brya/variants/craask/fw_config.c b/src/mainboard/google/brya/variants/craask/fw_config.c index 5b8f058..8ac399b 100644 --- a/src/mainboard/google/brya/variants/craask/fw_config.c +++ b/src/mainboard/google/brya/variants/craask/fw_config.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <boardid.h> #include <console/console.h> #include <fw_config.h> @@ -51,27 +52,33 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { - if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { - printk(BIOS_INFO, "Disable LTE-related GPIO pins on craask.\n"); - gpio_padbased_override(padbased_table, lte_disable_pads, + + const uint32_t id = board_id(); + + if (id < 0x20) { + + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { + printk(BIOS_INFO, "Disable LTE-related GPIO pins on craask.\n"); + gpio_padbased_override(padbased_table, lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); - } + } - if (fw_config_probe(FW_CONFIG(WFC, WFC_ABSENT))) { - printk(BIOS_INFO, "Disable MIPI WFC GPIO pins.\n"); - gpio_padbased_override(padbased_table, wfc_disable_pads, + if (fw_config_probe(FW_CONFIG(WFC, WFC_ABSENT))) { + printk(BIOS_INFO, "Disable MIPI WFC GPIO pins.\n"); + gpio_padbased_override(padbased_table, wfc_disable_pads, ARRAY_SIZE(wfc_disable_pads)); - } + } - if (fw_config_probe(FW_CONFIG(SD_CARD, SD_ABSENT))) { - printk(BIOS_INFO, "Disable SD card GPIO pins.\n"); - gpio_padbased_override(padbased_table, sd_disable_pads, + if (fw_config_probe(FW_CONFIG(SD_CARD, SD_ABSENT))) { + printk(BIOS_INFO, "Disable SD card GPIO pins.\n"); + gpio_padbased_override(padbased_table, sd_disable_pads, ARRAY_SIZE(sd_disable_pads)); - } + } - if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) { - printk(BIOS_INFO, "Disable Stylus GPIO pins.\n"); - gpio_padbased_override(padbased_table, stylus_disable_pads, + if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) { + printk(BIOS_INFO, "Disable Stylus GPIO pins.\n"); + gpio_padbased_override(padbased_table, stylus_disable_pads, ARRAY_SIZE(stylus_disable_pads)); + } } } diff --git a/src/mainboard/google/brya/variants/craask/gpio.c b/src/mainboard/google/brya/variants/craask/gpio.c index f075ba0..fa0a6ee 100644 --- a/src/mainboard/google/brya/variants/craask/gpio.c +++ b/src/mainboard/google/brya/variants/craask/gpio.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <boardid.h> #include <commonlib/helpers.h> #include <soc/gpio.h> @@ -41,6 +42,57 @@ PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), }; +/* Pad configuration in ramstage for craaskneo/craaskino, board id >= 0x20 */ +static const struct pad_config override_gpio_table_extend[] = { + + /* Configure the WWAN GPIO pads */ + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* E13 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO_LOCK(GPP_E13, 1, LOCK_CONFIG), + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), + + /* Configure the WLAN GPIO pads */ + /* D7 : WLAN_CLKREQ_ODL */ + PAD_NC(GPP_D7, NONE), + /* H3 : WLAN_PCIE_WAKE_ODL */ + PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG), + + /* Configure the SSD GPIO pads */ + /* B4 : SSD_PERST_L */ + PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), + /* D6 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D11 : EN_PP3300_SSD */ + PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG), + /* E17 : SSD_PLN_L */ + PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG), + + /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ + /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), + /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), + /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), + /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), + /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* SSP_RXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), +}; + + /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* F12 : GSXDOUT ==> WWAN_RST_L */ @@ -67,25 +119,85 @@ PAD_CFG_GPO(GPP_H13, 1, DEEP), }; +/* Early pad configuration in bootblock for craaskneo/craaskino, board id >= 0x20 */ +static const struct pad_config early_gpio_table_extend[] = { + /* B4 : SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* F12 : GSXDOUT ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* E13 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_E13, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* D11 : EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), +}; + static const struct pad_config romstage_gpio_table[] = { /* H12 : UART0_RTS# ==> SD_PERST_L */ PAD_CFG_GPO(GPP_H12, 1, DEEP), }; + +/* Pad configuration in romstage for craaskneo/craaskino, board id >= 0x20 */ +static const struct pad_config romstage_gpio_table_extend[] = { + /* B4 : SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 1, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { + const uint32_t id = board_id(); + + if (id >= 0x20) { + *num = ARRAY_SIZE(override_gpio_table_extend); + return override_gpio_table_extend; + } + *num = ARRAY_SIZE(override_gpio_table); return override_gpio_table; } const struct pad_config *variant_early_gpio_table(size_t *num) { + const uint32_t id = board_id(); + + if (id >= 0x20) { + *num = ARRAY_SIZE(early_gpio_table_extend); + return early_gpio_table_extend; + } + *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } const struct pad_config *variant_romstage_gpio_table(size_t *num) { + const uint32_t id = board_id(); + + if (id >= 0x20) { + *num = ARRAY_SIZE(romstage_gpio_table_extend); + return romstage_gpio_table_extend; + } + *num = ARRAY_SIZE(romstage_gpio_table); return romstage_gpio_table; } diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index 6db23d4..db9e363 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -444,6 +444,14 @@ end probe SD_CARD SD_GL9750S end + device ref pcie_rp9 on + # Enable NVMe SSD PCIe 9-12 using clk 1 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0] -- To view, visit https://review.coreboot.org/c/coreboot/+/69693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b9c90abe562768ea2afff5608a8cfac764569d5 Gerrit-Change-Number: 69693 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: :q
by build bot (Jenkins) (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Tarun Tuli. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69691 ) Change subject: :q ...................................................................... Patch Set 1: (3 comments) File src/mainboard/google/brya/variants/craask/gpio.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163857): https://review.coreboot.org/c/coreboot/+/69691/comment/3b8df75e_d8355962 PS1, Line 48: /* Configure the WWAN GPIO pads */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163857): https://review.coreboot.org/c/coreboot/+/69691/comment/48c83922_563244de PS1, Line 60: /* Configure the WLAN GPIO pads */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163857): https://review.coreboot.org/c/coreboot/+/69691/comment/2e6d8e7e_596e16d7 PS1, Line 66: /* Configure the SSD GPIO pads */ code indent should use tabs where possible -- To view, visit https://review.coreboot.org/c/coreboot/+/69691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaf4ace5e71b5b49d80ee177637f68f1d4a9536d Gerrit-Change-Number: 69691 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 03:23:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: test firmare for craaskneto
by Ren Kuo (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Tarun Tuli. Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69692 ) Change subject: test firmare for craaskneto ...................................................................... test firmare for craaskneto Change-Id: I0de54b8724eb23b19c7313c01b94f7edcbb2cbe3 --- M src/mainboard/google/brya/variants/craask/overridetree.cb 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/69692/1 diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index 6db23d4..db9e363 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -444,6 +444,14 @@ end probe SD_CARD SD_GL9750S end + device ref pcie_rp9 on + # Enable NVMe SSD PCIe 9-12 using clk 1 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0] -- To view, visit https://review.coreboot.org/c/coreboot/+/69692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0de54b8724eb23b19c7313c01b94f7edcbb2cbe3 Gerrit-Change-Number: 69692 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: :q
by Ren Kuo (Code Review) 17 Nov '22

17 Nov '22

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69691 ) Change subject: :q ...................................................................... :q Change-Id: Idaf4ace5e71b5b49d80ee177637f68f1d4a9536d --- M src/mainboard/google/brya/variants/craask/fw_config.c M src/mainboard/google/brya/variants/craask/gpio.c 2 files changed, 143 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/69691/1 diff --git a/src/mainboard/google/brya/variants/craask/fw_config.c b/src/mainboard/google/brya/variants/craask/fw_config.c index 5b8f058..8ac399b 100644 --- a/src/mainboard/google/brya/variants/craask/fw_config.c +++ b/src/mainboard/google/brya/variants/craask/fw_config.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <boardid.h> #include <console/console.h> #include <fw_config.h> @@ -51,27 +52,33 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { - if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { - printk(BIOS_INFO, "Disable LTE-related GPIO pins on craask.\n"); - gpio_padbased_override(padbased_table, lte_disable_pads, + + const uint32_t id = board_id(); + + if (id < 0x20) { + + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { + printk(BIOS_INFO, "Disable LTE-related GPIO pins on craask.\n"); + gpio_padbased_override(padbased_table, lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); - } + } - if (fw_config_probe(FW_CONFIG(WFC, WFC_ABSENT))) { - printk(BIOS_INFO, "Disable MIPI WFC GPIO pins.\n"); - gpio_padbased_override(padbased_table, wfc_disable_pads, + if (fw_config_probe(FW_CONFIG(WFC, WFC_ABSENT))) { + printk(BIOS_INFO, "Disable MIPI WFC GPIO pins.\n"); + gpio_padbased_override(padbased_table, wfc_disable_pads, ARRAY_SIZE(wfc_disable_pads)); - } + } - if (fw_config_probe(FW_CONFIG(SD_CARD, SD_ABSENT))) { - printk(BIOS_INFO, "Disable SD card GPIO pins.\n"); - gpio_padbased_override(padbased_table, sd_disable_pads, + if (fw_config_probe(FW_CONFIG(SD_CARD, SD_ABSENT))) { + printk(BIOS_INFO, "Disable SD card GPIO pins.\n"); + gpio_padbased_override(padbased_table, sd_disable_pads, ARRAY_SIZE(sd_disable_pads)); - } + } - if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) { - printk(BIOS_INFO, "Disable Stylus GPIO pins.\n"); - gpio_padbased_override(padbased_table, stylus_disable_pads, + if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) { + printk(BIOS_INFO, "Disable Stylus GPIO pins.\n"); + gpio_padbased_override(padbased_table, stylus_disable_pads, ARRAY_SIZE(stylus_disable_pads)); + } } } diff --git a/src/mainboard/google/brya/variants/craask/gpio.c b/src/mainboard/google/brya/variants/craask/gpio.c index f075ba0..fa0a6ee 100644 --- a/src/mainboard/google/brya/variants/craask/gpio.c +++ b/src/mainboard/google/brya/variants/craask/gpio.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <boardid.h> #include <commonlib/helpers.h> #include <soc/gpio.h> @@ -41,6 +42,57 @@ PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), }; +/* Pad configuration in ramstage for craaskneo/craaskino, board id >= 0x20 */ +static const struct pad_config override_gpio_table_extend[] = { + + /* Configure the WWAN GPIO pads */ + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* E13 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO_LOCK(GPP_E13, 1, LOCK_CONFIG), + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), + + /* Configure the WLAN GPIO pads */ + /* D7 : WLAN_CLKREQ_ODL */ + PAD_NC(GPP_D7, NONE), + /* H3 : WLAN_PCIE_WAKE_ODL */ + PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG), + + /* Configure the SSD GPIO pads */ + /* B4 : SSD_PERST_L */ + PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), + /* D6 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D11 : EN_PP3300_SSD */ + PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG), + /* E17 : SSD_PLN_L */ + PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG), + + /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ + /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), + /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), + /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), + /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), + /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* SSP_RXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), +}; + + /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* F12 : GSXDOUT ==> WWAN_RST_L */ @@ -67,25 +119,85 @@ PAD_CFG_GPO(GPP_H13, 1, DEEP), }; +/* Early pad configuration in bootblock for craaskneo/craaskino, board id >= 0x20 */ +static const struct pad_config early_gpio_table_extend[] = { + /* B4 : SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* F12 : GSXDOUT ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* E13 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_E13, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* D11 : EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), +}; + static const struct pad_config romstage_gpio_table[] = { /* H12 : UART0_RTS# ==> SD_PERST_L */ PAD_CFG_GPO(GPP_H12, 1, DEEP), }; + +/* Pad configuration in romstage for craaskneo/craaskino, board id >= 0x20 */ +static const struct pad_config romstage_gpio_table_extend[] = { + /* B4 : SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 1, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { + const uint32_t id = board_id(); + + if (id >= 0x20) { + *num = ARRAY_SIZE(override_gpio_table_extend); + return override_gpio_table_extend; + } + *num = ARRAY_SIZE(override_gpio_table); return override_gpio_table; } const struct pad_config *variant_early_gpio_table(size_t *num) { + const uint32_t id = board_id(); + + if (id >= 0x20) { + *num = ARRAY_SIZE(early_gpio_table_extend); + return early_gpio_table_extend; + } + *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } const struct pad_config *variant_romstage_gpio_table(size_t *num) { + const uint32_t id = board_id(); + + if (id >= 0x20) { + *num = ARRAY_SIZE(romstage_gpio_table_extend); + return romstage_gpio_table_extend; + } + *num = ARRAY_SIZE(romstage_gpio_table); return romstage_gpio_table; } -- To view, visit https://review.coreboot.org/c/coreboot/+/69691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaf4ace5e71b5b49d80ee177637f68f1d4a9536d Gerrit-Change-Number: 69691 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/mediatek/mt8188: Enable and initialize EINT
by Rex-BC Chen (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Hung-Te Lin, Liju-Clr Chen, johnson wang, Yidi Lin, Yu-Ping Wu. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69688 ) Change subject: soc/mediatek/mt8188: Enable and initialize EINT ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: @yuping and @yidi, any suggestion for this patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/69688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94b20909b0b8d77f75c41bc745f892baded7a54b Gerrit-Change-Number: 69688 Gerrit-PatchSet: 1 Gerrit-Owner: johnson wang <johnson.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: johnson wang <johnson.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 03:22:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: build: List all Kconfigs in CBFS `config` file, compress it
by Julius Werner (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Vadim Bendebury, Martin L Roth, Patrick Georgi, Yu-Ping Wu. Hello build bot (Jenkins), Martin L Roth, Patrick Georgi, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69710 to look at the new patch set (#2). Change subject: build: List all Kconfigs in CBFS `config` file, compress it ...................................................................... build: List all Kconfigs in CBFS `config` file, compress it The coreboot build system automatically adds a `config` file to CBFS that lists the exact Kconfig configuration that this image was built with. This is useful to reproduce a build after the fact or to check whether support for a specific feature is enabled in the image. However, the file is currently generated using the `savedefconfig` command to Kconfig, which generates the minimal .config file that is needed to produce the required config in a coreboot build. This is fine for reproduction, but bad when you want to check if a certain config was enabled, since many configs get enabled by default or pulled in through another config's `select` statement and thus don't show up in the defconfig. This patch tries to fix that second use case by instead including the full .config instead. In order to save some space, we can remove all comments (e.g. `# CONFIG_XXX is not set`) from the file, which still makes it easy to test for a specific config (if it's in the file you can extract the right value, if not you can assume it was set to `n`). We can also LZMA compress it since this file is never read by firmware itself and only intended for later re-extraction via cbfstool, which always has LZMA support included. On a sample Trogdor device the existing (uncompressed) `config` file takes up 519 bytes in CBFS, whereas the new (compressed) file after this patch will take up 1832 bytes -- still a small amount that should hopefully not break the bank for anyone. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I5259ec6f932cdc5780b8843f46dd476da9d19728 --- M Makefile.inc M src/Kconfig 2 files changed, 45 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/69710/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5259ec6f932cdc5780b8843f46dd476da9d19728 Gerrit-Change-Number: 69710 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Attention: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: build: List all Kconfigs in CBFS `config` file, compress it
by Julius Werner (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Vadim Bendebury, Martin L Roth, Patrick Georgi, Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69710 ) Change subject: build: List all Kconfigs in CBFS `config` file, compress it ...................................................................... Patch Set 1: (1 comment) File Makefile.inc: https://review.coreboot.org/c/coreboot/+/69710/comment/fbdf16d2_8e7d90ac PS1, Line 1231: config-compression := LZMA > I'm just curious: where is this `config-compression` used? It's quite complicated since it's all written in make script, but basically adding `config` to `cbfs-files-y` tells it to add a CBFS file called `config`, and then it looks if certain `config-xxx` variables are defined to get more details about that file. Some of the code for that starts on lines 350 and 800. -- To view, visit https://review.coreboot.org/c/coreboot/+/69710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5259ec6f932cdc5780b8843f46dd476da9d19728 Gerrit-Change-Number: 69710 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Attention: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 03:18:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs
by Julius Werner (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Shelley Chen. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69690 ) Change subject: soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fa0ad392ba6320fdbab54b3b5dc83ac28cd20ba Gerrit-Change-Number: 69690 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 03:09:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/herobrine: Implement mainboard_needs_pcie_init
by Julius Werner (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Shelley Chen. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69689 ) Change subject: mb/google/herobrine: Implement mainboard_needs_pcie_init ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c Gerrit-Change-Number: 69689 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 03:09:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: build: List all Kconfigs in CBFS `config` file, compress it
by Vadim Bendebury (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Martin L Roth, Patrick Georgi, Julius Werner, Yu-Ping Wu. Vadim Bendebury has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69710 ) Change subject: build: List all Kconfigs in CBFS `config` file, compress it ...................................................................... Patch Set 1: (1 comment) File Makefile.inc: https://review.coreboot.org/c/coreboot/+/69710/comment/23d58744_fbc19566 PS1, Line 1231: config-compression := LZMA I'm just curious: where is this `config-compression` used? -- To view, visit https://review.coreboot.org/c/coreboot/+/69710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5259ec6f932cdc5780b8843f46dd476da9d19728 Gerrit-Change-Number: 69710 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 02:58:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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