coreboot-gerrit November 2022

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[M] Change in coreboot[master]: soc/intel/meteorlake: Log CSE RO write protection info for MTL
by Kapil Porwal (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69571 to look at the new patch set (#6). Change subject: soc/intel/meteorlake: Log CSE RO write protection info for MTL ...................................................................... soc/intel/meteorlake: Log CSE RO write protection info for MTL The patch logs CSE RO's write protection information for Meteor Lake platform. As part of write protection information, coreboot logs status on CSE RO write protection and range. Also, logs error message if EOM is disabled, and write protection for CSE RO is not enabled. Port of commit abe0d810f009 ("soc/intel/alderlake: Log CSE RO write protection info for ADL"). BUG=none TEST=Verify the write protection details on google/rex. Excerpt from google/rex coreboot log: [DEBUG] ME: WP for RO is enabled : YES [DEBUG] ME: RO write protection scope - Start=0x4000, End=0x396FFF Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 --- M src/soc/intel/meteorlake/me.c 1 file changed, 66 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/69571/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/69571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 Gerrit-Change-Number: 69571 Gerrit-PatchSet: 6 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Enable FSP multiphase
by Subrata Banik (Code Review) 17 Nov '22

17 Nov '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67741 ) Change subject: soc/intel/meteorlake: Enable FSP multiphase ...................................................................... soc/intel/meteorlake: Enable FSP multiphase This patch changes the UPD EnableMultiPhaseSiliconInit to enable the Meteor Lake FSP multiphase flow. BUG=b:247670186 TEST=Able to build and boot Google, Rex with MultiPhaseSiInit Enable. [SPEW ] Executing Phase 1 of FspMultiPhaseSiInit [DEBUG] FSP MultiPhaseSiInit src/soc/intel/meteorlake/ fsp_params.c/platform_fsp_multi_phase_init_cb called [DEBUG] port C0 DISC req: usage 1 usb3 1 usb2 2 [DEBUG] Raw Buffer output 0 00000211 [DEBUG] Raw Buffer output 1 00000000 [DEBUG] pmc_send_ipc_cmd succeeded [DEBUG] port C1 DISC req: usage 1 usb3 3 usb2 4 [DEBUG] Raw Buffer output 0 00000431 [DEBUG] Raw Buffer output 1 00000000 [DEBUG] pmc_send_ipc_cmd succeeded Change-Id: I759c0ecee29c07bae4abe6b56d015e7253bd49fe Signed-off-by: zhaojohn <john.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67741 Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> --- M src/soc/intel/meteorlake/fsp_params.c 1 file changed, 37 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, but someone else must approve Jamie Ryu: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved Tarun Tuli: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 4fe2f63..4429dc0 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -394,10 +394,10 @@ static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg) { - /* UPDATEME: Disable for VP + /* * EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ - s_arch_cfg->EnableMultiPhaseSiliconInit = 0; + s_arch_cfg->EnableMultiPhaseSiliconInit = 1; /* Assign FspEventHandler arch Upd to use coreboot debug event handler */ if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) && -- To view, visit https://review.coreboot.org/c/coreboot/+/67741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I759c0ecee29c07bae4abe6b56d015e7253bd49fe Gerrit-Change-Number: 67741 Gerrit-PatchSet: 4 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices
by Sridhar Siricilla (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69680 ) Change subject: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69680/comment/8a0b8250_602c4f62 PS2, Line 10: : The learning being made from Alder Lake platform showed that the CSE : EOP cmd response time is highly nondeterministic and letting the EOP : cmd issued by FSP makes the response time even worse. : : The idea being pursued during Alder Lake platform is to let FSP skip sending the EOP cmd and coreboot sends it at the last minute : (late sending of EOP) to ensure there is ample time for CSE to come : to a state where the response to the EOP is almost immediate. > > > Thanks for commit update. […] >This is to ensure FSP can skip setting D0i3 bit for CSE and coreboot is able to sent EOP and put the HECI devices into the D0i3 The message seems to be apt for the current CL. >Can you please elaborate how the EOP cmd receiving arch is different between ADL and MTL? My comment is based on the issue you indicated in the CL's commit message. It seems the current commit message is not relevant directly. -- To view, visit https://review.coreboot.org/c/coreboot/+/69680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c3765ce41f192ab5f5ff176e0a2b49b312d18d2 Gerrit-Change-Number: 69680 Gerrit-PatchSet: 3 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 06:07:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/variants/crota: Configure TDC current for VR domains.
by Johnny Li (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Johnny Li, Paul F Yang. Johnny Li has removed Mars Chen from this change. ( https://review.coreboot.org/c/coreboot/+/69135 ) Change subject: mb/google/brya/variants/crota: Configure TDC current for VR domains. ...................................................................... Removed cc Mars Chen <chenxiangrui(a)huaqin.corp-partner.google.com>. -- To view, visit https://review.coreboot.org/c/coreboot/+/69135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife36655f077bae567bff3c3e33f779c990cf5ed9 Gerrit-Change-Number: 69135 Gerrit-PatchSet: 9 Gerrit-Owner: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Paul F Yang <paul.f.yang(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Paul Yang <paul.f.yang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-Attention: Paul F Yang <paul.f.yang(a)intel.com> Gerrit-MessageType: deleteReviewer

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[M] Change in coreboot[master]: soc/intel/meteorlake: Log CSE RO write protection info for MTL
by Kapil Porwal (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69571 ) Change subject: soc/intel/meteorlake: Log CSE RO write protection info for MTL ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69571/comment/2fcc2d82_9577e955 PS2, Line 21: YES > It is just a debug message. A port of ADL CL. It is the output of an existing API (is_spi_wp_cse_ro_en). File src/soc/intel/meteorlake/me.c: https://review.coreboot.org/c/coreboot/+/69571/comment/04fb09f0_c617b8fe PS2, Line 186: hfsts1.fields.mfg_mode > Thanks Sridhar & Subrata. I will port both CLs (CB:69286 & CB:69324) once they are merged. Rebased on top of MTL CL CB:69578 -- To view, visit https://review.coreboot.org/c/coreboot/+/69571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 Gerrit-Change-Number: 69571 Gerrit-PatchSet: 4 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 05:51:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/meteorlake: Log CSE RO write protection info for MTL
by Kapil Porwal (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69571 to look at the new patch set (#5). Change subject: soc/intel/meteorlake: Log CSE RO write protection info for MTL ...................................................................... soc/intel/meteorlake: Log CSE RO write protection info for MTL The patch logs CSE RO's write protection information for Meteor Lake platform. As part of write protection information, coreboot logs status on CSE RO write protection and range. Also, logs error message if EOM is disabled, and write protection for CSE RO is not enabled. Port of commit abe0d810f009 ("soc/intel/alderlake: Log CSE RO write protection info for ADL"). BUG=none TEST=Verify the write protection details on google/rex. Excerpt from google/rex coreboot log: [DEBUG] ME: WP for RO is enabled : YES [DEBUG] ME: RO write protection scope - Start=0x4000, End=0x396FFF Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 --- M src/soc/intel/meteorlake/me.c 1 file changed, 54 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/69571/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/69571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 Gerrit-Change-Number: 69571 Gerrit-PatchSet: 5 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/rex: Enable TCSS Displayport detection at preboot
by John Zhao (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, John Zhao. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67742 to look at the new patch set (#6). Change subject: mb/google/rex: Enable TCSS Displayport detection at preboot ...................................................................... mb/google/rex: Enable TCSS Displayport detection at preboot This change enables the Displayport detection at preboot for Rex board. BUG=b:247670186 TEST=Built image and validated Displayport feature at preboot on Rex. Change-Id: I1a8a13e937c7132696aa39d85c3c6b6fb2dd13a5 Signed-off-by: zhaojohn <john.zhao(a)intel.com> --- M src/mainboard/google/rex/Kconfig 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/67742/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/67742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a8a13e937c7132696aa39d85c3c6b6fb2dd13a5 Gerrit-Change-Number: 67742 Gerrit-PatchSet: 6 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/meteorlake: Log CSE RO write protection info for MTL
by Sridhar Siricilla (Code Review) 17 Nov '22

17 Nov '22

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[S] Change in coreboot[master]: soc/intel/common: Fix the TCSS DisplayPort detection flow
by John Zhao (Code Review) 17 Nov '22

17 Nov '22

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69694 ) Change subject: soc/intel/common: Fix the TCSS DisplayPort detection flow ...................................................................... soc/intel/common: Fix the TCSS DisplayPort detection flow After DisplayPort is plugged into type-C port, its hpd signal is instantly presents and EC has mux_info for dp and hpd. This change fixes the DP detection flow to avoid the 1 second delay while no DP is connected. If DP is present, there will be requests towards PMC through the sequence of connect, safe mode, dp and hpd mode. BUG=b:247670186 TEST=Built image and validated the DisplayPort preboot feature on Rex. Change-Id: I7cb95ec7fcc7e1a86e86466e6d45390eedcc4531 Signed-off-by: zhaojohn <john.zhao(a)intel.com> --- M src/soc/intel/common/block/tcss/tcss.c 1 file changed, 21 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/69694/1 diff --git a/src/soc/intel/common/block/tcss/tcss.c b/src/soc/intel/common/block/tcss/tcss.c index df331c2..b4a5a0e 100644 --- a/src/soc/intel/common/block/tcss/tcss.c +++ b/src/soc/intel/common/block/tcss/tcss.c @@ -202,7 +202,6 @@ req.buf[0] = cmd; return send_pmc_req(HPD_REQ, &req, &rsp, PMC_IPC_HPD_REQ_SIZE); - } static int send_pmc_dp_mode_request(int port, const struct usbc_mux_info *mux_data, @@ -287,7 +286,7 @@ static void tcss_configure_dp_mode(const struct tcss_port_map *port_map, size_t num_ports) { - int ret, port_bitmask; + int ret; size_t i; const struct usbc_ops *ops; struct usbc_mux_info mux_info; @@ -300,24 +299,9 @@ if (ops == NULL) return; - port_bitmask = ops->dp_ops.wait_for_connection(WAIT_FOR_DISPLAYPORT_TIMEOUT_MS); - if (!port_bitmask) /* No DP device is connected */ - return; - for (i = 0; i < num_ports; i++) { - if (!(port_bitmask & BIT(i))) - continue; - - ret = ops->dp_ops.enter_dp_mode(i); - if (ret < 0) - continue; - - ret = ops->dp_ops.wait_for_hpd(i, WAIT_FOR_HPD_TIMEOUT_MS); - if (ret < 0) - continue; - ret = ops->mux_ops.get_mux_info(i, &mux_info); - if (ret < 0) + if ((ret < 0) || (!mux_info.dp)) continue; port_info = &port_map[i]; -- To view, visit https://review.coreboot.org/c/coreboot/+/69694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cb95ec7fcc7e1a86e86466e6d45390eedcc4531 Gerrit-Change-Number: 69694 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/meteorlake: Log CSE RO write protection info for MTL
by Kapil Porwal (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Sridhar Siricilla. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69571 to look at the new patch set (#4). Change subject: soc/intel/meteorlake: Log CSE RO write protection info for MTL ...................................................................... soc/intel/meteorlake: Log CSE RO write protection info for MTL The patch logs CSE RO's write protection information for Meteor Lake platform. As part of write protection information, coreboot logs status on CSE RO write protection and range. Also, logs error message if EOM is disabled, and write protection for CSE RO is not enabled. Port of commit abe0d810f009 ("soc/intel/alderlake: Log CSE RO write protection info for ADL"). BUG=none TEST=Verify the write protection details on google/rex. Excerpt from google/rex coreboot log: [DEBUG] ME: WP for RO is enabled : YES [DEBUG] ME: RO write protection scope - Start=0x4000, End=0x396FFF Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 --- M src/soc/intel/meteorlake/me.c 1 file changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/69571/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 Gerrit-Change-Number: 69571 Gerrit-PatchSet: 4 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2022