coreboot-gerrit November 2022

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[S] Change in coreboot[master]: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.5
by Elyes Haouas (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Martin L Roth, Arthur Heymans. Elyes Haouas has uploaded a new patch set (#5). ( https://review.coreboot.org/c/coreboot/+/69700 ) Change subject: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.5 ...................................................................... crossgcc: Upgrade LLVM from 15.0.0 to 15.0.5 Change-Id: I9e6c23c6552eded92e706bc21bb162a66767572e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/clang-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/clang-15.0.5.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-15.0.5.src.tar.xz.cksum D util/crossgcc/sum/cmake-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/cmake-15.0.5.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-15.0.5.src.tar.xz.cksum D util/crossgcc/sum/llvm-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/llvm-15.0.5.src.tar.xz.cksum 11 files changed, 16 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/69700/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/69700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e6c23c6552eded92e706bc21bb162a66767572e Gerrit-Change-Number: 69700 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.5
by Elyes Haouas (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Martin L Roth, Arthur Heymans. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69700 ) Change subject: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.5 ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69700/comment/9250a53f_5c4d1de9 PS3, Line 7: LLVN > LLVM Oops, Merci beaucoup. -- To view, visit https://review.coreboot.org/c/coreboot/+/69700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e6c23c6552eded92e706bc21bb162a66767572e Gerrit-Change-Number: 69700 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 17 Nov 2022 08:26:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.5
by Elyes Haouas (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Martin L Roth, Elyes Haouas. Elyes Haouas has uploaded a new patch set (#4). ( https://review.coreboot.org/c/coreboot/+/69700 ) Change subject: crossgcc: Upgrade LLVM from 15.0.0 to 15.0.5 ...................................................................... crossgcc: Upgrade LLVM from 15.0.0 to 15.0.5 Change-Id: I9e6c23c6552eded92e706bc21bb162a66767572e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/clang-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/clang-15.0.5.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-15.0.5.src.tar.xz.cksum D util/crossgcc/sum/cmake-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/cmake-15.0.5.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-15.0.5.src.tar.xz.cksum D util/crossgcc/sum/llvm-15.0.0.src.tar.xz.cksum A util/crossgcc/sum/llvm-15.0.5.src.tar.xz.cksum 11 files changed, 16 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/69700/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e6c23c6552eded92e706bc21bb162a66767572e Gerrit-Change-Number: 69700 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/rex: Enable TCSS DisplayPort detection at preboot
by Subrata Banik (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Tarun Tuli, John Zhao, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67742 ) Change subject: mb/google/rex: Enable TCSS DisplayPort detection at preboot ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a8a13e937c7132696aa39d85c3c6b6fb2dd13a5 Gerrit-Change-Number: 67742 Gerrit-PatchSet: 7 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 08:21:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Enable TCSS DisplayPort detection at preboot
by John Zhao (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, John Zhao. John Zhao has uploaded a new patch set (#7) to the change originally created by John Zhao. ( https://review.coreboot.org/c/coreboot/+/67742 ) Change subject: mb/google/rex: Enable TCSS DisplayPort detection at preboot ...................................................................... mb/google/rex: Enable TCSS DisplayPort detection at preboot This change enables the DisplayPort detection at preboot for Rex board. BUG=b:247670186 TEST=Built image and validated DisplayPort feature at preboot on Rex. Change-Id: I1a8a13e937c7132696aa39d85c3c6b6fb2dd13a5 Signed-off-by: zhaojohn <john.zhao(a)intel.com> --- M src/mainboard/google/rex/Kconfig 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/67742/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/67742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a8a13e937c7132696aa39d85c3c6b6fb2dd13a5 Gerrit-Change-Number: 67742 Gerrit-PatchSet: 7 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/common: Fix the TCSS DisplayPort detection flow
by John Zhao (Code Review) 17 Nov '22

17 Nov '22

John Zhao has uploaded a new patch set (#2) to the change originally created by John Zhao. ( https://review.coreboot.org/c/coreboot/+/69694 ) Change subject: soc/intel/common: Fix the TCSS DisplayPort detection flow ...................................................................... soc/intel/common: Fix the TCSS DisplayPort detection flow After DisplayPort is plugged into type-C port, its hpd signal instantly presents and EC has mux_info for dp and hpd. This change fixes the DP detection flow to avoid the 1 second delay while no DP is connected. If DP is present, there will be requests towards PMC through the sequence of connect, safe mode, dp and hpd mode. BUG=b:247670186 TEST=Built image and validated the DisplayPort preboot feature on Rex. Change-Id: I7cb95ec7fcc7e1a86e86466e6d45390eedcc4531 Signed-off-by: zhaojohn <john.zhao(a)intel.com> --- M src/soc/intel/common/block/tcss/tcss.c 1 file changed, 21 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/69694/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cb95ec7fcc7e1a86e86466e6d45390eedcc4531 Gerrit-Change-Number: 69694 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/meteorlake: Log CSE RO write protection info for MTL
by Subrata Banik (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69571 ) Change subject: soc/intel/meteorlake: Log CSE RO write protection info for MTL ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/meteorlake/me.c: https://review.coreboot.org/c/coreboot/+/69571/comment/f668f0de_9ec538fd PS6, Line 79: consider dividing this CL into 3 Cls further 1. rename is_eom to is_manuf_mode 2. Add additional prints ``` printk(BIOS_DEBUG, "ME: FPFs Committed : %s\n", hfsts6.fields.fpf_soc_lock ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Manufacturing Vars Locked : %s\n", hfsts6.fields.manuf_lock ? "YES" : "NO"); ``` 3. Implement and call into log_me_ro_write_protection_info() -- To view, visit https://review.coreboot.org/c/coreboot/+/69571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 Gerrit-Change-Number: 69571 Gerrit-PatchSet: 6 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 07:52:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: sb/intel/i82801dx: Improve LPC device early init
by Kyösti Mälkki (Code Review) 17 Nov '22

17 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69671 ) Change subject: sb/intel/i82801dx: Improve LPC device early init ...................................................................... sb/intel/i82801dx: Improve LPC device early init Make the implementation more similar to i82801gx, enabling ACPI PM and GPIO register spaces already in bootblock. Change-Id: I41ad8622801dbbadafdc37359d521eed42256e63 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69671 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/e7505/romstage.c M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/bootblock.c A src/southbridge/intel/i82801dx/early_init.c D src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c 7 files changed, 63 insertions(+), 69 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/e7505/romstage.c b/src/northbridge/intel/e7505/romstage.c index df10f9d..d997ee1 100644 --- a/src/northbridge/intel/e7505/romstage.c +++ b/src/northbridge/intel/e7505/romstage.c @@ -8,10 +8,9 @@ void mainboard_romstage_entry(void) { - /* Perform some early chipset initialization required - * before RAM initialization can work - */ + /* FIXME: Keep until flashed bootblock has these. */ i82801dx_early_init(); + i82801dx_lpc_setup(); sdram_initialize(); diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index c352e3e..be17cf9 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -2,6 +2,11 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801DX),y) +bootblock-y += bootblock.c +bootblock-y += early_init.c + +romstage-y += early_init.c + ramstage-y += i82801dx.c ramstage-y += ac97.c ramstage-y += fadt.c @@ -10,8 +15,4 @@ ramstage-y += usb.c ramstage-y += usb2.c -romstage-y += early_smbus.c - -bootblock-y += bootblock.c - endif diff --git a/src/southbridge/intel/i82801dx/bootblock.c b/src/southbridge/intel/i82801dx/bootblock.c index 6cda0a8..c22eb3e 100644 --- a/src/southbridge/intel/i82801dx/bootblock.c +++ b/src/southbridge/intel/i82801dx/bootblock.c @@ -8,4 +8,9 @@ /* Set FWH IDs for 2 MB flash part. */ if (CONFIG_ROM_SIZE == 0x200000) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xe8, 0x00001111); + + + /* Setup decode ports and LPC I/F enables. */ + i82801dx_early_init(); + i82801dx_lpc_setup(); } diff --git a/src/southbridge/intel/i82801dx/early_init.c b/src/southbridge/intel/i82801dx/early_init.c new file mode 100644 index 0000000..2ed7aa3 --- /dev/null +++ b/src/southbridge/intel/i82801dx/early_init.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/smbus_host.h> +#include <device/pci_ops.h> +#include "i82801dx.h" + +void i82801dx_early_init(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config32(dev, PMBASE, DEFAULT_PMBASE | 1); + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); + + pci_write_config32(dev, GPIO_BASE, GPIOBASE_ADDR | 1); + pci_write_config8(dev, GPIO_CNTL, 0x10); + + if (ENV_RAMINIT) + enable_smbus(); +} + +void i82801dx_lpc_setup(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + + /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. + * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. + * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7. + * We also need to set the value for LPC I/F Enables Register. + */ + pci_write_config8(dev, COM_DEC, 0x10); + pci_write_config16(dev, LPC_EN, 0x300F); +} diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c deleted file mode 100644 index 76ef1b8..0000000 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/smbus_host.h> -#include "i82801dx.h" - -void i82801dx_early_init(void) -{ - enable_smbus(); -} diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 7946bd5..ecb9924 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -1,26 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* the problem: we have 82801dbm support in fb1, and 82801er in fb2. - * fb1 code is what we want, fb2 structure is needed however. - * so we need to get fb1 code for 82801dbm into fb2 structure. - */ -/* What I did: took the 80801er stuff from fb2, verify it against the - * db stuff in fb1, and made sure it was right. - */ - #ifndef I82801DX_H #define I82801DX_H #include <acpi/acpi.h> - -#if !defined(__ASSEMBLER__) - #include <device/device.h> void i82801dx_enable(struct device *dev); void i82801dx_early_init(void); - -#endif +void i82801dx_lpc_setup(void); #define DEBUG_PERIODIC_SMIS 0 @@ -54,8 +42,7 @@ #define PCICMD 0x04 #define PMBASE 0x40 -#define PMBASE_ADDR 0x0400 -#define DEFAULT_PMBASE PMBASE_ADDR +#define DEFAULT_PMBASE 0x0400 #define ACPI_CNTL 0x44 #define ACPI_EN (1 << 4) #define BIOS_CNTL 0x4E diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index c844735..c92562a 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -22,20 +22,6 @@ typedef struct southbridge_intel_i82801dx_config config_t; /** - * Enable ACPI I/O range. - * - * @param dev PCI device with ACPI and PM BAR's - */ -static void i82801dx_enable_acpi(struct device *dev) -{ - /* Set ACPI base address (I/O space). */ - pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); - - /* Enable ACPI I/O range decode and ACPI power management. */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); -} - -/** * Set miscellaneous static southbridge features. * * @param dev PCI device with I/O APIC control registers @@ -155,12 +141,6 @@ outl(reg32, pmbase + 0x04); } -static void gpio_init(struct device *dev) -{ - /* This should be done in romstage.c already */ - pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1)); - pci_write_config8(dev, GPIO_CNTL, 0x10); -} static void i82801dx_rtc_init(struct device *dev) { @@ -197,17 +177,6 @@ pci_write_config16(dev, PCI_DMA_CFG, reg16); } -static void i82801dx_lpc_decode_en(struct device *dev) -{ - /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. - * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. - * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7. - * We also need to set the value for LPC I/F Enables Register. - */ - pci_write_config8(dev, COM_DEC, 0x10); - pci_write_config16(dev, LPC_EN, 0x300F); -} - /* ICH4 does not mention HPET in the docs, but * all ICH3 and ICH4 do have HPETs built in. */ @@ -247,7 +216,6 @@ static void lpc_init(struct device *dev) { - i82801dx_enable_acpi(dev); /* IO APIC initialization. */ i82801dx_enable_ioapic(dev); @@ -259,9 +227,6 @@ /* Setup power options. */ i82801dx_power_options(dev); - /* Set the state of the GPIO lines. */ - gpio_init(dev); - /* Initialize the real time clock. */ i82801dx_rtc_init(dev); @@ -271,9 +236,6 @@ /* Initialize ISA DMA. */ isa_dma_init(); - /* Setup decode ports and LPC I/F enables. */ - i82801dx_lpc_decode_en(dev); - /* Initialize the High Precision Event Timers */ enable_hpet(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/69671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41ad8622801dbbadafdc37359d521eed42256e63 Gerrit-Change-Number: 69671 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: sb/intel/common: Fix GPE0 related register conflict
by Kyösti Mälkki (Code Review) 17 Nov '22

17 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69669 ) Change subject: sb/intel/common: Fix GPE0 related register conflict ...................................................................... sb/intel/common: Fix GPE0 related register conflict When ACPI GPE0 block was extended to 64 events or 8 bytes, ACPI PM register space was slightly modified. After adjustment, PM2_CNT register moved to 0x50 where register SS_CNT was previously defined to be. For platforms that have a valid use for PM2_CNT==0x50 in their FADT, remove overlapping definition of SS_CNT. On i82801dx/gx ACPI GPE0 supports 32 events, reset_gpe0_status() incorrectly addressed also GPE0_EN register. For a bit cleaner implementation, define GPE0_HAS_64_EVENTS. Change-Id: Iec83e9010146ebd487a61f542ac5c6f4c6a60833 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69669 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/pch.h 6 files changed, 55 insertions(+), 26 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 34b36c3..2ebec62 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -428,7 +428,6 @@ #define LV2 0x14 #define LV3 0x15 #define LV4 0x16 -#define PM2_CNT 0x50 // mobile only #define GPE0_STS 0x20 #define PME_B0_STS (1 << 13) #define PME_STS (1 << 11) @@ -462,8 +461,9 @@ #define ALT_GP_SMI_STS 0x3a #define GPE_CNTL 0x42 #define DEVACT_STS 0x44 -#define SS_CNT 0x50 +#define PM2_CNT 0x50 // mobile only #define C3_RES 0x54 + #define TCO1_STS 0x64 #define TCO1_TIMEOUT (1 << 3) #define DMISCI_STS (1 << 9) diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index a43b95c..8ecb74c 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -73,6 +73,7 @@ { printk(BIOS_DEBUG, "SMI_STS: "); if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); + if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI "); if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); @@ -100,13 +101,15 @@ */ u64 reset_gpe0_status(void) { - u32 reg_h, reg_l; + u32 reg_h = 0, reg_l; reg_l = read_pmbase32(GPE0_STS); - reg_h = read_pmbase32(GPE0_STS + 4); + if (GPE0_HAS_64_EVENTS) + reg_h = read_pmbase32(GPE0_STS + 4); /* set status bits are cleared by writing 1 to them */ write_pmbase32(GPE0_STS, reg_l); - write_pmbase32(GPE0_STS + 4, reg_h); + if (GPE0_HAS_64_EVENTS) + write_pmbase32(GPE0_STS + 4, reg_h); return (((u64)reg_h) << 32) | reg_l; } @@ -128,7 +131,7 @@ if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); - if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "USB5 "); + if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97/USB5 "); if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE "); diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index ff7b5e8..5cf76b6 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -5,6 +5,9 @@ #include <cpu/x86/smm.h> +#define GPE0_HAS_64_EVENTS \ + (!(CONFIG(SOUTHBRIDGE_INTEL_I82801DX) || CONFIG(SOUTHBRIDGE_INTEL_I82801GX))) + #define D31F0_PMBASE 0x40 #define D31F0_GEN_PMCON_1 0xa0 #define SMI_LOCK (1 << 4) @@ -54,13 +57,18 @@ #define LV2 0x14 #define LV3 0x15 #define LV4 0x16 -#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) + +#if GPE0_HAS_64_EVENTS +#define GPE0_STS 0x20 +#define GPE0_EN 0x28 // GPE0_STS + 8 +#define PM2_CNT 0x50 // mobile only +#else #define PM2_CNT 0x20 // mobile only #define GPE0_STS 0x28 -#else -#define PM2_CNT 0x50 // mobile only -#define GPE0_STS 0x20 -#endif /* CONFIG(SOUTHBRIDGE_INTEL_I82801GX) */ +#define GPE0_EN 0x2c // GPE0_STS + 4 +#endif + +/* def GPE0_STS */ #define USB4_STS (1 << 14) /* i82801gx only */ #define PME_B0_STS (1 << 13) #define PME_STS (1 << 11) @@ -71,11 +79,8 @@ #define TCOSCI_STS (1 << 6) #define SWGPE_STS (1 << 2) #define HOT_PLUG_STS (1 << 1) -#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) -#define GPE0_EN 0x2c -#else -#define GPE0_EN 0x28 -#endif /* CONFIG(SOUTHBRIDGE_INTEL_I82801GX) */ + +/* def GPE0_EN */ #define PME_B0_EN (1 << 13) #define PME_EN (1 << 11) #define TCOSCI_EN (1 << 6) @@ -98,8 +103,7 @@ #define ALT_GP_SMI_STS 0x3a #define GPE_CNTL 0x42 #define DEVACT_STS 0x44 -#define SS_CNT 0x50 -#define C3_RES 0x54 + #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define BOOT_STS (1 << 18) diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index c07e581..7946bd5 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -113,9 +113,6 @@ #define PM1_TMR 0x08 #define PROC_CNT 0x10 #define LV2 0x14 -#define LV3 0x15 -#define LV4 0x16 -#define PM2_CNT 0x20 // mobile only #define GPE0_STS 0x28 #define PME_B0_STS (1 << 13) #define USB3_STS (1 << 12) @@ -155,7 +152,6 @@ #define GPE_CNTL 0x42 #define DEVACT_STS 0x44 #define SS_CNT 0x50 -#define C3_RES 0x54 #define TCOBASE 0x60 /* TCO Base Address Register */ #define TCO1_CNT 0x08 /* TCO1 Control Register */ diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 1f5b4ea..c42fe0f 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -409,7 +409,6 @@ #define LV2 0x14 #define LV3 0x15 #define LV4 0x16 -#define PM2_CNT 0x50 // mobile only #define GPE0_STS 0x20 #define PME_B0_STS (1 << 13) #define PME_STS (1 << 11) @@ -443,8 +442,9 @@ #define ALT_GP_SMI_STS 0x3a #define GPE_CNTL 0x42 #define DEVACT_STS 0x44 -#define SS_CNT 0x50 +#define PM2_CNT 0x50 // mobile only #define C3_RES 0x54 + #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 1623274..dcd3ce5 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -581,7 +581,6 @@ #define LV2 0x14 #define LV3 0x15 #define LV4 0x16 -#define PM2_CNT 0x50 // mobile only #define GPE0_STS 0x20 #define PME_B0_STS (1 << 13) #define PME_STS (1 << 11) @@ -617,8 +616,9 @@ #define ALT_GP_SMI_STS 0x3a #define GPE_CNTL 0x42 #define DEVACT_STS 0x44 -#define SS_CNT 0x50 +#define PM2_CNT 0x50 // mobile only #define C3_RES 0x54 + #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 -- To view, visit https://review.coreboot.org/c/coreboot/+/69669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec83e9010146ebd487a61f542ac5c6f4c6a60833 Gerrit-Change-Number: 69669 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: sb/intel/common: Drop duplicate smi_set_eos()
by Kyösti Mälkki (Code Review) 17 Nov '22

17 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69668 ) Change subject: sb/intel/common: Drop duplicate smi_set_eos() ...................................................................... sb/intel/common: Drop duplicate smi_set_eos() We have equivalent southbridge_smi_set_eos(). Change-Id: I03a48f0ec9efac2a220aa4ca502a5f504d78c585 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69668 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smm_module_handler.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/pmutil.h 3 files changed, 16 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index e813f78..32f66af 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -74,14 +74,6 @@ printk(BIOS_DEBUG, "Unknown function\n"); } -/** - * @brief Set the EOS bit - */ -static void smi_set_eos(void) -{ - southbridge_smi_set_eos(); -} - static u32 pci_orig; /** @@ -196,7 +188,7 @@ smi_release_lock(); /* De-assert SMI# signal to allow another SMI */ - smi_set_eos(); + southbridge_smi_set_eos(); } RMODULE_ENTRY(smm_handler_start); diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index 02a8375..a43b95c 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -176,18 +176,6 @@ printk(BIOS_DEBUG, "\n"); } -/** - * @brief Set the EOS bit - */ -void smi_set_eos(void) -{ - u8 reg8; - - reg8 = read_pmbase8(SMI_EN); - reg8 |= EOS; - write_pmbase8(SMI_EN, reg8); -} - void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) { int i; diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index c9cf544..ff7b5e8 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -120,7 +120,6 @@ u32 reset_smi_status(void); void gpe0_mask(u32 clr, u32 set); void alt_gpi_mask(u16 clr, u16 set); -void smi_set_eos(void); void dump_alt_gp_smi_status(u16 alt_gp_smi_sts); u16 reset_alt_gp_smi_status(void); void dump_all_status(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/69668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03a48f0ec9efac2a220aa4ca502a5f504d78c585 Gerrit-Change-Number: 69668 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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