coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/herobrine: Implement mainboard_needs_pcie_init
by Shelley Chen (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69689 ) Change subject: mb/google/herobrine: Implement mainboard_needs_pcie_init ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/herobrine/mainboard.c: https://review.coreboot.org/c/coreboot/+/69689/comment/310763f3_f1c97ec6 PS2, Line 104: if ((sku & BIT(0)) == 2) > Uhh... pretty sure this doesn't work...? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c Gerrit-Change-Number: 69689 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 17 Nov 2022 02:52:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs
by Shelley Chen (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69690 ) Change subject: soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs ...................................................................... Patch Set 4: (1 comment) File src/soc/qualcomm/common/pcie_common.c: https://review.coreboot.org/c/coreboot/+/69690/comment/d7950d9c_dab60fcd PS3, Line 420: CB_ERR > nit: Should probably use CB_ERR_NOT_IMPLEMENTED, like the stub version that boards without PCIe use. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fa0ad392ba6320fdbab54b3b5dc83ac28cd20ba Gerrit-Change-Number: 69690 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 17 Nov 2022 02:52:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs
by Shelley Chen (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Shelley Chen. Hello Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69690 to look at the new patch set (#4). Change subject: soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs ...................................................................... soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs On Herobrine, we will determine if we have an NVMe device based on SKU id. Basically, if bit 0 is 2 (or Z), then we know that we have an NVMe device and thus will need to go through PCIe initialization. Otherwise, we know that we are booting an eMMC device. BUG=b:254281839 BRANCH=None TEST=build firmware image and boot and make sure we can boot up Tested on villager, which does not have NVMe and made sure that it boots still. Check cbmem dump to make sure that device configuration entry is still low since it's not initializing PCIe devices: 40:device configuration 730,203 (1,295) Change-Id: I1fa0ad392ba6320fdbab54b3b5dc83ac28cd20ba Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/soc/qualcomm/common/pcie_common.c M src/soc/qualcomm/sc7280/soc.c 2 files changed, 33 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/69690/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fa0ad392ba6320fdbab54b3b5dc83ac28cd20ba Gerrit-Change-Number: 69690 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/herobrine: Implement mainboard_needs_pcie_init
by Shelley Chen (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Shelley Chen. Hello Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69689 to look at the new patch set (#3). Change subject: mb/google/herobrine: Implement mainboard_needs_pcie_init ...................................................................... mb/google/herobrine: Implement mainboard_needs_pcie_init Implement mainboard_needs_pcie_init() for herobrine in order to determine if we need to initialize the pcie links. When the SKU id is unknown or unprovisioned (for example at the beginning of the factory flow), we should still initialize PCIe. Otherwise the devices with NVMe will fail to boot. BUG=b:254281839 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/herobrine/mainboard.c M src/soc/qualcomm/common/include/soc/pcie.h 2 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/69689/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c Gerrit-Change-Number: 69689 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: Revert "mb/google/herobrine: Remove NVMe from device tree"
by Shelley Chen (Code Review) 17 Nov '22

17 Nov '22

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69720 ) Change subject: Revert "mb/google/herobrine: Remove NVMe from device tree" ...................................................................... Revert "mb/google/herobrine: Remove NVMe from device tree" This reverts commit d164feb72602da958b644643b44e754f04a1f281. Reason for revert: Herobrine program decided that we wanted to be able to boot from NVMe if one exists. Change-Id: I2d3217c514734608e2ff049b620f4c7acf86de89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69720 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/herobrine/devicetree.cb 1 file changed, 20 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/mainboard/google/herobrine/devicetree.cb b/src/mainboard/google/herobrine/devicetree.cb index e23782f..34360b7 100644 --- a/src/mainboard/google/herobrine/devicetree.cb +++ b/src/mainboard/google/herobrine/devicetree.cb @@ -2,4 +2,7 @@ chip soc/qualcomm/sc7280 device cpu_cluster 0 on end + device domain 0 on + device pci 00.0 on end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/69720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d3217c514734608e2ff049b620f4c7acf86de89 Gerrit-Change-Number: 69720 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: Revert "soc/qualcomm/sc7280: Remove NVMe init"
by Shelley Chen (Code Review) 17 Nov '22

17 Nov '22

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69719 ) Change subject: Revert "soc/qualcomm/sc7280: Remove NVMe init" ...................................................................... Revert "soc/qualcomm/sc7280: Remove NVMe init" This reverts commit 1b07797a7b79ea6c11421b61b9cf14b92cb91c66. Reason for revert: Herobrine program decided that we wanted to be able to boot from NVMe if one exists. Change-Id: If675947026095d16b72bdb0f3ec790e583523465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69719 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/qualcomm/sc7280/Kconfig M src/soc/qualcomm/sc7280/soc.c 2 files changed, 22 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig index 3f3ded3..ccba8ff 100644 --- a/src/soc/qualcomm/sc7280/Kconfig +++ b/src/soc/qualcomm/sc7280/Kconfig @@ -19,6 +19,8 @@ select HAVE_LINEAR_FRAMEBUFFER select COMPRESS_BOOTBLOCK select HAVE_UART_SPECIAL + select PCI + select NO_ECAM_MMCONF_SUPPORT if SOC_QUALCOMM_SC7280 diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c index 265a694..dc5a9b0 100644 --- a/src/soc/qualcomm/sc7280/soc.c +++ b/src/soc/qualcomm/sc7280/soc.c @@ -43,14 +43,10 @@ static void enable_soc_dev(struct device *dev) { /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - if (CONFIG(PCI) && CONFIG(NO_ECAM_MMCONF_SUPPORT)) - dev->ops = &pci_domain_ops; - else - printk(BIOS_INFO, "Skip setting PCIe ops\n"); - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + if (dev->path.type == DEVICE_PATH_DOMAIN) + dev->ops = &pci_domain_ops; + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) dev->ops = &soc_ops; - } } struct chip_operations soc_qualcomm_sc7280_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/69719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If675947026095d16b72bdb0f3ec790e583523465 Gerrit-Change-Number: 69719 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs
by Julius Werner (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Shelley Chen. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69690 ) Change subject: soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs ...................................................................... Patch Set 3: Code-Review+2 (1 comment) File src/soc/qualcomm/common/pcie_common.c: https://review.coreboot.org/c/coreboot/+/69690/comment/4b30a8f0_6f7a866b PS3, Line 420: CB_ERR nit: Should probably use CB_ERR_NOT_IMPLEMENTED, like the stub version that boards without PCIe use. -- To view, visit https://review.coreboot.org/c/coreboot/+/69690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fa0ad392ba6320fdbab54b3b5dc83ac28cd20ba Gerrit-Change-Number: 69690 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 02:27:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/herobrine: Implement mainboard_needs_pcie_init
by Julius Werner (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Shelley Chen. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69689 ) Change subject: mb/google/herobrine: Implement mainboard_needs_pcie_init ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/herobrine/mainboard.c: https://review.coreboot.org/c/coreboot/+/69689/comment/b42a1d03_a4e64804 PS2, Line 104: if ((sku & BIT(0)) == 2) Uhh... pretty sure this doesn't work...? I don't know how exactly the EC generates the SKU ID, but if it's a normal (not "binary-first") base 3 number (e.g. (pin0 * 3^0 + pin1 * 3^1 + ...)) and you want to check if pin0 was Z, then I think `if (sku % 3 == 2)` is what you want here. -- To view, visit https://review.coreboot.org/c/coreboot/+/69689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c Gerrit-Change-Number: 69689 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 02:24:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: build: List all Kconfigs in CBFS `config` file, compress it
by Julius Werner (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Patrick Georgi, Yu-Ping Wu. Hello Patrick Georgi, Yu-Ping Wu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/69710 to review the following change. Change subject: build: List all Kconfigs in CBFS `config` file, compress it ...................................................................... build: List all Kconfigs in CBFS `config` file, compress it The coreboot build system automatically adds a `config` file to CBFS that lists the exact Kconfig configuration that this image was built with. This is useful to reproduce a build after the fact or to check whether support for a specific feature is enabled in the image. However, the file is currently generated using the `savedefconfig` command to Kconfig, which generates the minimal .config file that is needed to produce the required config in a coreboot build. This is fine for reproduction, but bad when you want to check if a certain config was enabled, since many configs get enabled by default or pulled in through another config's `select` statement and thus don't show up in the defconfig. This patch tries to fix that second use case by instead including the full .config instead. In order to save some space, we can extract all comments (e.g. `# CONFIG_XXX is not set`) from the file, which still makes it easy to test for a specific config (if it's in the file you can extract the right value, if not you can assume it was set to `n`). We can also LZMA compress it since this file is never read by firmware itself and only intended for later re-extraction via cbfstool, which always has LZMA support included. On a sample Trogdor device the existing (uncompressed) `config` file takes up 519 bytes in CBFS, whereas the new (compressed) file after this patch will take up 1832 bytes -- still a small amount that should hopefully not break the bank for anyone. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I5259ec6f932cdc5780b8843f46dd476da9d19728 --- M Makefile.inc 1 file changed, 43 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/69710/1 diff --git a/Makefile.inc b/Makefile.inc index 0ed205f..890f32e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -322,17 +322,15 @@ mv $(2).tmp $(2)) ####################################################################### -# Reduce a .config file to its minimal representation +# Reduce a .config file by removing lines about unset booleans # arg1: input # arg2: output -define cbfs-files-processor-defconfig - $(eval $(2): $(1) $(obj)/build.h $(objutil)/kconfig/conf; \ +define cbfs-files-processor-config + $(eval $(2): $(1) $(obj)/build.h; \ +printf " CREATE $(2) (from $(1))\n"; \ printf "# This image was built using coreboot " > $(2).tmp && \ grep "\<COREBOOT_VERSION\>" $(obj)/build.h |cut -d\" -f2 >> $(2).tmp && \ - $(MAKE) DOTCONFIG=$(1) DEFCONFIG=$(2).tmp2 savedefconfig && \ - cat $(2).tmp2 >> $(2).tmp && \ - rm -f $(2).tmp2 && \ + sed -e '/^CONFIG/!d' $(1) >> $(2).tmp && \ \mv -f $(2).tmp $(2)) endef @@ -1228,8 +1226,9 @@ vgaroms/seavgabios.bin-type := raw cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += config -config-file := $(DOTCONFIG):defconfig +config-file := $(DOTCONFIG):config config-type := raw +config-compression := LZMA cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += revision revision-file := $(obj)/build.h -- To view, visit https://review.coreboot.org/c/coreboot/+/69710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5259ec6f932cdc5780b8843f46dd476da9d19728 Gerrit-Change-Number: 69710 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/cmn/block/acpi: enable BERT table without crashlog
by Shuming Chu (Shuming) (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Jonathan Zhang, Arthur Heymans, Elyes Haouas. Shuming Chu (Shuming) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68878 ) Change subject: soc/intel/cmn/block/acpi: enable BERT table without crashlog ...................................................................... Patch Set 3: (2 comments) File src/soc/intel/common/block/acpi/acpi_bert.c: https://review.coreboot.org/c/coreboot/+/68878/comment/1598511a_8c0e795c PS2, Line 9: : #if (CONFIG(SOC_INTEL_CRASHLOG)) > This should not be needed. […] Done https://review.coreboot.org/c/coreboot/+/68878/comment/8004973b_aefa54bc PS2, Line 100: Error: > Please remove. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I323ca889eef2b246fc4e062582d2d11b4213316f Gerrit-Change-Number: 68878 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 17 Nov 2022 01:36:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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coreboot-gerrit November 2022