coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/herobrine: Implement mainboard_needs_pcie_init
by Shelley Chen (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Julius Werner. Hello Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69689 to look at the new patch set (#2). Change subject: mb/google/herobrine: Implement mainboard_needs_pcie_init ...................................................................... mb/google/herobrine: Implement mainboard_needs_pcie_init Implement mainboard_needs_pcie_init() for herobrine in order to determine if we need to initialize the pcie links. When the SKU id is unknown or unprovisioned (for example at the beginning of the factory flow), we should still initialize PCIe. Otherwise the devices with NVMe will fail to boot. BUG=b:254281839 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/herobrine/mainboard.c M src/soc/qualcomm/common/include/soc/pcie.h 2 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/69689/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c Gerrit-Change-Number: 69689 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs
by Shelley Chen (Code Review) 17 Nov '22

17 Nov '22

Shelley Chen has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/69690 ) Change subject: soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs ...................................................................... soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs On Herobrine, we will determine if we have an NVMe device based on SKU id. Basically, if bit 0 is 2 (or Z), then we know that we have an NVMe device and thus will need to go through PCIe initialization. Otherwise, we know that we are booting an eMMC device. BUG=b:254281839 BRANCH=None TEST=build firmware image and boot and make sure we can boot up Tested on villager, which does not have NVMe and made sure that it boots still. Check cbmem dump to make sure that device configuration entry is still low since it's not initializing PCIe devices: 40:device configuration 730,203 (1,295) Change-Id: I1fa0ad392ba6320fdbab54b3b5dc83ac28cd20ba Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/soc/qualcomm/common/pcie_common.c M src/soc/qualcomm/sc7280/soc.c 2 files changed, 33 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/69690/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fa0ad392ba6320fdbab54b3b5dc83ac28cd20ba Gerrit-Change-Number: 69690 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: [WIP] mb/prodrive/atlas: Populate smbios table with VPD from ECs EMI
by Maximilian Brune (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Angel Pons, David Milosevic. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68137 ) Change subject: [WIP] mb/prodrive/atlas: Populate smbios table with VPD from ECs EMI ...................................................................... Patch Set 8: (5 comments) File src/mainboard/prodrive/atlas/emi.h: https://review.coreboot.org/c/coreboot/+/68137/comment/81495045_3c981c89 PS6, Line 40: typedef enum { > Coreboot is full of typedefs. I don't see the problem here. just because other people have done it doesn't mean you have to do it to. It violates coreboot coding style so I don't see a reason to keep the typedef. https://review.coreboot.org/c/coreboot/+/68137/comment/42a9c760_f56a62a2 PS6, Line 43: EMI_REGION_1 ///< EMI region 1 > Agreed. Done File src/mainboard/prodrive/atlas/emi.c: https://review.coreboot.org/c/coreboot/+/68137/comment/5cdecaee_40bfaf47 PS6, Line 83: { > I already considered using a u32 but I did not like this approach so I switched to […] If the function is not used there is no need to keep it. If there really is a need for that function in the future, it can be added at that time. Implementing functions and functionalitly that is/are never used only worsens readability and blows up code to no end. https://review.coreboot.org/c/coreboot/+/68137/comment/5b6056aa_c228ab93 PS6, Line 139: inline void emi_write_register(const EMI_INSTANCE instance, const u8 offs, const u8 value) > I wont remove this function for the same reason as above. […] same as above. https://review.coreboot.org/c/coreboot/+/68137/comment/d1d5fdd3_2de68753 PS6, Line 144: inline u8 emi_read_register(const EMI_INSTANCE instance, const u8 offs) > See previous replies. see previous replies -- To view, visit https://review.coreboot.org/c/coreboot/+/68137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47bb4883c43ff344a9bda92c3106dd025533b391 Gerrit-Change-Number: 68137 Gerrit-PatchSet: 8 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 01:13:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Revert "mb/google/herobrine: Remove NVMe from device tree"
by Julius Werner (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Shelley Chen. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69720 ) Change subject: Revert "mb/google/herobrine: Remove NVMe from device tree" ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d3217c514734608e2ff049b620f4c7acf86de89 Gerrit-Change-Number: 69720 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 01:12:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Revert "soc/qualcomm/sc7280: Remove NVMe init"
by Julius Werner (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Shelley Chen. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69719 ) Change subject: Revert "soc/qualcomm/sc7280: Remove NVMe init" ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If675947026095d16b72bdb0f3ec790e583523465 Gerrit-Change-Number: 69719 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 01:12:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs
by Shelley Chen (Code Review) 17 Nov '22

17 Nov '22

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69690 ) Change subject: soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs ...................................................................... soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs On Herobrine, we will determine if we have an NVMe device based on SKU id. Basically, if bit 0 is 2 (or Z), then we know that we have an NVMe device and thus will need to go through PCIe initialization. Otherwise, we know that we are booting an eMMC device. Change-Id: I1fa0ad392ba6320fdbab54b3b5dc83ac28cd20ba Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/soc/qualcomm/common/pcie_common.c M src/soc/qualcomm/sc7280/soc.c 2 files changed, 24 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/69690/1 diff --git a/src/soc/qualcomm/common/pcie_common.c b/src/soc/qualcomm/common/pcie_common.c index 2f53e28..2925466 100644 --- a/src/soc/qualcomm/common/pcie_common.c +++ b/src/soc/qualcomm/common/pcie_common.c @@ -416,6 +416,9 @@ */ enum cb_err fill_lb_pcie(struct lb_pcie *pcie) { + if (!mainboard_needs_pcie_init()) + return CB_ERR; + pcie_cntlr_cfg_t *pcierc = qcom_pcie_cfg.cntlr_cfg; pcie->ctrl_base = (uintptr_t)pcierc->dbi_base; return CB_SUCCESS; diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c index dc5a9b0..268f080 100644 --- a/src/soc/qualcomm/sc7280/soc.c +++ b/src/soc/qualcomm/sc7280/soc.c @@ -43,9 +43,12 @@ static void enable_soc_dev(struct device *dev) { /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) - dev->ops = &pci_domain_ops; - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) + if (dev->path.type == DEVICE_PATH_DOMAIN) { + if (mainboard_needs_pcie_init()) + dev->ops = &pci_domain_ops; + else + printk(BIOS_DEBUG, "Skip setting PCIe ops\n"); + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) dev->ops = &soc_ops; } -- To view, visit https://review.coreboot.org/c/coreboot/+/69690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fa0ad392ba6320fdbab54b3b5dc83ac28cd20ba Gerrit-Change-Number: 69690 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/herobrine: Implement mainboard_needs_pcie_init
by Shelley Chen (Code Review) 17 Nov '22

17 Nov '22

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69689 ) Change subject: mb/google/herobrine: Implement mainboard_needs_pcie_init ...................................................................... mb/google/herobrine: Implement mainboard_needs_pcie_init Implement mainboard_needs_pcie_init() for herobrine in order to determine if we need to initialize the pcie links. When the SKU id is unknown or unprovisioned (for example at the beginning of the factory flow), we should still initialize PCIe. Otherwise the devices with NVMe will fail to boot. BUG=b:254281839 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/herobrine/mainboard.c M src/soc/qualcomm/common/include/soc/pcie.h 2 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/69689/1 diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c index ece6d68..881ed44 100644 --- a/src/mainboard/google/herobrine/mainboard.c +++ b/src/mainboard/google/herobrine/mainboard.c @@ -8,10 +8,12 @@ #include <delay.h> #include <device/device.h> #include <device/mmio.h> +#include <ec/google/chromeec/ec.h> #include <edid.h> #include <soc/clock.h> #include <soc/display/mdssreg.h> #include <soc/display/edp_ctrl.h> +#include <soc/pcie.h> #include <soc/qupv3_config_common.h> #include <soc/qup_se_handlers_common.h> #include <soc/qcom_qup_se.h> @@ -82,6 +84,25 @@ } } +bool mainboard_needs_pcie_init(void) +{ + uint32_t sku = sku_id(); + + if (sku == CROS_SKU_UNKNOWN) { + printk(BIOS_WARNING, "Unknown SKU (%#x); assuming PCIe", sku); + return true; + } else if (sku == CROS_SKU_UNPROVISIONED) { + printk(BIOS_WARNING, "Unprovisioned SKU (%#x); assuming PCIe", sku); + return true; + } + + if ((sku & BIT(0)) == 2) + return true; + + /* Otherwise, eMMC */ + return false; +} + static void mainboard_init(struct device *dev) { /* Configure clock for eMMC */ diff --git a/src/soc/qualcomm/common/include/soc/pcie.h b/src/soc/qualcomm/common/include/soc/pcie.h index 09ea671..b2f9e45 100644 --- a/src/soc/qualcomm/common/include/soc/pcie.h +++ b/src/soc/qualcomm/common/include/soc/pcie.h @@ -221,5 +221,6 @@ void gcom_pcie_get_config(struct qcom_pcie_cntlr_t *host_cfg); void qcom_pci_domain_read_resources(struct device *dev); void qcom_setup_pcie_host(struct device *dev); +bool mainboard_needs_pcie_init(void); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/69689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c Gerrit-Change-Number: 69689 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: Documentation/sbom: Add SBOM Documentation
by Maximilian Brune (Code Review) 17 Nov '22

17 Nov '22

Attention is currently required from: Patrick Rudolph, Richard Hughes, Angel Pons, Nicholas Chin. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68995 ) Change subject: Documentation/sbom: Add SBOM Documentation ...................................................................... Patch Set 9: (3 comments) File Documentation/sbom/sbom.md: https://review.coreboot.org/c/coreboot/+/68995/comment/e729fdaf_dfb5d61b PS8, Line 94: 3. To build coreboot: Add `CONFIG_SBOM_[software-name]_PATH` to your defconfig pointing to your [software-name] generated File. > Please reflow to 72 chars Done https://review.coreboot.org/c/coreboot/+/68995/comment/67251995_7e54106d PS8, Line 97: 1. Generate a SWID/CoSWID/uSWID File in either JSON, XML or CBOR Format as part of your software's build process. for example in form of a Makefile target. > Same as above Done https://review.coreboot.org/c/coreboot/+/68995/comment/67b6002d_0ff90e9f PS8, Line 98: 2. Change src/sbom/Makefile.inc (in order to know where to find the CoSWID/SWID/uSWID File) as well as the Makefile in coreboot which builds said software. For example for GRUB2 that could mean to add a Makefile target in payloads/external/GRUB2/Makefile. > Same as above Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39fbcba60a0fbdbed9f662119ed7692c0a0fd30e Gerrit-Change-Number: 68995 Gerrit-PatchSet: 9 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Richard Hughes <richard(a)hughsie.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Richard Hughes <richard(a)hughsie.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 00:58:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/xivu: Add fw_config probe for ALC5682-VS/ALC5682-VD
by Eric Lai (Code Review) 17 Nov '22

17 Nov '22

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69607 ) Change subject: mb/google/nissa/var/xivu: Add fw_config probe for ALC5682-VS/ALC5682-VD ...................................................................... mb/google/nissa/var/xivu: Add fw_config probe for ALC5682-VS/ALC5682-VD ALC5682-VS/ALC5682-VD use different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. ALC5682I-VS: _HID = "RTL5682" ALC5682-VD: _HID = "10EC5682" BUG=b:246491349 TEST=ALC5682-VD/ALC5682-VS audio codec can work. Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: I60d5e0af7e2dabd134c8059eaeac388d40ac2073 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69607 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/xivu/overridetree.cb 1 file changed, 44 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Reka Norman: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb index fa3d22a..3c45ff4 100644 --- a/src/mainboard/google/brya/variants/xivu/overridetree.cb +++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb @@ -7,6 +7,10 @@ option STYLUS_PRESENT 0 option STYLUS_ABSENT 1 end + field AUDIO_CODEC_SOURCE 8 + option AUDIO_CODEC_ALC5682_VS 0 + option AUDIO_CODEC_ALC5682_VD 1 + end end chip soc/intel/alderlake @@ -281,7 +285,23 @@ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on end + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682_VS + end + end + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682_VD + end end chip drivers/generic/alc1015 register "hid" = ""RTL1019"" -- To view, visit https://review.coreboot.org/c/coreboot/+/69607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60d5e0af7e2dabd134c8059eaeac388d40ac2073 Gerrit-Change-Number: 69607 Gerrit-PatchSet: 4 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/meteorlake: Check MANUF_LOCK when logging manufacturing mode
by Eric Lai (Code Review) 17 Nov '22

17 Nov '22

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69578 ) Change subject: soc/intel/meteorlake: Check MANUF_LOCK when logging manufacturing mode ...................................................................... soc/intel/meteorlake: Check MANUF_LOCK when logging manufacturing mode As per Intel doc #729124 Section 3.6.1 "Intel CSME Production Machine Determination", from ADL onwards there are three criteria which determine whether a device is in production mode: 1. Fuses are programmed 2. SPI descriptor is locked 3. Manufacturing variables are locked When logging whether the device is in manufacturing mode, #1 and #2 are already checked. Add a check for #3 as well. TEST=Build and boot MTL RVP Snippet from coreboot log: [DEBUG] ME: Manufacturing Mode : YES Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I495a7d8730716fc92e8c57b2caef73e8bb44d30b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69578 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> --- M src/soc/intel/meteorlake/me.c 1 file changed, 45 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Jamie Ryu: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved Ivy Jian: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/me.c b/src/soc/intel/meteorlake/me.c index 7d89590..743e963 100644 --- a/src/soc/intel/meteorlake/me.c +++ b/src/soc/intel/meteorlake/me.c @@ -76,6 +76,18 @@ } __packed fields; }; + +/* + * Manufacturing mode is disabled if the descriptor is locked, fuses + * are programmed and manufacturing variables are locked. + * The function returns true if manufacturing mode is disabled otherwise false. + */ +static bool is_eom(union me_hfsts1 hfsts1, union me_hfsts6 hfsts6) +{ + return (hfsts1.fields.mfg_mode == 0) && (hfsts6.fields.manuf_lock == 1) && + (hfsts6.fields.fpf_soc_lock == 1); +} + static void dump_me_status(void *unused) { union me_hfsts1 hfsts1; @@ -102,13 +114,9 @@ printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.data); printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data); - /* - * Lock Descriptor, and Fuses must be programmed on a - * production system to indicate ME Manufacturing mode is disabled. - */ printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - ((hfsts1.fields.mfg_mode == 0) && - (hfsts6.fields.fpf_soc_lock == 1)) ? "NO" : "YES"); + is_eom(hfsts1, hfsts6) ? "NO" : "YES"); + /* * The SPI Protection Mode bit reflects SPI descriptor * locked(0) or unlocked(1). -- To view, visit https://review.coreboot.org/c/coreboot/+/69578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I495a7d8730716fc92e8c57b2caef73e8bb44d30b Gerrit-Change-Number: 69578 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2022