coreboot-gerrit November 2022

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[S] Change in coreboot[master]: util/kconfig: Move Kconfig deps back into build/config
by Felix Held (Code Review) 18 Nov '22

18 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69536 ) Change subject: util/kconfig: Move Kconfig deps back into build/config ...................................................................... util/kconfig: Move Kconfig deps back into build/config revert commit 1b9e740a8 (kconfig: fix failing to generate auto.conf) [1] The above change caused all of the enabled kconfig options to be written into the top level build directory. We don't want that, so go back to the old behavior for the coreboot tree. [1] https://web.archive.org/web/20220316120807/https://github.com/torvalds/linu… Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I2904f69a5d85337ad0a6b48590ccd4b4a6e38b70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69536 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/kconfig/confdata.c 1 file changed, 33 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved Fred Reitberger: Looks good to me, approved diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c index 95fb960..3da9e8b 100644 --- a/util/kconfig/confdata.c +++ b/util/kconfig/confdata.c @@ -230,6 +230,13 @@ return name ? name : "include/generated/autoconf.h"; } +static const char *conf_get_autobase_name(void) +{ + char *name = getenv("KCONFIG_SPLITCONFIG"); + + return name ? name : "include/config/"; +} + static int conf_set_sym_val(struct symbol *sym, int def, int def_flags, char *p) { char *p2; @@ -1024,19 +1031,14 @@ static int conf_touch_deps(void) { - const char *name, *tmp; + const char *name; struct symbol *sym; int res, i; + strcpy(depfile_path, conf_get_autobase_name()); + depfile_prefix_len = strlen(depfile_path); + name = conf_get_autoconfig_name(); - tmp = strrchr(name, '/'); - depfile_prefix_len = tmp ? tmp - name + 1 : 0; - if (depfile_prefix_len + 1 > sizeof(depfile_path)) - return -1; - - strncpy(depfile_path, name, depfile_prefix_len); - depfile_path[depfile_prefix_len] = 0; - conf_read_simple(name, S_DEF_AUTO); sym_calc_value(modules_sym); -- To view, visit https://review.coreboot.org/c/coreboot/+/69536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2904f69a5d85337ad0a6b48590ccd4b4a6e38b70 Gerrit-Change-Number: 69536 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd: Use ioapic helper functions
by Felix Held (Code Review) 18 Nov '22

18 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55571 ) Change subject: soc/amd: Use ioapic helper functions ...................................................................... soc/amd: Use ioapic helper functions Calling setup_ioapic() was only correct for the IOAPIC routing GSI 0..15 that mimic legacy PIC IRQs. Change-Id: Ifdacc61b72f461ec6bea334fa06651c09a9695d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55571 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/acpi.c M src/soc/amd/cezanne/root_complex.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/glinda/acpi.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/morgana/acpi.c M src/soc/amd/morgana/root_complex.c M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/root_complex.c M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/northbridge.c 13 files changed, 41 insertions(+), 31 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 934547d..189e84e 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -26,11 +26,10 @@ /* create all subtables for processors */ current = acpi_create_madt_lapics(current); - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - FCH_IOAPIC_ID, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, + GNB_IO_APIC_ADDR); /* PIT is connected to legacy IRQ 0, but IOAPIC GSI 2 */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 31c2e1a..81b2b96 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -172,7 +172,7 @@ static void root_complex_init(struct device *dev) { - setup_ioapic((u8 *)GNB_IO_APIC_ADDR, GNB_IOAPIC_ID); + register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); } static void acipgen_dptci(void) diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 26e0c26..5633d8f 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -38,7 +38,7 @@ static void fch_ioapic_init(void) { fch_enable_ioapic_decode(); - setup_ioapic(VIO_APIC_VADDR, FCH_IOAPIC_ID); + register_new_ioapic_gsi0(VIO_APIC_VADDR); } static void lpc_init(struct device *dev) diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 5a219cb..85430b9 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -29,11 +29,10 @@ /* create all subtables for processors */ current = acpi_create_madt_lapics(current); - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - FCH_IOAPIC_ID, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, + GNB_IO_APIC_ADDR); /* PIT is connected to legacy IRQ 0, but IOAPIC GSI 2 */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index 04d0599..5cc88f1 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -187,7 +187,7 @@ static void root_complex_init(struct device *dev) { - setup_ioapic((u8 *)GNB_IO_APIC_ADDR, GNB_IOAPIC_ID); + register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); } static void acipgen_dptci(void) diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 779ea4e..b867930 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -28,11 +28,10 @@ /* create all subtables for processors */ current = acpi_create_madt_lapics(current); - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - FCH_IOAPIC_ID, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, + GNB_IO_APIC_ADDR); /* PIT is connected to legacy IRQ 0, but IOAPIC GSI 2 */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index abc49cf..0d24a25 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -187,7 +187,7 @@ static void root_complex_init(struct device *dev) { - setup_ioapic((u8 *)GNB_IO_APIC_ADDR, GNB_IOAPIC_ID); + register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); } static void acipgen_dptci(void) diff --git a/src/soc/amd/morgana/acpi.c b/src/soc/amd/morgana/acpi.c index 945dc54..5eb21ff 100644 --- a/src/soc/amd/morgana/acpi.c +++ b/src/soc/amd/morgana/acpi.c @@ -29,11 +29,10 @@ /* create all subtables for processors */ current = acpi_create_madt_lapics(current); - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - FCH_IOAPIC_ID, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, + GNB_IO_APIC_ADDR); /* PIT is connected to legacy IRQ 0, but IOAPIC GSI 2 */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, diff --git a/src/soc/amd/morgana/root_complex.c b/src/soc/amd/morgana/root_complex.c index 10e5415..5a1a4ad 100644 --- a/src/soc/amd/morgana/root_complex.c +++ b/src/soc/amd/morgana/root_complex.c @@ -187,7 +187,7 @@ static void root_complex_init(struct device *dev) { - setup_ioapic((u8 *)GNB_IO_APIC_ADDR, GNB_IOAPIC_ID); + register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); } static void acipgen_dptci(void) diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index a8639eb..2af6459 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -33,11 +33,10 @@ /* create all subtables for processors */ current = acpi_create_madt_lapics(current); - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - FCH_IOAPIC_ID, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, + GNB_IO_APIC_ADDR); /* PIT is connected to legacy IRQ 0, but IOAPIC GSI 2 */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index c662320..9af9c0a 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -169,7 +169,7 @@ static void root_complex_init(struct device *dev) { - setup_ioapic((u8 *)GNB_IO_APIC_ADDR, GNB_IOAPIC_ID); + register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); } static void acipgen_dptci(void) diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index d6f7048..20221d2 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -29,11 +29,9 @@ current = acpi_create_madt_lapics(current); /* Write Kern IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - FCH_IOAPIC_ID, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, - GNB_IOAPIC_ID, IO_APIC2_ADDR, 24); + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC2_ADDR); /* PIT is connected to legacy IRQ 0, but IOAPIC GSI 2 */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 7e93896..3960a39 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -164,7 +164,7 @@ static void northbridge_init(struct device *dev) { - setup_ioapic((u8 *)IO_APIC2_ADDR, GNB_IOAPIC_ID); + register_new_ioapic((u8 *)IO_APIC2_ADDR); } static unsigned long acpi_fill_hest(acpi_hest_t *hest) -- To view, visit https://review.coreboot.org/c/coreboot/+/55571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdacc61b72f461ec6bea334fa06651c09a9695d6 Gerrit-Change-Number: 55571 Gerrit-PatchSet: 12 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: [RFC] Pull ligfxinit in romstage
by build bot (Jenkins) (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Tarun Tuli, Martin L Roth, Subrata Banik, Andrey Petrov. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69757 ) Change subject: [RFC] Pull ligfxinit in romstage ...................................................................... Patch Set 1: (18 comments) File src/drivers/intel/fsp2_0/memory_init.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163987): https://review.coreboot.org/c/coreboot/+/69757/comment/2a0beed9_0b097027 PS1, Line 53: struct cpuid_result cp = cpuid_ext(1, 0); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163987): https://review.coreboot.org/c/coreboot/+/69757/comment/f3a13bc6_98ad0937 PS1, Line 56: if (!(cp.ecx & (1 << 6))) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163987): https://review.coreboot.org/c/coreboot/+/69757/comment/d269e6ee_49941f55 PS1, Line 56: if (!(cp.ecx & (1 << 6))) suspect code indent for conditional statements (7, 15) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163987): https://review.coreboot.org/c/coreboot/+/69757/comment/5aefd118_8da2379d PS1, Line 57: return; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163987): https://review.coreboot.org/c/coreboot/+/69757/comment/4d8b946e_1da0068d PS1, Line 57: return; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163987): https://review.coreboot.org/c/coreboot/+/69757/comment/dc7ade44_bb69f993 PS1, Line 60: if (!(read32((void *)0xfed30010) & 1)) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163987): https://review.coreboot.org/c/coreboot/+/69757/comment/2993709e_6a6159c8 PS1, Line 60: if (!(read32((void *)0xfed30010) & 1)) suspect code indent for conditional statements (7, 15) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163987): https://review.coreboot.org/c/coreboot/+/69757/comment/d102fcfb_101eca98 PS1, Line 61: return; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163987): https://review.coreboot.org/c/coreboot/+/69757/comment/1cffb928_6c37f20b PS1, Line 61: return; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163987): https://review.coreboot.org/c/coreboot/+/69757/comment/4be29b68_83ab77f0 PS1, Line 64: while (!(read8((void *)0xfed40000) & (1 << 7))) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163987): https://review.coreboot.org/c/coreboot/+/69757/comment/cf938435_1c6c7c40 PS1, Line 64: while (!(read8((void *)0xfed40000) & (1 << 7))) suspect code indent for conditional statements (7, 15) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163987): https://review.coreboot.org/c/coreboot/+/69757/comment/bb3b70b6_d764076b PS1, Line 65: ; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163987): https://review.coreboot.org/c/coreboot/+/69757/comment/16328cf4_79b8f6a0 PS1, Line 65: ; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163987): https://review.coreboot.org/c/coreboot/+/69757/comment/4eaa392f_5de2221d PS1, Line 288: printk(BIOS_DEBUG, "J2M: Initalizing backlight\n"); 'Initalizing' may be misspelled - perhaps 'Initializing'? File src/soc/intel/common/block/graphics/graphics.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163987): https://review.coreboot.org/c/coreboot/+/69757/comment/137d0cbf_7c85b25e PS1, Line 43: /* graphics_soc_panel_init(dev); */ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163987): https://review.coreboot.org/c/coreboot/+/69757/comment/5dc3a0b6_5979e68c PS1, Line 72: /* int lightup_ok; */ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163987): https://review.coreboot.org/c/coreboot/+/69757/comment/e4140ad3_c1596564 PS1, Line 73: /* gma_gfxinit(&lightup_ok); */ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163987): https://review.coreboot.org/c/coreboot/+/69757/comment/4508fbb1_00b7a41a PS1, Line 74: /* gfx_set_init_done(lightup_ok); */ please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/69757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3357e746a7d94afe9d285c36ed6172c7bfd9718 Gerrit-Change-Number: 69757 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 23:28:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [DONOTMERGE] soc/intel/alderlake: Add panel support
by build bot (Jenkins) (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69754 ) Change subject: [DONOTMERGE] soc/intel/alderlake: Add panel support ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/graphics.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163984): https://review.coreboot.org/c/coreboot/+/69754/comment/eba345d2_8fd168e9 PS1, Line 48: printk(BIOS_DEBUG, "J2M: Initalizing backlight\n"); 'Initalizing' may be misspelled - perhaps 'Initializing'? -- To view, visit https://review.coreboot.org/c/coreboot/+/69754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44d957ff902c60f1d3281a05a618a5d89ace8022 Gerrit-Change-Number: 69754 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Thu, 17 Nov 2022 23:27:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [DONOTMERGE] DEBUG_ADA_CODE
by Jérémy Compostella (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik. Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69779 ) Change subject: [DONOTMERGE] DEBUG_ADA_CODE ...................................................................... [DONOTMERGE] DEBUG_ADA_CODE Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Change-Id: I5a1efdaa3fbfdffd3a80f7d93a3e4ad2bd3aadbe --- M src/soc/intel/alderlake/Kconfig 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/69779/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 2bd59a9..1026551 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -50,6 +50,7 @@ select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USE_LIBGFXINIT select VGA_TEXT_FRAMEBUFFER + select DEBUG_ADA_CODE select GFX_GMA select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_ADL_IPU_ES_SUPPORT -- To view, visit https://review.coreboot.org/c/coreboot/+/69779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a1efdaa3fbfdffd3a80f7d93a3e4ad2bd3aadbe Gerrit-Change-Number: 69779 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: [DONOTMERGE] Force VGA_TEXT_FRAMEBUFFER
by Jérémy Compostella (Code Review) 18 Nov '22

18 Nov '22

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69758 ) Change subject: [DONOTMERGE] Force VGA_TEXT_FRAMEBUFFER ...................................................................... [DONOTMERGE] Force VGA_TEXT_FRAMEBUFFER Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Change-Id: Ia148f43264611ba66854f8d39a511dea227ba06c --- M src/device/Kconfig M src/soc/intel/common/block/graphics/graphics.c 2 files changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/69758/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index 34600ad..25e8cb9 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -425,9 +425,9 @@ choice prompt "Framebuffer mode" + default VGA_TEXT_FRAMEBUFFER default VBE_LINEAR_FRAMEBUFFER if HAVE_VBE_LINEAR_FRAMEBUFFER && WANT_LINEAR_FRAMEBUFFER default GENERIC_LINEAR_FRAMEBUFFER if HAVE_LINEAR_FRAMEBUFFER && WANT_LINEAR_FRAMEBUFFER - default VGA_TEXT_FRAMEBUFFER config VGA_TEXT_FRAMEBUFFER bool "Legacy VGA text mode" diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 36ec61e..3206072 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -15,6 +15,11 @@ #include <fsp/graphics.h> #include <soc/pci_devs.h> #include <types.h> +#include <delay.h> +#include <pc80/vga.h> +#include <pc80/vga_io.h> +#include <device/pci_ops.h> +#include <device/pci_type.h> /* SoC Overrides */ __weak void graphics_soc_panel_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/69758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia148f43264611ba66854f8d39a511dea227ba06c Gerrit-Change-Number: 69758 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[master]: [RFC] Pull ligfxinit in romstage
by Jérémy Compostella (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Tarun Tuli, Martin L Roth, Subrata Banik, Andrey Petrov. Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69757 ) Change subject: [RFC] Pull ligfxinit in romstage ...................................................................... [RFC] Pull ligfxinit in romstage Change-Id: If3357e746a7d94afe9d285c36ed6172c7bfd9718 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M Makefile M src/arch/x86/car.ld M src/console/Makefile.inc M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/gma/Kconfig M src/drivers/intel/gma/Makefile.inc M src/drivers/pc80/vga/Makefile.inc M src/include/adainit.h M src/lib/Kconfig M src/lib/Makefile.inc M src/lib/gnat/Makefile.inc M src/mainboard/google/brya/Makefile.inc M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/common/block/graphics/graphics.c 16 files changed, 271 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/69757/1 diff --git a/Makefile b/Makefile index 58cd85b..d09032d 100644 --- a/Makefile +++ b/Makefile @@ -315,6 +315,9 @@ ifeq ($(CONFIG_RAMSTAGE_ADA),y) ramstage-srcs += $(obj)/ramstage/$(notdir $(KCONFIG_AUTOADS)) endif +ifeq ($(CONFIG_ROMSTAGE_ADA),y) +romstage-srcs += $(obj)/romstage/$(notdir $(KCONFIG_AUTOADS)) +endif # To track dependencies, we need all Ada specification (.ads) files in # *-srcs. Extract / filter all specification files that have a matching diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 47afd78..604fe35 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -67,6 +67,7 @@ *(.bss.*) *(.sbss) *(.sbss.*) + *(.data.*) . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _ebss = .; RECORD_SIZE(bss) @@ -118,8 +119,7 @@ . = 0xffffff00; .illegal_globals . : { - *(.data) - *(.data.*) + } _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index e2a20d7..4296426 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -5,6 +5,8 @@ ifeq ($(CONFIG_HWBASE_DEBUG_CB),y) ramstage-$(CONFIG_RAMSTAGE_LIBHWBASE) += hw-debug_sink.ads ramstage-$(CONFIG_RAMSTAGE_LIBHWBASE) += hw-debug_sink.adb +romstage-$(CONFIG_ROMSTAGE_LIBHWBASE) += hw-debug_sink.ads +romstage-$(CONFIG_ROMSTAGE_LIBHWBASE) += hw-debug_sink.adb endif smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 8c36063..b40b540 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -39,6 +39,14 @@ 1. Added ExtendedImageRevision field in FSP_INFO_HEADER 2. Added FSP_NON_VOLATILE_STORAGE_HOB2 +config DISPLAY_MSG_DURING_MEMORY_TRAINING + bool + default n + depends on GFX_GMA && VGA + help + Display a message on-screen notifying the end-user that + memory training is in progress + if PLATFORM_USES_FSP2_0 config PLATFORM_USES_FSP2_X86_32 diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 99b0fea..cf5a3bd 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -3,10 +3,16 @@ #include <arch/null_breakpoint.h> #include <arch/symbols.h> #include <assert.h> +#include <drivers/intel/gma/libgfxinit.h> +#include <arch/cpu.h> +#include <arch/io.h> +#include <bootmode.h> #include <cbfs.h> #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> +#include <cpu/x86/msr.h> +#include <device/mmio.h> #include <elog.h> #include <fsp/api.h> #include <fsp/util.h> @@ -23,10 +29,42 @@ #include <timestamp.h> #include <types.h> #include <vb2_api.h> +#include <mode_switch.h> +#include <drivers/intel/gma/i915_reg.h> +#include <arch/mmio.h> +#include <pc80/vga.h> +#include <pc80/vga_io.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci.h> +#include <timer.h> +#include <inttypes.h> +#include <delay.h> +#include <adainit.h> static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); static void save_memory_training_data(uint32_t fsp_version) + +static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); + +static void wait_txt_clear(void) +{ + struct cpuid_result cp = cpuid_ext(1, 0); + + /* Check if TXT is supported */ + if (!(cp.ecx & (1 << 6))) + return; + + /* Some TXT public bit */ + if (!(read32((void *)0xfed30010) & 1)) + return; + + /* Wait for TXT clear */ + while (!(read8((void *)0xfed40000) & (1 << 7))) + ; +} +static void save_memory_training_data(bool s3wake, uint32_t fsp_version) { size_t mrc_data_size; const void *mrc_data; @@ -221,6 +259,109 @@ struct memranges memmap; }; +static void panel_init(void) +{ + uint32_t cycle_delay_ms = 500; + uint32_t up_delay_ms = 200; + uint32_t backlight_on_delay_ms = 1; + uint32_t down_delay_ms = 50; + uint32_t backlight_off_delay_ms = 200; + uint32_t backlight_pwm_hz = 200; + void *mmio = (void *)0x81000000; + uint32_t reg32; + unsigned int pwm_period, pwm_polarity, pwm_duty; + + reg32 = ((DIV_ROUND_UP(cycle_delay_ms, 100) + 1) & 0x1f) << 4; + reg32 |= PANEL_POWER_RESET; + write32(mmio + PCH_PP_CONTROL, reg32); + + reg32 = ((up_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (backlight_on_delay_ms * 10) & 0x1fff; + write32(mmio + PCH_PP_ON_DELAYS, reg32); + + reg32 = ((down_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (backlight_off_delay_ms * 10) & 0x1fff; + write32(mmio + PCH_PP_OFF_DELAYS, reg32); + + /* Backlight */ + if (backlight_pwm_hz) { + printk(BIOS_DEBUG, "J2M: Initalizing backlight\n"); + pwm_polarity = 0; + pwm_period = DIV_ROUND_CLOSEST(CONFIG_CPU_XTAL_HZ, backlight_pwm_hz); + pwm_duty = DIV_ROUND_CLOSEST(pwm_period, 2); /* Start with 50 % */ + + write32(mmio + BXT_BLC_PWM_FREQ(0), pwm_period); + write32(mmio + BXT_BLC_PWM_CTL(0), pwm_polarity); + write32(mmio + BXT_BLC_PWM_DUTY(0), pwm_duty); + } +} + +static void mrc_splash_screen(void) +{ + int lightup_ok; + + /* + * We can generally jump between C and Ada code back and forth + * without trouble. But since we don't have an Ada main() we + * have to do some Ada package initializations that GNAT would + * do there. This has to be done before calling any Ada code. + * + * The package initializations should not have any dependen- + * cies on C code. So we can call them here early, and don't + * have to worry at which point we can start to use Ada. + */ + printk(BIOS_DEBUG, "J2M: About to call romstage_adainit()\n"); + romstage_adainit(); + printk(BIOS_DEBUG, "J2M: Done.\n"); + + /* Unlock memory before accessing 0xB8000 (VGA Frame buffer) address*/ + msr_t msrval; + wait_txt_clear(); + msrval.lo = 0; + msrval.hi = 0; + wrmsr(0x2e6, msrval); + + pci_write_config16(PCI_DEV(0, 0, 0), PCI_COMMAND, 6); + printk(BIOS_DEBUG, "J2M: About to perform panel initialization...\n"); + + printk(BIOS_DEBUG, "J2M: panel initialization done.\n"); + pci_or_config16(PCI_DEV(0, 2, 0), PCI_COMMAND, PCI_COMMAND_MASTER); + + printk(BIOS_DEBUG, "J2M: %s - pci_read_config32(PCI_DEV(2, 0), 0x0)=0x%x\n", + __func__, pci_read_config32(PCI_DEV(0, 2, 0), 0x0)); + pci_write_config32(PCI_DEV(0, 2, 0), 0x10, 0x81000004); + pci_write_config32(PCI_DEV(0, 2, 0), 0x18, 0x9000000c); + pci_write_config32(PCI_DEV(0, 2, 0), 0x20, 0x1001); + pci_write_config16(PCI_DEV(0, 2, 0), PCI_COMMAND, 3); + printk(BIOS_DEBUG, "J2M: %s - pci_read_config32(PCI_DEV(2, 0), 0x10)=0x%x\n", + __func__, pci_read_config32(PCI_DEV(0, 2, 0), 0x10)); + printk(BIOS_DEBUG, "J2M: %s - pci_read_config32(PCI_DEV(2, 0), 0x18)=0x%x\n", + __func__, pci_read_config32(PCI_DEV(0, 2, 0), 0x18)); + printk(BIOS_DEBUG, "J2M: %s - pci_read_config32(PCI_DEV(2, 0), 0x20)=0x%x\n", + __func__, pci_read_config32(PCI_DEV(0, 2, 0), 0x20)); + + panel_init(); + + printk(BIOS_DEBUG, "J2M: PCH_PP_ON_DELAYS - 0x810c7208=0x%x", *(volatile uint32_t *)0x810c7208); + + printk(BIOS_DEBUG, "J2M: About to run libgfxinit...\n"); + gma_gfxinit(&lightup_ok); + gfx_set_init_done(lightup_ok); + if (!lightup_ok) { + printk(BIOS_DEBUG, "J2M: libgfxinit failed.\n"); + return; + } + printk(BIOS_DEBUG, "J2M: libgfxinit done.\n"); + + vga_textmode_init(); + for (size_t line = 0 ; line < 20; line++) + vga_line_write(line, "Welcome to ROMSTAGE !"); + + printk(BIOS_DEBUG, "J2M: Going to wait for 10s...\n"); + udelay(10 * 1000 * 1000); + printk(BIOS_DEBUG, "J2M: Done. Resuming boot now.\n"); +} + static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) { uint32_t status; @@ -286,6 +427,8 @@ if (CONFIG(MMA)) setup_mma(&fspm_upd.FspmConfig); + printk(BIOS_DEBUG, "J2M: Right before memory training init\n"); + mrc_splash_screen(); post_code(POST_MEM_PREINIT_PREP_END); /* Call FspMemoryInit */ diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index d0aff4c..c9a5360 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -88,7 +88,8 @@ || SOC_INTEL_COMMON_SKYLAKE_BASE || SOC_INTEL_APOLLOLAKE \ || SOC_INTEL_CANNONLAKE_BASE || SOC_INTEL_ALDERLAKE depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID - select RAMSTAGE_LIBHWBASE + select ROMSTAGE_LIBHWBASE if DISPLAY_MSG_DURING_MEMORY_TRAINING + select RAMSTAGE_LIBHWBASE if !DISPLAY_MSG_DURING_MEMORY_TRAINING config GFX_GMA_PANEL_1_ON_EDP bool diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index 5588e5a..355a7f0 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -22,6 +22,8 @@ ifeq ($(CONFIG_GFX_GMA),y) +ifeq ($(CONFIG_RAMSTAGE_LIBHWBASE),y) + $(call add-special-class,gfxinit) gfxinit-handler = $(eval ramstage-srcs += $(1)$(2)) @@ -46,4 +48,35 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += text_fb/gma-gfx_init.adb endif +endif # CONFIG_RAMSTAGE_LIBHWBASE + +ifeq ($(CONFIG_ROMSTAGE_LIBHWBASE),y) + +$(call add-special-class,gfxinit) +gfxinit-handler = \ + $(eval romstage-srcs += $(1)$(2)) + +$(call add-special-class,gfxinit-gen) +gfxinit-gen-handler = \ + $(eval additional-dirs += $(dir $(2))) \ + $(eval romstage-srcs += $(2)) \ + $(eval romstage-ads-deps += $(2)) \ + $(eval romstage-adb-deps += $(2)) \ + $(eval $(2): $(obj)/config.h) + +CONFIG_GFX_GMA_DEFAULT_MMIO := 0 # dummy, will be overwritten at runtime + +subdirs-y += ../../../../3rdparty/libgfxinit + +romstage-y += gma.ads gma.adb + +romstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-gfx_init.ads +ifeq ($(CONFIG_LINEAR_FRAMEBUFFER),y) +romstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += hires_fb/gma-gfx_init.adb +else +romstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += text_fb/gma-gfx_init.adb +endif + +endif # CONFIG_ROMSTAGE_LIBHWBASE + endif # CONFIG_GFX_GMA diff --git a/src/drivers/pc80/vga/Makefile.inc b/src/drivers/pc80/vga/Makefile.inc index 3e31de1..d5370bd 100644 --- a/src/drivers/pc80/vga/Makefile.inc +++ b/src/drivers/pc80/vga/Makefile.inc @@ -5,4 +5,9 @@ ramstage-$(CONFIG_VGA) += vga_font_8x16.c ramstage-$(CONFIG_VGA) += vga.c +romstage-$(CONFIG_VGA) += vga_io.c +romstage-$(CONFIG_VGA) += vga_palette.c +romstage-$(CONFIG_VGA) += vga_font_8x16.c +romstage-$(CONFIG_VGA) += vga.c + endif diff --git a/src/include/adainit.h b/src/include/adainit.h index 4953d44..389499e 100644 --- a/src/include/adainit.h +++ b/src/include/adainit.h @@ -21,4 +21,10 @@ static inline void ramstage_adainit(void) {} #endif +#if CONFIG(ROMSTAGE_ADA) +void romstage_adainit(void); +#else +static inline void romstage_adainit(void) {} +#endif + #endif /* _ADAINIT_H */ diff --git a/src/lib/Kconfig b/src/lib/Kconfig index ae96fc6..91726b0 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -10,12 +10,23 @@ help Selected by features that use Ada code in ramstage. +config ROMSTAGE_ADA + bool + help + Selected by features that use Ada code in ramstage. + config RAMSTAGE_LIBHWBASE bool select RAMSTAGE_ADA help Selected by features that require `libhwbase` in ramstage. +config ROMSTAGE_LIBHWBASE + bool + select ROMSTAGE_ADA + help + Selected by features that require `libhwbase` in ramstage. + config FLATTENED_DEVICE_TREE bool help @@ -63,7 +74,7 @@ help Name of the FMAP region created in the default FMAP to cache SPD data. -if RAMSTAGE_LIBHWBASE +if RAMSTAGE_LIBHWBASE || ROMSTAGE_LIBHWBASE config HWBASE_DYNAMIC_MMIO def_bool y diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1c7bc22..bc26179 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -340,6 +340,7 @@ $(RMODTOOL) -i $< -o $@ ramstage-$(CONFIG_RAMSTAGE_ADA) += cb.ads +romstage-$(CONFIG_ROMSTAGE_ADA) += cb.ads ifeq ($(CONFIG_RAMSTAGE_LIBHWBASE),y) @@ -364,6 +365,30 @@ endif # CONFIG_RAMSTAGE_LIBHWBASE +ifeq ($(CONFIG_ROMSTAGE_LIBHWBASE),y) + +to-ada-hex = $(eval $(1) := 16\\\#$(patsubst 0x%,%,$($(1)))\\\#) + +$(call to-ada-hex,CONFIG_HWBASE_DEFAULT_MMCONF) + +$(call add-special-class,hw) +hw-handler = \ + $(eval romstage-srcs += $$(addprefix $(1),$(2))) + +$(call add-special-class,hw-gen) +hw-gen-handler = \ + $(eval additional-dirs += $(dir $(2))) \ + $(eval romstage-srcs += $(2)) \ + $(eval romstage-ads-deps += $(2)) \ + $(eval romstage-adb-deps += $(2)) \ + $(eval $(2): $(obj)/config.h) + +subdirs-y += ../../3rdparty/libhwbase + +romstage-$(CONFIG_HAVE_MONOTONIC_TIMER) += hw-time-timer.adb + +endif # CONFIG_ROMSTAGE_LIBHWBASE + romstage-y += spd_bin.c ifeq ($(CONFIG_HAVE_SPD_IN_CBFS),y) diff --git a/src/lib/gnat/Makefile.inc b/src/lib/gnat/Makefile.inc index 065ba71..f52c107 100644 --- a/src/lib/gnat/Makefile.inc +++ b/src/lib/gnat/Makefile.inc @@ -54,3 +54,6 @@ ifeq ($(CONFIG_RAMSTAGE_ADA),y) ramstage-libs += $(obj)/libgnat-$(ARCH-ramstage-y)/libgnat.a endif +ifeq ($(CONFIG_ROMSTAGE_ADA),y) +romstage-libs += $(obj)/libgnat-$(ARCH-ramstage-y)/libgnat.a +endif diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc index 98a08f2..9b80342 100644 --- a/src/mainboard/google/brya/Makefile.inc +++ b/src/mainboard/google/brya/Makefile.inc @@ -20,4 +20,9 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads \ No newline at end of file +ifeq ($(CONFIG_RAMSTAGE_ADA),y) +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +endif +ifeq ($(CONFIG_ROMSTAGE_ADA),y) +romstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +endif \ No newline at end of file diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index abd0570..2bd59a9 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -45,6 +45,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y + select DISPLAY_MSG_DURING_MEMORY_TRAINING select ENABLE_TCSS_DISPLAY_DETECTION select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USE_LIBGFXINIT @@ -76,7 +77,7 @@ select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_GMA_ACPI - select INTEL_GMA_ADD_VBT if RUN_FSP_GOP + select INTEL_GMA_ADD_VBT select INTEL_GMA_OPREGION_2_1 select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 26eba76..912528a 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -613,8 +613,8 @@ s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get(); /* Check if IGD is present and fill Graphics init param accordingly */ - s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); - s_cfg->LidStatus = CONFIG(RUN_FSP_GOP); + s_cfg->PeiGraphicsPeimInit = is_devfn_enabled(SA_DEVFN_IGD); + s_cfg->LidStatus = 1; s_cfg->PavpEnable = CONFIG(PAVP); } diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index dae181a..36ec61e 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -39,8 +39,8 @@ If FSP has already run/configured the IGD, we can assume the panel/backlight control have already been set up sufficiently and that we shouldn't attempt to reconfigure things. */ - if (!CONFIG(RUN_FSP_GOP)) - graphics_soc_panel_init(dev); + /* if (!CONFIG(RUN_FSP_GOP)) */ + /* graphics_soc_panel_init(dev); */ if (CONFIG(SOC_INTEL_CONFIGURE_DDI_A_4_LANES) && !acpi_is_wakeup_s3()) { const u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); @@ -68,11 +68,11 @@ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { - if (!acpi_is_wakeup_s3() && display_init_required()) { - int lightup_ok; - gma_gfxinit(&lightup_ok); - gfx_set_init_done(lightup_ok); - } + /* if (!acpi_is_wakeup_s3() && display_init_required()) { */ + /* int lightup_ok; */ + /* gma_gfxinit(&lightup_ok); */ + /* gfx_set_init_done(lightup_ok); */ + /* } */ } else { /* Initialize PCI device, load/execute BIOS Option ROM */ pci_dev_init(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/69757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3357e746a7d94afe9d285c36ed6172c7bfd9718 Gerrit-Change-Number: 69757 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: [RFC] Remove dependency on RUN_FSP_GOP
by Jérémy Compostella (Code Review) 18 Nov '22

18 Nov '22

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69756 ) Change subject: [RFC] Remove dependency on RUN_FSP_GOP ...................................................................... [RFC] Remove dependency on RUN_FSP_GOP Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Change-Id: I58cc0660f5cebe8bcd4108929f6696d34b7f40c5 --- M src/soc/intel/common/block/tcss/Kconfig 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/69756/1 diff --git a/src/soc/intel/common/block/tcss/Kconfig b/src/soc/intel/common/block/tcss/Kconfig index 2e67913..7a0bacb 100644 --- a/src/soc/intel/common/block/tcss/Kconfig +++ b/src/soc/intel/common/block/tcss/Kconfig @@ -6,6 +6,6 @@ config ENABLE_TCSS_DISPLAY_DETECTION bool "Enable detection of displays over USB Type-C ports with TCSS" - depends on SOC_INTEL_COMMON_BLOCK_TCSS && RUN_FSP_GOP + depends on SOC_INTEL_COMMON_BLOCK_TCSS help Enable displays to be detected over Type-C ports during boot. -- To view, visit https://review.coreboot.org/c/coreboot/+/69756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58cc0660f5cebe8bcd4108929f6696d34b7f40c5 Gerrit-Change-Number: 69756 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: [DONOTMERGE] brya/skolas: graphic configuration
by Jérémy Compostella (Code Review) 18 Nov '22

18 Nov '22

Attention is currently required from: Tarun Tuli. Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69755 ) Change subject: [DONOTMERGE] brya/skolas: graphic configuration ...................................................................... [DONOTMERGE] brya/skolas: graphic configuration Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Change-Id: Iddc2d9b2fe3dc15a4f6706e90db6268ce4ce2043 --- M src/drivers/intel/gma/Kconfig M src/mainboard/google/brya/Makefile.inc A src/mainboard/google/brya/gma-mainboard.ads M src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb 4 files changed, 42 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/69755/1 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 87f6d12..d0aff4c 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -86,7 +86,7 @@ || NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE \ || NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL \ || SOC_INTEL_COMMON_SKYLAKE_BASE || SOC_INTEL_APOLLOLAKE \ - || SOC_INTEL_CANNONLAKE_BASE + || SOC_INTEL_CANNONLAKE_BASE || SOC_INTEL_ALDERLAKE depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID select RAMSTAGE_LIBHWBASE @@ -125,6 +125,7 @@ default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL default "Ironlake" if NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X + default "Tigerlake" if SOC_INTEL_ALDERLAKE config GFX_GMA_PCH string @@ -133,6 +134,7 @@ default "Lynx_Point" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL default "Sunrise_Point" if SOC_INTEL_COMMON_SKYLAKE_BASE default "Cannon_Point" if SOC_INTEL_CANNONLAKE_BASE + default "Alder_Point" if SOC_INTEL_ALDERLAKE default "No_PCH" config GFX_GMA_PANEL_1_PORT diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc index c40f21c..98a08f2 100644 --- a/src/mainboard/google/brya/Makefile.inc +++ b/src/mainboard/google/brya/Makefile.inc @@ -20,3 +20,4 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads \ No newline at end of file diff --git a/src/mainboard/google/brya/gma-mainboard.ads b/src/mainboard/google/brya/gma-mainboard.ads new file mode 100644 index 0000000..a7023d5 --- /dev/null +++ b/src/mainboard/google/brya/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; +private package GMA.Mainboard is + + + -- NOTE: your board probably doesn’t have ALL of these + -- outputs; only list the ones your board actually has here. + ports : constant Port_List := + (eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb index c861c9b..485ea90 100644 --- a/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb @@ -127,7 +127,17 @@ }" device domain 0 on - device ref igpu on end + device ref igpu on + register "gfx" = "GMA_DEFAULT_PANEL(0)" + # Power Sequence: T3 2000 T7 10 T9 2000 T10 500 T12 5000 + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200,}" + end device ref dtt on end device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp1 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/69755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddc2d9b2fe3dc15a4f6706e90db6268ce4ce2043 Gerrit-Change-Number: 69755 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: [DONOTMERGE] soc/intel/alderlake: Add panel support
by Jérémy Compostella (Code Review) 18 Nov '22

18 Nov '22

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69754 ) Change subject: [DONOTMERGE] soc/intel/alderlake: Add panel support ...................................................................... [DONOTMERGE] soc/intel/alderlake: Add panel support Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Change-Id: I44d957ff902c60f1d3281a05a618a5d89ace8022 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/graphics.c 3 files changed, 80 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/69754/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 08d4132..abd0570 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -45,6 +45,11 @@ config CPU_SPECIFIC_OPTIONS def_bool y + select ENABLE_TCSS_DISPLAY_DETECTION + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USE_LIBGFXINIT + select VGA_TEXT_FRAMEBUFFER + select GFX_GMA select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_ADL_IPU_ES_SUPPORT select ARCH_X86 diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index a732fe6..c9d713f 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -6,6 +6,7 @@ #include <drivers/i2c/designware/dw_i2c.h> #include <drivers/intel/gma/gma.h> #include <device/pci_ids.h> +#include <drivers/intel/gma/gma.h> #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> @@ -256,6 +257,17 @@ /* Common struct containing power limits configuration information */ struct soc_power_limits_config power_limits_config[ADL_POWER_LIMITS_COUNT]; + /* + * IGD panel configuration + * + * Second backlight control shares logic with other pins (aka. display utility pin). + * Be sure it's used for PWM before setting any secondary backlight value. + */ + struct i915_gpu_panel_config panel_cfg; + + /* i915 struct for GMA backlight control */ + struct i915_gpu_controller_info gfx; + /* Gpio group routed to each dword of the GPE0 block. Values are * of the form PMC_GPP_[A:U] or GPD. */ uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ diff --git a/src/soc/intel/alderlake/graphics.c b/src/soc/intel/alderlake/graphics.c index f2c792c..41d9d7c 100644 --- a/src/soc/intel/alderlake/graphics.c +++ b/src/soc/intel/alderlake/graphics.c @@ -1,7 +1,60 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <commonlib/helpers.h> +#include <device/device.h> +#include <device/mmio.h> +#include <device/pci_def.h> +#include <device/resource.h> +#include <drivers/intel/gma/i915_reg.h> #include <intelblocks/graphics.h> #include <soc/ramstage.h> +#include <types.h> + +void graphics_soc_panel_init(struct device *dev) +{ + const struct soc_intel_alderlake_config *conf = dev->chip_info; + const struct i915_gpu_panel_config *panel_cfg; + const struct resource *mmio_res; + void *mmio; + uint32_t reg32; + unsigned int pwm_period, pwm_polarity, pwm_duty; + + if (!conf) + return; + + panel_cfg = &conf->panel_cfg; + + mmio_res = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (!mmio_res || !mmio_res->base) + return; + mmio = (void *)(uintptr_t)mmio_res->base; + + /* Panel timings */ + + reg32 = ((DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f) << 4; + reg32 |= PANEL_POWER_RESET; + write32(mmio + PCH_PP_CONTROL, reg32); + + reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff; + write32(mmio + PCH_PP_ON_DELAYS, reg32); + + reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff; + write32(mmio + PCH_PP_OFF_DELAYS, reg32); + + /* Backlight */ + if (panel_cfg->backlight_pwm_hz) { + printk(BIOS_DEBUG, "J2M: Initalizing backlight\n"); + pwm_polarity = panel_cfg->backlight_polarity ? BXT_BLC_PWM_POLARITY : 0; + pwm_period = DIV_ROUND_CLOSEST(CONFIG_CPU_XTAL_HZ, panel_cfg->backlight_pwm_hz); + pwm_duty = DIV_ROUND_CLOSEST(pwm_period, 2); /* Start with 50 % */ + + write32(mmio + BXT_BLC_PWM_FREQ(0), pwm_period); + write32(mmio + BXT_BLC_PWM_CTL(0), pwm_polarity); + write32(mmio + BXT_BLC_PWM_DUTY(0), pwm_duty); + } +} const struct i915_gpu_controller_info * intel_igd_get_controller_info(const struct device *const dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/69754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44d957ff902c60f1d3281a05a618a5d89ace8022 Gerrit-Change-Number: 69754 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

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