coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[master]: mb/amd/mayan: Add framework for morgana crb mayan
by build bot (Jenkins) (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: ritul guru, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70010 ) Change subject: mb/amd/mayan: Add framework for morgana crb mayan ...................................................................... Patch Set 3: (3 comments) File src/mainboard/amd/mayan/port_descriptors.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164559): https://review.coreboot.org/c/coreboot/+/70010/comment/48b75623_c973bcb2 PS3, Line 104: break; break is not useful after a return Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164559): https://review.coreboot.org/c/coreboot/+/70010/comment/24413c41_33c0c0d7 PS3, Line 108: break; break is not useful after a return Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164559): https://review.coreboot.org/c/coreboot/+/70010/comment/d271e4c6_ff2bba89 PS3, Line 112: break; break is not useful after a return -- To view, visit https://review.coreboot.org/c/coreboot/+/70010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6801e6c6e706ae3878ce9e2c3d6452964235148 Gerrit-Change-Number: 70010 Gerrit-PatchSet: 3 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 25 Nov 2022 18:51:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: security/tpm/: turn tis_{init,open} into tis_probe
by Sergii Dmytruk (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: Michał Żygowski, Christian Walter, Julius Werner, Krystian Hebel, Yu-Ping Wu. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68991 ) Change subject: security/tpm/: turn tis_{init,open} into tis_probe ...................................................................... Patch Set 2: (1 comment) File src/security/tpm/tss/tcg-1.2/tss.c: https://review.coreboot.org/c/coreboot/+/68991/comment/49e13419_4a12d86c PS2, Line 35: tis_sendrecv > How do we make sure this is not NULL? Just by assuming that API is initialized before being used like the code was already doing. -- To view, visit https://review.coreboot.org/c/coreboot/+/68991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4ce35ada24e3959ea1a518c29d431b4ae123809 Gerrit-Change-Number: 68991 Gerrit-PatchSet: 2 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 25 Nov 2022 18:50:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/amd/mayan: Add framework for morgana crb mayan
by ritul guru (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: ritul guru, Felix Held. Hello Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70010 to look at the new patch set (#3). Change subject: mb/amd/mayan: Add framework for morgana crb mayan ...................................................................... mb/amd/mayan: Add framework for morgana crb mayan mayan is the reference board for the morgana SoC. It needs to be updated to match the actual board design as well. amd/mayan is started as a copy of amd/birman. Change-Id: Id6801e6c6e706ae3878ce9e2c3d6452964235148 Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com> --- A src/mainboard/amd/mayan/Kconfig A src/mainboard/amd/mayan/Kconfig.name A src/mainboard/amd/mayan/Makefile.inc A src/mainboard/amd/mayan/board.fmd A src/mainboard/amd/mayan/board_info.txt A src/mainboard/amd/mayan/bootblock.c A src/mainboard/amd/mayan/chromeos.c A src/mainboard/amd/mayan/chromeos.fmd A src/mainboard/amd/mayan/devicetree_morgana.cb A src/mainboard/amd/mayan/dsdt.asl A src/mainboard/amd/mayan/early_gpio.c A src/mainboard/amd/mayan/ec.c A src/mainboard/amd/mayan/ec.h A src/mainboard/amd/mayan/gpio.c A src/mainboard/amd/mayan/gpio.h A src/mainboard/amd/mayan/mainboard.c A src/mainboard/amd/mayan/port_descriptors.c 17 files changed, 812 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/70010/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/70010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6801e6c6e706ae3878ce9e2c3d6452964235148 Gerrit-Change-Number: 70010 Gerrit-PatchSet: 3 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: mb/intel/mtlrvp: Enable EC and building ChromeOS
by Harsha B R (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Wonkyu Kim, Harsha B R, Ravishankar Sarawadi, Paul Menzel, Kapil Porwal, Angel Pons, Nick Vaccaro, Tim Wawrzynczak, Raj Astekar. Harsha B R has uploaded a new patch set (#9) to the change originally created by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/66101 ) Change subject: mb/intel/mtlrvp: Enable EC and building ChromeOS ...................................................................... mb/intel/mtlrvp: Enable EC and building ChromeOS This configures and initializes EC, and adds building ChromeOS. BUG=b:224325352 TEST=FW_NAME=mtlrvp_p emerge-rex coreboot chromeos-bootimage Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: I662d7f79050d35e152d97dc5c2118a4af56223bc Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/Makefile.inc A src/mainboard/intel/mtlrvp/chromeos.c D src/mainboard/intel/mtlrvp/devicetree.cb M src/mainboard/intel/mtlrvp/dsdt.asl A src/mainboard/intel/mtlrvp/ec.c A src/mainboard/intel/mtlrvp/mainboard.c A src/mainboard/intel/mtlrvp/smihandler.c A src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/include/baseboard/ec.h M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/include/baseboard/gpio.h A src/mainboard/intel/mtlrvp/variants/mtlrvp_p/Makefile.inc A src/mainboard/intel/mtlrvp/variants/mtlrvp_p/devicetree.cb A src/mainboard/intel/mtlrvp/variants/mtlrvp_p/gpio.c A src/mainboard/intel/mtlrvp/variants/mtlrvp_p/include/variant/ec.h A src/mainboard/intel/mtlrvp/variants/mtlrvp_p/include/variant/gpio.h 15 files changed, 315 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/66101/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/66101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I662d7f79050d35e152d97dc5c2118a4af56223bc Gerrit-Change-Number: 66101 Gerrit-PatchSet: 9 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: mb/amd/mayan: Add framework for morgana crb mayan
by build bot (Jenkins) (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: ritul guru, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70010 ) Change subject: mb/amd/mayan: Add framework for morgana crb mayan ...................................................................... Patch Set 2: (3 comments) File src/mainboard/amd/mayan/port_descriptors.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164555): https://review.coreboot.org/c/coreboot/+/70010/comment/8a9de2f0_144356fd PS2, Line 104: break; break is not useful after a return Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164555): https://review.coreboot.org/c/coreboot/+/70010/comment/54acea67_e34a2462 PS2, Line 108: break; break is not useful after a return Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164555): https://review.coreboot.org/c/coreboot/+/70010/comment/00f7a321_70fe6e3e PS2, Line 112: break; break is not useful after a return -- To view, visit https://review.coreboot.org/c/coreboot/+/70010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6801e6c6e706ae3878ce9e2c3d6452964235148 Gerrit-Change-Number: 70010 Gerrit-PatchSet: 2 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 25 Nov 2022 18:47:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/amd/mayan: Add framework for morgana crb mayan
by ritul guru (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: ritul guru, Felix Held. Hello Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70010 to look at the new patch set (#2). Change subject: mb/amd/mayan: Add framework for morgana crb mayan ...................................................................... mb/amd/mayan: Add framework for morgana crb mayan mayan is the reference board for the morgana SoC. It needs to be updated to match the actual board design as well. amd/mayan is started as a copy of amd/birman. Change-Id: Id6801e6c6e706ae3878ce9e2c3d6452964235148 Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com> --- A src/mainboard/amd/mayan/Kconfig A src/mainboard/amd/mayan/Kconfig.name A src/mainboard/amd/mayan/Makefile.inc A src/mainboard/amd/mayan/board.fmd A src/mainboard/amd/mayan/board_info.txt A src/mainboard/amd/mayan/bootblock.c A src/mainboard/amd/mayan/chromeos.c A src/mainboard/amd/mayan/chromeos.fmd A src/mainboard/amd/mayan/devicetree_morgana.cb A src/mainboard/amd/mayan/dsdt.asl A src/mainboard/amd/mayan/early_gpio.c A src/mainboard/amd/mayan/ec.c A src/mainboard/amd/mayan/ec.h A src/mainboard/amd/mayan/gpio.c A src/mainboard/amd/mayan/gpio.h A src/mainboard/amd/mayan/mainboard.c A src/mainboard/amd/mayan/port_descriptors.c 17 files changed, 812 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/70010/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6801e6c6e706ae3878ce9e2c3d6452964235148 Gerrit-Change-Number: 70010 Gerrit-PatchSet: 2 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: util/amdfwtool: Deal with psp position in flash offset directly
by Arthur Heymans (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69852 ) Change subject: util/amdfwtool: Deal with psp position in flash offset directly ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/Makefile.inc: https://review.coreboot.org/c/coreboot/+/69852/comment/589b31b0_138fb297 PS4, Line 25: $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 1 $(CONFIG_AMD_FWM_POSITION)) > would it make sense to add flash offset support to cbfstool? It already knows the flash size from the FMAP, right? It knows that from the file size too I guess. -- To view, visit https://review.coreboot.org/c/coreboot/+/69852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89c9e73e7db748379c97e3c0ad69af3faedc8d66 Gerrit-Change-Number: 69852 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 25 Nov 2022 18:36:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/security/vboot: Add platform hook for vboot phase 1
by build bot (Jenkins) (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: Julius Werner, Yu-Ping Wu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70012 ) Change subject: src/security/vboot: Add platform hook for vboot phase 1 ...................................................................... Patch Set 1: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164551): https://review.coreboot.org/c/coreboot/+/70012/comment/8c1f55e1_0478a07b PS1, Line 8: Possible unwrapped commit description (prefer a maximum 72 chars per line) File src/security/vboot/vboot_logic.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164551): https://review.coreboot.org/c/coreboot/+/70012/comment/faaa806a_0240fdfb PS1, Line 327: if(vboot_platform_hook_phase1(ctx, &plat_rec_reason, &plat_rec_subcode)) { space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/70012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4f5347d1af02650a6ee0b261050556d95be21cb Gerrit-Change-Number: 70012 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 25 Nov 2022 17:55:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/{common, alderlake}: implement vboot phase 1 handler
by Rizwan Qureshi (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik. Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70015 ) Change subject: soc/intel/{common, alderlake}: implement vboot phase 1 handler ...................................................................... soc/intel/{common, alderlake}: implement vboot phase 1 handler implement a vboot phase 1 platform handler to switch CSE boot partion early in the boot flow TEST=Build and boot nirwen, make sure CSE parition is switched based on the vboot boot mode. Also make sure that the partition switch does not happen when CSE update is in progress. Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: I2d12fac7dd9f0555d28115275d60934beb85a5e7 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/common/block/cse/cse_lite.c 2 files changed, 98 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/70015/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 08d4132..622ae5d 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -117,6 +117,7 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET + select SOC_INTEL_CSE_LITE_SYNC_IN_BOOTBLOCK select SOC_INTEL_CSE_SEND_EOP_EARLY select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index f051061..1a7493c 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -14,6 +14,7 @@ #include <security/vboot/vboot_common.h> #include <soc/intel/common/reset.h> #include <timestamp.h> +#include <vb2_api.h> #define BPDT_HEADER_SZ sizeof(struct bpdt_header) #define BPDT_ENTRY_SZ sizeof(struct bpdt_entry) @@ -1048,6 +1049,85 @@ return handle_cse_sub_part_fw_update_rv(rv); } +/* + * Use the vboot_platform_hook_phase1 to switch to the right CSE partition + * WE SHOULD NOT perform any updates to CSE partition here + * +*/ +int vboot_platform_hook_phase1(struct vb2_context *ctx, enum vb2_nv_recovery *rec_reason, + uint8_t *subcode) +{ + static struct get_bp_info_rsp cse_bp_info; + uint8_t boot_mode = ctx->boot_mode; + uint8_t hmrfpo_status = HMRFPO_STATUS_DISABLED; + + printk(BIOS_DEBUG, "Syncing CSE boot partition\n"); + + /* If CSE SKU type is not Lite, skip enabling CSE Lite SKU */ + if (!cse_is_hfs3_fw_sku_lite()) { + printk(BIOS_ERR, "cse_lite: Not a CSE Lite SKU\n"); + return 0; + } + + if (!cse_get_bp_info(&cse_bp_info)) { + printk(BIOS_ERR, "cse_lite: Failed to get CSE boot partition info\n"); + *subcode = CSE_COMMUNICATION_ERROR; + goto failure; + } + + /* + * If HMRFPO is enabled, then update is in progress just alow the system to boot + * in the same mode + */ + if (!cse_hmrfpo_get_status(&hmrfpo_status)) { + printk(BIOS_ERR, "cse_lite: CSE could not get HMRFPO status\n"); + *subcode = CSE_COMMUNICATION_ERROR; + goto failure; + } + + printk(BIOS_DEBUG, "cse_lite: HMRFPO status %d\n", hmrfpo_status); + if (hmrfpo_status == HMRFPO_STATUS_ENABLED) { + printk(BIOS_DEBUG, "HMRFPO Enabled, not switching\n"); + return 0; + } + + /* + * If there are any errors, dont try to fix here and also dont try switch boot mode + * allow the errors to be handled later + */ + if (!cse_fix_data_failure_err(&cse_bp_info.bp_info)) { + printk(BIOS_ERR, "cse_lite: CSE data error could not be fixed\n"); + return 0; + } + + if (!cse_is_rw_bp_status_valid(&cse_bp_info.bp_info)) { + printk(BIOS_ERR, "cse_lite: Boot partition errors\n"); + return 0; + } + + if ((boot_mode == VB2_BOOT_MODE_NORMAL || boot_mode == VB2_BOOT_MODE_DEVELOPER) + && cse_bp_info.bp_info.current_bp == 0) { + if (!cse_boot_to_rw(&cse_bp_info.bp_info)) { + printk(BIOS_ERR, "cse_lite: Failed to switch to RW\n"); + *subcode = CSE_LITE_SKU_RW_SWITCH_ERROR; + goto failure; + } + } else if (boot_mode == VB2_BOOT_MODE_MANUAL_RECOVERY && + cse_bp_info.bp_info.current_bp == 1) { + if (!cse_boot_to_ro(&cse_bp_info.bp_info)){ + printk(BIOS_ERR, "cse_lite: Failed to switch to RO\n"); + *subcode = CSE_LITE_SKU_RW_SWITCH_ERROR; + goto failure; + } + } + + return 0; + +failure: + *rec_reason = VB2_RECOVERY_INTEL_CSE_LITE_SKU; + return 1; +} + void cse_fw_sync(void) { static struct get_bp_info_rsp cse_bp_info; -- To view, visit https://review.coreboot.org/c/coreboot/+/70015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d12fac7dd9f0555d28115275d60934beb85a5e7 Gerrit-Change-Number: 70015 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/{common, alderlake}: Add a config to support CSE sync in bo...
by Rizwan Qureshi (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik. Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70014 ) Change subject: soc/intel/{common, alderlake}: Add a config to support CSE sync in bootblock ...................................................................... soc/intel/{common, alderlake}: Add a config to support CSE sync in bootblock Add SOC_INTEL_CSE_LITE_SYNC_IN_BOOTBLOCK config to support CSE partition switching elarly in the boot flow. Compile reset.c in bootblock to resolve a dependency in cse_lite.c. Initialize HECI interface in bootblock if SOC_INTEL_CSE_LITE_SYNC_IN_BOOTBLOCK is set. TEST=Build and boot nirwen Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: I16646c4cca773daa60f6add0f9c7349eb1e4edaa --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/bootblock/pch.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc 4 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/70014/1 diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 7f808ff..67f7b7e 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -17,6 +17,7 @@ bootblock-y += espi.c bootblock-y += p2sb.c bootblock-$(CONFIG_ALDERLAKE_CONFIGURE_DESCRIPTOR) += bootblock/update_descriptor.c +bootblock-y += reset.c romstage-y += espi.c romstage-y += meminit.c diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index 712c128..f6966c0 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -9,6 +9,7 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> +#include <intelblocks/cse.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -127,4 +128,8 @@ pmc_gpe_init(); enable_rtc_upper_bank(); + + /* Initialize HECI interface */ + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_BOOTBLOCK)) + cse_init(HECI1_BASE_ADDRESS); } diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 55a2b49..4a98a20 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -173,6 +173,14 @@ Mainboard user to select this Kconfig in order to capture pre-cpu reset boot performance telemetry data. +config SOC_INTEL_CSE_LITE_SYNC_IN_BOOTBLOCK + bool + default y + depends on SOC_INTEL_CSE_LITE_SKU + help + Use this option to switch to the correct partition based on vboot boot mode early + in the boot flow. + config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE bool default y diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index d5ea933..f05c35e 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -1,6 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +bootblock-$(CONFIG_SOC_INTEL_CSE_LITE_SYNC_IN_BOOTBLOCK) += cse.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c +bootblock-$(CONFIG_SOC_INTEL_CSE_LITE_SYNC_IN_BOOTBLOCK) += cse_lite.c romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c -- To view, visit https://review.coreboot.org/c/coreboot/+/70014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16646c4cca773daa60f6add0f9c7349eb1e4edaa Gerrit-Change-Number: 70014 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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