coreboot-gerrit November 2022

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[L] Change in coreboot[master]: mb/intel/mtlrvp: Enable EC and building ChromeOS
by Harsha B R (Code Review) 26 Nov '22

26 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Wonkyu Kim, Harsha B R, Ravishankar Sarawadi, Paul Menzel, Kapil Porwal, Angel Pons, Nick Vaccaro, Tim Wawrzynczak, Raj Astekar. Harsha B R has uploaded a new patch set (#10) to the change originally created by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/66101 ) Change subject: mb/intel/mtlrvp: Enable EC and building ChromeOS ...................................................................... mb/intel/mtlrvp: Enable EC and building ChromeOS This configures and initializes EC, and adds building ChromeOS. BUG=b:224325352 TEST=FW_NAME=mtlrvp_p emerge-rex coreboot chromeos-bootimage Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: I662d7f79050d35e152d97dc5c2118a4af56223bc Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/Makefile.inc A src/mainboard/intel/mtlrvp/chromeos.c D src/mainboard/intel/mtlrvp/devicetree.cb M src/mainboard/intel/mtlrvp/dsdt.asl A src/mainboard/intel/mtlrvp/ec.c A src/mainboard/intel/mtlrvp/mainboard.c A src/mainboard/intel/mtlrvp/smihandler.c M src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h A src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/include/baseboard/ec.h M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/include/baseboard/gpio.h A src/mainboard/intel/mtlrvp/variants/mtlrvp_p/Makefile.inc A src/mainboard/intel/mtlrvp/variants/mtlrvp_p/devicetree.cb A src/mainboard/intel/mtlrvp/variants/mtlrvp_p/gpio.c A src/mainboard/intel/mtlrvp/variants/mtlrvp_p/include/variant/ec.h A src/mainboard/intel/mtlrvp/variants/mtlrvp_p/include/variant/gpio.h 16 files changed, 308 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/66101/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/66101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I662d7f79050d35e152d97dc5c2118a4af56223bc Gerrit-Change-Number: 66101 Gerrit-PatchSet: 10 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/meteorlake: Refactor heci finalize functions
by Subrata Banik (Code Review) 26 Nov '22

26 Nov '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69974 ) Change subject: soc/intel/meteorlake: Refactor heci finalize functions ...................................................................... soc/intel/meteorlake: Refactor heci finalize functions This patch creates a helper function `heci_finalize()` to keep HECI related operations separated for easy guarding again FSP config. Currently, `heci_set_to_d0i3()` function is getting called twice. BUG=b:260041679 TEST=Able to build google/rex with this patch and observe coreboot log modification as below: Without this patch: [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled [DEBUG] Finalizing chipset. [DEBUG] apm_control: Finalizing SMM. [DEBUG] APMC done. [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled [DEBUG] BS: BS_PAYLOAD_BOOT entry times (exec / console): 29 / 78 ms With this patch: [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled [DEBUG] Finalizing chipset. [DEBUG] apm_control: Finalizing SMM. [DEBUG] APMC done. [DEBUG] BS: BS_PAYLOAD_BOOT entry times (exec / console): 28 / 52 ms Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I7021a1d4c73d3fdfddfd6e809ebc1eeb1fa6d75e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69974 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> --- M src/soc/intel/meteorlake/finalize.c 1 file changed, 63 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Ivy Jian: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/finalize.c b/src/soc/intel/meteorlake/finalize.c index d3ae16a..f30a6ac 100644 --- a/src/soc/intel/meteorlake/finalize.c +++ b/src/soc/intel/meteorlake/finalize.c @@ -64,6 +64,13 @@ sa_lock_pam(); } +static void heci_finalize(void) +{ + heci_set_to_d0i3(); + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + heci1_disable(); +} + static void soc_finalize(void *unused) { printk(BIOS_DEBUG, "Finalizing chipset.\n"); @@ -72,9 +79,9 @@ apm_control(APM_CNT_FINALIZE); tbt_finalize(); sa_finalize(); - heci_set_to_d0i3(); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) - heci1_disable(); + if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) && + CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) + heci_finalize(); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); -- To view, visit https://review.coreboot.org/c/coreboot/+/69974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7021a1d4c73d3fdfddfd6e809ebc1eeb1fa6d75e Gerrit-Change-Number: 69974 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: Use common code CSE-Lite API for WP information
by Subrata Banik (Code Review) 26 Nov '22

26 Nov '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69969 ) Change subject: soc/intel/alderlake: Use common code CSE-Lite API for WP information ...................................................................... soc/intel/alderlake: Use common code CSE-Lite API for WP information This patch drops the local implementation `log_me_ro_write_protection_info` and adopts the API from IA common code (cse_lite.c). BUG=none TEST=Able to compile the cse_lite.c file for google/kano without any error. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I087ffb8ac94f14a6bd7f2bf6bb907c4047dc9899 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69969 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/alderlake/me.c 1 file changed, 23 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/alderlake/me.c b/src/soc/intel/alderlake/me.c index 4937ced..8b5e94f 100644 --- a/src/soc/intel/alderlake/me.c +++ b/src/soc/intel/alderlake/me.c @@ -2,7 +2,6 @@ #include <bootstate.h> #include <intelblocks/cse.h> -#include <intelblocks/spi.h> #include <console/console.h> #include <soc/me.h> #include <stdint.h> @@ -88,28 +87,6 @@ } __packed fields; }; -static void log_me_ro_write_protection_info(bool mfg_mode) -{ - bool cse_ro_wp_en = is_spi_wp_cse_ro_en(); - - printk(BIOS_DEBUG, "ME: WP for RO is enabled : %s\n", - cse_ro_wp_en ? "YES" : "NO"); - - if (cse_ro_wp_en) { - uint32_t base, limit; - spi_get_wp_cse_ro_range(&base, &limit); - printk(BIOS_DEBUG, "ME: RO write protection scope - Start=0x%X, End=0x%X\n", - base, limit); - } - - /* - * If manufacturing mode is disabled, but CSE RO is not write protected, - * log error. - */ - if (!mfg_mode && !cse_ro_wp_en) - printk(BIOS_ERR, "ME: Write protection for CSE RO is not enabled\n"); -} - static bool is_manuf_mode(union me_hfsts1 hfsts1, union me_hfsts6 hfsts6) { /* @@ -195,7 +172,7 @@ hfsts6.fields.txt_support ? "YES" : "NO"); if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) - log_me_ro_write_protection_info(manuf_mode); + cse_log_ro_write_protection_info(manuf_mode); } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/69969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I087ffb8ac94f14a6bd7f2bf6bb907c4047dc9899 Gerrit-Change-Number: 69969 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Create API to get CSE Lite WP Information
by Subrata Banik (Code Review) 26 Nov '22

26 Nov '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69968 ) Change subject: soc/intel/cmn/cse: Create API to get CSE Lite WP Information ...................................................................... soc/intel/cmn/cse: Create API to get CSE Lite WP Information This patch creates an API for CSE-Lite specific SKU to retrieve the Write Protect (WP) information (`cse_log_ro_write_protection_info`) like WP range and limit, if the region is write-protected or not etc. BUG=none TEST=Able to compile the cse_lite.c file for google/kano without any error. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I8f4b7880534ded5401b6f8d601ded88019c636c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69968 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 48 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index f051061..37640f4 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -10,6 +10,7 @@ #include <intelbasecode/debug_feature.h> #include <intelblocks/cse.h> #include <intelblocks/cse_layout.h> +#include <intelblocks/spi.h> #include <security/vboot/misc.h> #include <security/vboot/vboot_common.h> #include <soc/intel/common/reset.h> @@ -133,6 +134,28 @@ static const char * const cse_regions[] = {"RO", "RW"}; +void cse_log_ro_write_protection_info(bool mfg_mode) +{ + bool cse_ro_wp_en = is_spi_wp_cse_ro_en(); + + printk(BIOS_DEBUG, "ME: WP for RO is enabled : %s\n", + cse_ro_wp_en ? "YES" : "NO"); + + if (cse_ro_wp_en) { + uint32_t base, limit; + spi_get_wp_cse_ro_range(&base, &limit); + printk(BIOS_DEBUG, "ME: RO write protection scope - Start=0x%X, End=0x%X\n", + base, limit); + } + + /* + * If manufacturing mode is disabled, but CSE RO is not write protected, + * log error. + */ + if (!mfg_mode && !cse_ro_wp_en) + printk(BIOS_ERR, "ME: Write protection for CSE RO is not enabled\n"); +} + bool cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf_rsp) { struct cse_boot_perf_req { diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index f7aae1c..cceee4f 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -555,4 +555,7 @@ */ void cse_get_telemetry_data(void); +/* Function to log the cse WP information like range, if WP etc. */ +void cse_log_ro_write_protection_info(bool mfg_mode); + #endif // SOC_INTEL_COMMON_CSE_H -- To view, visit https://review.coreboot.org/c/coreboot/+/69968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f4b7880534ded5401b6f8d601ded88019c636c8 Gerrit-Change-Number: 69968 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: 3rdparty/libgfxinit: Update submodule pointer to 066e52eeaa32
by Felix Singer (Code Review) 26 Nov '22

26 Nov '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69945 ) Change subject: 3rdparty/libgfxinit: Update submodule pointer to 066e52eeaa32 ...................................................................... 3rdparty/libgfxinit: Update submodule pointer to 066e52eeaa32 Change-Id: I9b36a4b5f0a7a075ddef5d4bec984f3cd131626d Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69945 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M 3rdparty/libgfxinit 1 file changed, 14 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index 1b04c51..066e52e 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit 1b04c517b377468b3b470d38607fb539187391dd +Subproject commit 066e52eeaa329d782ccee96265a6a351fc395bf1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b36a4b5f0a7a075ddef5d4bec984f3cd131626d Gerrit-Change-Number: 69945 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: 3rdparty/libhwbase: Update submodule pointer to 8be5a82b85ce
by Felix Singer (Code Review) 26 Nov '22

26 Nov '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69944 ) Change subject: 3rdparty/libhwbase: Update submodule pointer to 8be5a82b85ce ...................................................................... 3rdparty/libhwbase: Update submodule pointer to 8be5a82b85ce Change-Id: I5ad61c39125b19922ae2fdda9767544d857139d0 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69944 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M 3rdparty/libhwbase 1 file changed, 14 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/3rdparty/libhwbase b/3rdparty/libhwbase index fc2102f..8be5a82 160000 --- a/3rdparty/libhwbase +++ b/3rdparty/libhwbase @@ -1 +1 @@ -Subproject commit fc2102f560f25e0f2e5be91ec36646dcb69e6e1b +Subproject commit 8be5a82b85ceb3ee8a1c4fbf36c75a4bfbda8900 -- To view, visit https://review.coreboot.org/c/coreboot/+/69944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ad61c39125b19922ae2fdda9767544d857139d0 Gerrit-Change-Number: 69944 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: 3rdparty/libhwbase: Update submodule pointer to 8be5a82b85ce
by Elyes Haouas (Code Review) 26 Nov '22

26 Nov '22

Attention is currently required from: Felix Singer, Nico Huber. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69944 ) Change subject: 3rdparty/libhwbase: Update submodule pointer to 8be5a82b85ce ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ad61c39125b19922ae2fdda9767544d857139d0 Gerrit-Change-Number: 69944 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sat, 26 Nov 2022 08:08:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: 3rdparty/libgfxinit: Update submodule pointer to 066e52eeaa32
by Elyes Haouas (Code Review) 26 Nov '22

26 Nov '22

Attention is currently required from: Felix Singer, Nico Huber. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69945 ) Change subject: 3rdparty/libgfxinit: Update submodule pointer to 066e52eeaa32 ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b36a4b5f0a7a075ddef5d4bec984f3cd131626d Gerrit-Change-Number: 69945 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sat, 26 Nov 2022 08:08:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/amd/mayan: Add framework for morgana crb mayan
by ritul guru (Code Review) 26 Nov '22

26 Nov '22

Attention is currently required from: Paul Menzel. ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70010 ) Change subject: mb/amd/mayan: Add framework for morgana crb mayan ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/70010/comment/83a77f9e_5dbe717a PS1, Line 9: mayan is the reference board for the morgana SoC. It needs to be : updated to match the actual board design as well. : amd/mayan is started as a copy of amd/birman. > Please remove the indentation, and reflow for 72 characters per line. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/70010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6801e6c6e706ae3878ce9e2c3d6452964235148 Gerrit-Change-Number: 70010 Gerrit-PatchSet: 3 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 26 Nov 2022 07:39:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add bootblock and early gpio for MTL-RVP
by Harsha B R (Code Review) 26 Nov '22

26 Nov '22

Attention is currently required from: Ashish Kumar Mishra, Haribalaraman Ramasubramanian, Rizwan Qureshi, Krishna P Bhat D, Balaji Manigandan, Eric Lai, Ronak Kanabar, Usha P. Hello build bot (Jenkins), Ashish Kumar Mishra, Haribalaraman Ramasubramanian, Rizwan Qureshi, Krishna P Bhat D, Balaji Manigandan, Eric Lai, Ronak Kanabar, Usha P, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69886 to look at the new patch set (#3). Change subject: mb/intel/mtlrvp: Add bootblock and early gpio for MTL-RVP ...................................................................... mb/intel/mtlrvp: Add bootblock and early gpio for MTL-RVP This adds an initial bootblock code. This also configures required GPIOs for early board initialization. 1. Add bootblock file for MTL-RVP 2. Add early gpio config for MTL-P variant in gpio.c BRANCH=none BUG=b:224325352 TEST=FW_NAME=mtlrvp_p emerge-rex coreboot chromeos-bootimage Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I9c0893e52036147c5f6bbfafc6d818e9d3460bed --- M src/mainboard/intel/mtlrvp/Makefile.inc A src/mainboard/intel/mtlrvp/bootblock.c M src/mainboard/intel/mtlrvp/variants/mtlrvp_p/Makefile.inc M src/mainboard/intel/mtlrvp/variants/mtlrvp_p/gpio.c 4 files changed, 118 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/69886/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c0893e52036147c5f6bbfafc6d818e9d3460bed Gerrit-Change-Number: 69886 Gerrit-PatchSet: 3 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2022