coreboot-gerrit November 2022

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[S] Change in coreboot[master]: ACPI: Flag boards with ACPI_NO_MADT
by Kyösti Mälkki (Code Review) 25 Nov '22

25 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69777 ) Change subject: ACPI: Flag boards with ACPI_NO_MADT ...................................................................... ACPI: Flag boards with ACPI_NO_MADT These boards do no fill MADT with useful information. Change-Id: Ie61e4e4b03c9b7fcd70aba7a2bd71eadd6f4dab1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69777 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/acpi/Kconfig M src/acpi/acpi.c M src/mainboard/asus/p2b/Kconfig D src/mainboard/asus/p2b/acpi_tables.c M src/soc/intel/quark/Kconfig M src/soc/intel/quark/acpi.c 6 files changed, 26 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Arthur Heymans: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index 7afff4e..816f9fb 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -30,6 +30,11 @@ Set to indicate <soc/nvs.h> exists for the platform with a definition for global_nvs. +config ACPI_NO_MADT + bool + help + Selected by platforms that don't expose a useful MADT. + config ACPI_NO_PCAT_8259 bool help diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index f6a36f8..c567299 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -282,7 +282,8 @@ if (CONFIG(ACPI_HAVE_PCAT_8259)) madt->flags |= 1; - current = acpi_fill_madt(current); + if (!CONFIG(ACPI_NO_MADT)) + current = acpi_fill_madt(current); /* (Re)calculate length and checksum. */ header->length = current - (unsigned long)madt; diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index 8e46fb9..986cfde 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ACPI_NO_MADT select CPU_INTEL_SLOT_1 select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB diff --git a/src/mainboard/asus/p2b/acpi_tables.c b/src/mainboard/asus/p2b/acpi_tables.c deleted file mode 100644 index b35610a..0000000 --- a/src/mainboard/asus/p2b/acpi_tables.c +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* mainboard has no ioapic */ - return current; -} diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 9783c1d..58f01da 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -9,6 +9,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y + select ACPI_NO_MADT select ARCH_X86 select NO_ECAM_MMCONF_SUPPORT select NO_SMM diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index 9e41b31..6a7f2c2 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -5,11 +5,6 @@ #include <soc/acpi.h> #include <soc/ramstage.h> -unsigned long acpi_fill_madt(unsigned long current) -{ - return current; -} - void acpi_fill_fadt(acpi_fadt_t *fadt) { struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC, -- To view, visit https://review.coreboot.org/c/coreboot/+/69777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie61e4e4b03c9b7fcd70aba7a2bd71eadd6f4dab1 Gerrit-Change-Number: 69777 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: cpu/intel/haswell: Move chip_ops to cpu cluster
by Felix Held (Code Review) 25 Nov '22

25 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59314 ) Change subject: cpu/intel/haswell: Move chip_ops to cpu cluster ...................................................................... cpu/intel/haswell: Move chip_ops to cpu cluster The cpu cluster is always present and it's the proper device to contain the settings that need to be applied to all cpus. This makes it possible to remove the fake lapic from devicetrees. Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59314 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/chip.h M src/cpu/intel/haswell/haswell_init.c M src/mainboard/asrock/b85m_pro4/devicetree.cb M src/mainboard/asrock/h81m-hds/devicetree.cb M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/google/slippy/devicetree.cb M src/mainboard/hp/folio_9480m/devicetree.cb M src/mainboard/intel/baskingridge/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb M src/mainboard/lenovo/haswell/variants/w541/devicetree.cb M src/mainboard/msi/h81m-p33/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/supermicro/x10slm-f/devicetree.cb M src/northbridge/intel/haswell/northbridge.c M src/soc/intel/broadwell/northbridge.c 21 files changed, 76 insertions(+), 138 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 1f028c3..a53978d 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -164,28 +164,22 @@ ARRAY_SIZE(tss_table_coarse), tss_table_coarse); } -static bool is_s0ix_enabled(void) +static bool is_s0ix_enabled(const struct device *dev) { if (!haswell_is_ult()) return false; - const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - - if (!lapic || !lapic->chip_info) - return false; - - const struct cpu_intel_haswell_config *conf = lapic->chip_info; - + const struct cpu_intel_haswell_config *conf = dev->chip_info; return conf->s0ix_enable; } -static void generate_C_state_entries(void) +static void generate_C_state_entries(const struct device *dev) { acpi_cstate_t acpi_cstate_map[3] = {0}; const int *acpi_cstates; - if (is_s0ix_enabled()) + if (is_s0ix_enabled(dev)) acpi_cstates = cstate_set_s0ix; else if (haswell_is_ult()) acpi_cstates = cstate_set_lp; @@ -352,7 +346,7 @@ coreID - 1, cores_per_package); /* Generate C-state tables */ - generate_C_state_entries(); + generate_C_state_entries(device); /* Generate T-state tables */ generate_T_state_entries( diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h index 776e239..5f2324c 100644 --- a/src/cpu/intel/haswell/chip.h +++ b/src/cpu/intel/haswell/chip.h @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Magic value used to locate this chip in the device tree */ -#define SPEEDSTEP_APIC_MAGIC 0xACAC - #include <stdbool.h> #include <stdint.h> diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 7b3f3ad..5a0b09d 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -172,18 +172,16 @@ return 0; } +static struct device *cpu_cluster; + static void initialize_vr_config(void) { struct cpu_vr_config vr_config = { 0 }; msr_t msr; - const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - - if (lapic && lapic->chip_info) { - const struct cpu_intel_haswell_config *conf = lapic->chip_info; - - vr_config = conf->vr_config; - } + /* Make sure your devicetree has the cpu_cluster below chip cpu/intel/haswell! */ + const struct cpu_intel_haswell_config *conf = cpu_cluster->chip_info; + vr_config = conf->vr_config; printk(BIOS_DEBUG, "Initializing VR config.\n"); @@ -448,18 +446,12 @@ wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } -static void configure_thermal_target(void) +static void configure_thermal_target(struct device *dev) { - struct cpu_intel_haswell_config *conf; - struct device *lapic; + /* Make sure your devicetree has the cpu_cluster below chip cpu/intel/haswell! */ + struct cpu_intel_haswell_config *conf = dev->bus->dev->chip_info; msr_t msr; - /* Find pointer to CPU configuration */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic || !lapic->chip_info) - return; - conf = lapic->chip_info; - /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); if ((msr.lo & (1 << 30)) && conf->tcc_offset) { @@ -551,7 +543,7 @@ configure_misc(); /* Thermal throttle activation offset */ - configure_thermal_target(); + configure_thermal_target(cpu); /* Enable Direct Cache Access */ configure_dca_cap(); @@ -638,6 +630,7 @@ void mp_init_cpus(struct bus *cpu_bus) { + cpu_cluster = cpu_bus->dev; /* TODO: Handle mp_init_with_smm failure? */ mp_init_with_smm(cpu_bus, &mp_ops); } diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index 7667392..e9a9876 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -3,12 +3,8 @@ # This mainboard has VGA register "gpu_ddi_e_connected" = "1" - device cpu_cluster 0 on - ops haswell_cpu_bus_ops - chip cpu/intel/haswell - device lapic 0 on end - device lapic 0xacac off end - end + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end end device domain 0 on diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index 144c247..d84c471 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -3,12 +3,8 @@ chip northbridge/intel/haswell register "gpu_ddi_e_connected" = "1" - device cpu_cluster 0 on - ops haswell_cpu_bus_ops - chip cpu/intel/haswell - device lapic 0 on end - device lapic 0xacac off end - end + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end end device domain 0 on diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 440efdf..2ded452 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -14,14 +14,10 @@ register "ec_present" = "true" - device cpu_cluster 0 on - ops broadwell_cpu_bus_ops - chip cpu/intel/haswell - register "s0ix_enable" = "1" + chip cpu/intel/haswell + device cpu_cluster 0 on ops broadwell_cpu_bus_ops end - device lapic 0 on end - device lapic 0xacac off end - end + register "s0ix_enable" = "1" end device domain 0 on diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 75bf8ee..be96e95 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -11,13 +11,10 @@ register "dq_pins_interleaved" = "true" - device cpu_cluster 0 on - chip cpu/intel/haswell - register "s0ix_enable" = "0" + chip cpu/intel/haswell + device cpu_cluster 0 on end - device lapic 0 on end - device lapic 0xacac off end - end + register "s0ix_enable" = "0" end device domain 0 on diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index cfb4812..3de469ec 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -12,19 +12,17 @@ .backlight_pwm_hz = 200, }" - device cpu_cluster 0 on - chip cpu/intel/haswell - # Disable S0ix for now - register "s0ix_enable" = "0" + chip cpu/intel/haswell + device cpu_cluster 0 on end - register "vr_config" = "{ - .slow_ramp_rate_set = 3, - .slow_ramp_rate_enable = true, - }" + # Disable S0ix for now + register "s0ix_enable" = "0" - device lapic 0 on end - device lapic 0xacac off end - end + register "vr_config" = "{ + .slow_ramp_rate_set = 3, + .slow_ramp_rate_enable = true, + }" + end device domain 0 on diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 9704cc3..18ec581 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -13,13 +13,8 @@ register "usb_xhci_on_resume" = "true" - device cpu_cluster 0 on - ops haswell_cpu_bus_ops - chip cpu/intel/haswell - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - end + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end end device domain 0 on diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index fe09566..59cf071 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -11,12 +11,8 @@ register "dq_pins_interleaved" = "true" - device cpu_cluster 0 on - ops broadwell_cpu_bus_ops - chip cpu/intel/haswell - device lapic 0 on end - device lapic 0xacac off end - end + chip cpu/intel/haswell + device cpu_cluster 0 on ops broadwell_cpu_bus_ops end end device domain 0 on diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index d09d7a1..0c1222c 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -15,13 +15,8 @@ register "usb_xhci_on_resume" = "true" - device cpu_cluster 0 on - ops haswell_cpu_bus_ops - chip cpu/intel/haswell - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - end + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end end device domain 0 on diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb index ee3209a..6a8e919 100644 --- a/src/mainboard/hp/folio_9480m/devicetree.cb +++ b/src/mainboard/hp/folio_9480m/devicetree.cb @@ -13,12 +13,8 @@ .backlight_pwm_hz = 200, }" register "usb_xhci_on_resume" = "true" - device cpu_cluster 0 on - ops haswell_cpu_bus_ops - chip cpu/intel/haswell - device lapic 0 on end - device lapic 0xacac off end - end + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end end device domain 0 on ops haswell_pci_domain_ops diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index d5b566d..3226170 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -11,13 +11,8 @@ # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - device cpu_cluster 0 on - ops haswell_cpu_bus_ops - chip cpu/intel/haswell - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - end + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end end device domain 0 on diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 0becbbf..3b3a975 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -9,12 +9,8 @@ # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - device cpu_cluster 0 on - ops broadwell_cpu_bus_ops - chip cpu/intel/haswell - device lapic 0 on end - device lapic 0xacac off end - end + chip cpu/intel/haswell + device cpu_cluster 0 on ops broadwell_cpu_bus_ops end end device domain 0 on ops broadwell_pci_domain_ops diff --git a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb index 85c484b..fc00734 100644 --- a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb +++ b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb @@ -13,12 +13,8 @@ .backlight_pwm_hz = 220, }" register "ec_present" = "true" - device cpu_cluster 0 on - ops haswell_cpu_bus_ops - chip cpu/intel/haswell - device lapic 0 on end - device lapic 0xacac off end - end + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end end device domain 0 on ops haswell_pci_domain_ops diff --git a/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb b/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb index ef4668c..292a30d 100644 --- a/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb +++ b/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb @@ -13,12 +13,8 @@ .backlight_pwm_hz = 220, }" register "ec_present" = "true" - device cpu_cluster 0 on - ops haswell_cpu_bus_ops - chip cpu/intel/haswell - device lapic 0 on end - device lapic 0xacac off end - end + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end end device domain 0 on ops haswell_pci_domain_ops diff --git a/src/mainboard/msi/h81m-p33/devicetree.cb b/src/mainboard/msi/h81m-p33/devicetree.cb index 429269c..f72ed9f 100644 --- a/src/mainboard/msi/h81m-p33/devicetree.cb +++ b/src/mainboard/msi/h81m-p33/devicetree.cb @@ -2,12 +2,8 @@ chip northbridge/intel/haswell register "gpu_ddi_e_connected" = "1" - device cpu_cluster 0 on - ops haswell_cpu_bus_ops - chip cpu/intel/haswell - device lapic 0 on end - device lapic 0xacac off end - end + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end end device domain 0 on ops haswell_pci_domain_ops diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index ae98c9e..45350b6 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -20,12 +20,8 @@ .backlight_pwm_hz = 200, }" - device cpu_cluster 0 on - ops broadwell_cpu_bus_ops - chip cpu/intel/haswell - device lapic 0 on end - device lapic 0xacac off end - end + chip cpu/intel/haswell + device cpu_cluster 0 on ops broadwell_cpu_bus_ops end end device domain 0 on ops broadwell_pci_domain_ops diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb index 959c3b8..8625daa 100644 --- a/src/mainboard/supermicro/x10slm-f/devicetree.cb +++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb @@ -2,12 +2,8 @@ chip northbridge/intel/haswell - device cpu_cluster 0 on - ops haswell_cpu_bus_ops - chip cpu/intel/haswell - device lapic 0 on end - device lapic 0xacac off end - end + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end end device domain 0 on diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index e11eb1c..bcb2a0b 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -536,7 +536,6 @@ .enable_resources = pci_dev_enable_resources, .init = northbridge_init, .final = northbridge_final, - .acpi_fill_ssdt = generate_cpu_entries, .ops_pci = &pci_dev_ops_pci, }; @@ -561,6 +560,7 @@ .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, + .acpi_fill_ssdt = generate_cpu_entries, }; struct chip_operations northbridge_intel_haswell_ops = { diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index bbde3d2..a01f7ec 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -398,7 +398,6 @@ static struct device_operations systemagent_ops = { .read_resources = systemagent_read_resources, - .acpi_fill_ssdt = generate_cpu_entries, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = systemagent_init, @@ -432,6 +431,7 @@ .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, + .acpi_fill_ssdt = generate_cpu_entries, }; static void broadwell_init_pre_device(void *chip_info) -- To view, visit https://review.coreboot.org/c/coreboot/+/59314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786 Gerrit-Change-Number: 59314 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: ACPI MADT: Add LINT1 as NMI source
by Kyösti Mälkki (Code Review) 25 Nov '22

25 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69528 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: ACPI MADT: Add LINT1 as NMI source ...................................................................... ACPI MADT: Add LINT1 as NMI source Set of boards and platforms did not have LINT1 configured as NMI source. Change-Id: I65044125562bda363b3a0d92da6137c77a28b587 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69528 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/aopen/dxplplusu/acpi_tables.c M src/mainboard/emulation/qemu-i440fx/acpi_tables.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/southbridge/intel/common/madt.c 5 files changed, 21 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c index 5f0d943..13ddb3e 100644 --- a/src/mainboard/aopen/dxplplusu/acpi_tables.c +++ b/src/mainboard/aopen/dxplplusu/acpi_tables.c @@ -8,7 +8,7 @@ struct device *bdev, *dev = NULL; struct resource *res = NULL; - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* Southbridge IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, 0xfec00000); diff --git a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c index 61771c7..e6262d1 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c +++ b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c @@ -11,7 +11,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 7589464..4406188 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -89,7 +89,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 1c9eb4e..46a8771 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -329,7 +329,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); diff --git a/src/southbridge/intel/common/madt.c b/src/southbridge/intel/common/madt.c index eb11c21..b85e110 100644 --- a/src/southbridge/intel/common/madt.c +++ b/src/southbridge/intel/common/madt.c @@ -7,7 +7,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); -- To view, visit https://review.coreboot.org/c/coreboot/+/69528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65044125562bda363b3a0d92da6137c77a28b587 Gerrit-Change-Number: 69528 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: ACPI: Use common code for MADT LAPIC NMIs
by Kyösti Mälkki (Code Review) 25 Nov '22

25 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69527 ) Change subject: ACPI: Use common code for MADT LAPIC NMIs ...................................................................... ACPI: Use common code for MADT LAPIC NMIs Use the broadcast ID to deliver LINT1 as NMI to all CPUs, instead of listing individual LAPIC IDs. Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69527 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/amd/cezanne/acpi.c M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/morgana/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/madt.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/madt.c 13 files changed, 49 insertions(+), 95 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 877c47e..f6a36f8 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -240,6 +240,24 @@ return lapic_nmi->length; } +unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current) +{ + const u16 flags = MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH; + + current = acpi_create_madt_lapics(current); + + /* 1: LINT1 connect to NMI */ + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, + ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, flags, 1); + + if (!CONFIG(XAPIC_ONLY)) + current += acpi_create_madt_lx2apic_nmi((acpi_madt_lx2apic_nmi_t *)current, + ACPI_MADT_LX2APIC_NMI_ALL_PROCESSORS, flags, 1); + + return current; +} + void acpi_create_madt(acpi_madt_t *madt) { acpi_header_t *header = &(madt->header); diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index fa216aa..57dbc65 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -678,7 +678,8 @@ u8 lint; /* Local APIC LINT# */ } __packed acpi_madt_lapic_nmi_t; -#define ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS 0xff +#define ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS 0xff +#define ACPI_MADT_LX2APIC_NMI_ALL_PROCESSORS ((u32)-1) /* MADT: I/O APIC Structure */ typedef struct acpi_madt_ioapic { @@ -1333,6 +1334,7 @@ u16 flags, u8 lint); void acpi_create_madt(acpi_madt_t *madt); unsigned long acpi_create_madt_lapics(unsigned long current); +unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current); int acpi_create_madt_lx2apic(acpi_madt_lx2apic_t *lapic, u32 cpu, u32 apic); int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, u16 flags, u8 lint); diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 189e84e..802476e 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -24,7 +24,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); @@ -41,12 +41,6 @@ MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); current = acpi_fill_madt_irqoverride(current); - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, - ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 1 /* 1: LINT1 connect to NMI */); - return current; } diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 85430b9..0c95494 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -27,7 +27,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); @@ -44,12 +44,6 @@ MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); current = acpi_fill_madt_irqoverride(current); - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, - ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 1 /* 1: LINT1 connect to NMI */); - return current; } diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index b867930..d30fb85 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -26,7 +26,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); @@ -43,12 +43,6 @@ MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); current = acpi_fill_madt_irqoverride(current); - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, - ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 1 /* 1: LINT1 connect to NMI */); - return current; } diff --git a/src/soc/amd/morgana/acpi.c b/src/soc/amd/morgana/acpi.c index 5eb21ff..15b64c5 100644 --- a/src/soc/amd/morgana/acpi.c +++ b/src/soc/amd/morgana/acpi.c @@ -27,7 +27,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); @@ -44,12 +44,6 @@ MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); current = acpi_fill_madt_irqoverride(current); - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, - ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 1 /* 1: LINT1 connect to NMI */); - return current; } diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 2af6459..6d46698 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -31,7 +31,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); @@ -49,12 +49,6 @@ current = acpi_fill_madt_irqoverride(current); - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, - ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 1 /* 1: LINT1 connect to NMI */); - return current; } diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 20221d2..cc0194b 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -26,7 +26,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* create all subtables for processors */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* Write Kern IOAPIC, only one */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); @@ -42,12 +42,6 @@ MP_BUS_ISA, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); - /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, - ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 1 /* 1: LINT1 connect to NMI */); - return current; } diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index c355c944..860c868 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -69,12 +69,6 @@ current += acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); - /* NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); - - if (is_x2apic_mode()) - current += acpi_create_madt_lx2apic_nmi((acpi_madt_lx2apic_nmi_t *)current, - 0xffffffff, 0x5, 1); return current; } @@ -91,7 +85,7 @@ size_t ioapic_entries; /* Local APICs */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ ioapic_table = soc_get_ioapic_info(&ioapic_entries); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 62ff757..f8a2dac8 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -352,20 +352,11 @@ unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); diff --git a/src/southbridge/intel/i82801ix/madt.c b/src/southbridge/intel/i82801ix/madt.c index 19d5d8c..009c9ea 100644 --- a/src/southbridge/intel/i82801ix/madt.c +++ b/src/southbridge/intel/i82801ix/madt.c @@ -7,20 +7,11 @@ unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 7dfc33f..39b662a 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -367,20 +367,11 @@ unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); diff --git a/src/southbridge/intel/ibexpeak/madt.c b/src/southbridge/intel/ibexpeak/madt.c index a1a28a1..26b1630 100644 --- a/src/southbridge/intel/ibexpeak/madt.c +++ b/src/southbridge/intel/ibexpeak/madt.c @@ -9,7 +9,7 @@ unsigned long acpi_fill_madt(unsigned long current) { /* Local APICs */ - current = acpi_create_madt_lapics(current); + current = acpi_create_madt_lapics_with_nmis(current); /* IOAPIC */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR); @@ -24,19 +24,5 @@ MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); - /* LAPIC_NMI */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 0, - MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 1, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 2, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, 3, MP_IRQ_POLARITY_HIGH | - MP_IRQ_TRIGGER_EDGE, 0x01); return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/69527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9 Gerrit-Change-Number: 69527 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: ACPI: Flag boards with ACPI_NO_MADT
by Felix Held (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: Lance Zhao, Tim Wawrzynczak, Kyösti Mälkki. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69777 ) Change subject: ACPI: Flag boards with ACPI_NO_MADT ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie61e4e4b03c9b7fcd70aba7a2bd71eadd6f4dab1 Gerrit-Change-Number: 69777 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 25 Nov 2022 14:24:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: ACPI: Use common code for MADT LAPIC NMIs
by Felix Held (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Matt DeVillier, Tim Wawrzynczak, Kyösti Mälkki, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69527 ) Change subject: ACPI: Use common code for MADT LAPIC NMIs ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9 Gerrit-Change-Number: 69527 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 25 Nov 2022 14:23:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: ACPI: Use common code for MADT LAPIC NMIs
by Felix Held (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: Lance Zhao, Jason Glenesk, Raul Rangel, Matt DeVillier, Tim Wawrzynczak, Kyösti Mälkki, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69527 ) Change subject: ACPI: Use common code for MADT LAPIC NMIs ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9 Gerrit-Change-Number: 69527 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 25 Nov 2022 14:21:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/amd/mayan: Add framework for morgana crb mayan
by Paul Menzel (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: ritul guru, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70010 ) Change subject: mb/amd/mayan: Add framework for morgana crb mayan ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/70010/comment/cdccdcf5_a46bb877 PS1, Line 9: mayan is the reference board for the morgana SoC. It needs to be : updated to match the actual board design as well. : amd/mayan is started as a copy of amd/birman. Please remove the indentation, and reflow for 72 characters per line. Please add a blank line between paragraphs, or do not break the line, just because a sentence ends. -- To view, visit https://review.coreboot.org/c/coreboot/+/70010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6801e6c6e706ae3878ce9e2c3d6452964235148 Gerrit-Change-Number: 70010 Gerrit-PatchSet: 1 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 25 Nov 2022 14:18:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: device/cpu_device.c: Zero initialize struct
by Kyösti Mälkki (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: Arthur Heymans. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69752 ) Change subject: device/cpu_device.c: Zero initialize struct ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c0d16b6a265bf9c7abcfdf2f18a43706ee03ea1 Gerrit-Change-Number: 69752 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 25 Nov 2022 14:14:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: nb/intel/sandybridge: Add a chipset devicetree
by Kyösti Mälkki (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: Arthur Heymans, Angel Pons, Evgeny Zinoviev, Alexander Couzens, Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56912 ) Change subject: nb/intel/sandybridge: Add a chipset devicetree ...................................................................... Patch Set 5: Code-Review+2 (3 comments) File src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/56912/comment/15345831_7d30f2a5 PS4, Line 7: register "tcc_offset" = "5" # TCC of 95C > Where did this go? Done File src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/56912/comment/0766b967_a31f58a7 PS5, Line 6: device lapic 0xacac off end I quess you need a device under chip/? Just remember to address these too before sconfig grammar removes keyword lapic. File src/mainboard/google/stout/devicetree.cb: https://review.coreboot.org/c/coreboot/+/56912/comment/cdff048f_6fe61c0b PS4, Line 28: register "tcc_offset" = "5" # TCC of 95C > ? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87 Gerrit-Change-Number: 56912 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 25 Nov 2022 14:13:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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