coreboot-gerrit November 2022

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[S] Change in coreboot[master]: intel/common/block/cse: Update input and return type for hmrfpo statu...
by Rizwan Qureshi (Code Review) 25 Nov '22

25 Nov '22

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70013 ) Change subject: intel/common/block/cse: Update input and return type for hmrfpo status API ...................................................................... intel/common/block/cse: Update input and return type for hmrfpo status API Update return type for hmrfpo status API to align with the rest of the APIs in the file. Also add an input variable to return the status TEST=Build and boot on nirwen Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: Id4bcec44430ab8e6efbd54fd69f582fc93a69e5d --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 32 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/70013/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index c2d4484..4ab8eca 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -820,7 +820,7 @@ * Sends HMRFPO Get Status command to CSE to get the HMRFPO status. * The status can be DISABLED/LOCKED/ENABLED */ -int cse_hmrfpo_get_status(void) +int cse_hmrfpo_get_status(uint8_t *hmrfpo_status) { struct hmrfpo_get_status_msg { struct mkhi_hdr hdr; @@ -841,26 +841,28 @@ struct hmrfpo_get_status_resp resp; size_t resp_size = sizeof(struct hmrfpo_get_status_resp); - printk(BIOS_INFO, "HECI: Sending Get HMRFPO Status Command\n"); + printk(BIOS_INFO, "HECI: Send HMRFPO Status Command\n"); if (!cse_is_hfs1_cws_normal()) { printk(BIOS_ERR, "HECI: CSE's current working state is not Normal\n"); - return -1; + return 0; } if (heci_send_receive(&msg, sizeof(struct hmrfpo_get_status_msg), &resp, &resp_size, HECI_MKHI_ADDR)) { printk(BIOS_ERR, "HECI: HMRFPO send/receive fail\n"); - return -1; + return 0; } if (resp.hdr.result) { printk(BIOS_ERR, "HECI: HMRFPO Resp Failed:%d\n", resp.hdr.result); - return -1; + return 0; } - return resp.status; + *hmrfpo_status = resp.status; + + return 1; } void print_me_fw_version(void *unused) diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index f7aae1c..02141fb 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -27,6 +27,11 @@ #define MKHI_HMRFPO_ENABLE 0x1 #define MKHI_HMRFPO_GET_STATUS 0x3 +#define HMRFPO_STATUS_DISABLED 0x0 +#define HMRFPO_STATUS_LOCKED 0x1 +#define HMRFPO_STATUS_ENABLED 0x2 + + /* Get Firmware Version Command Id */ #define MKHI_GEN_GET_FW_VERSION 0x2 @@ -409,10 +414,11 @@ /* * Send HMRFPO_GET_STATUS command. - * returns -1 on failure and 0 (DISABLED)/ 1 (LOCKED)/ 2 (ENABLED) - * on success. + * returns 0 on failure and 1 on success. + * hmrfpo_status is updated with 0 (DISABLED)/ 1 (LOCKED)/ 2 (ENABLED) + * */ -int cse_hmrfpo_get_status(void); +int cse_hmrfpo_get_status(uint8_t *hmrfpo_status); /* Fixed Address MEI Header's Host Address field value */ #define BIOS_HOST_ADDR 0x00 -- To view, visit https://review.coreboot.org/c/coreboot/+/70013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4bcec44430ab8e6efbd54fd69f582fc93a69e5d Gerrit-Change-Number: 70013 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: src/security/vboot: Add platform hook for vboot phase 1
by Rizwan Qureshi (Code Review) 25 Nov '22

25 Nov '22

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70012 ) Change subject: src/security/vboot: Add platform hook for vboot phase 1 ...................................................................... src/security/vboot: Add platform hook for vboot phase 1 Add a hook so that platform or soc code can be called to take actions after phase 1 has determined the boot mode. TEST=build and boot nirwen Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: Ic4f5347d1af02650a6ee0b261050556d95be21cb --- M src/security/vboot/vboot_common.h M src/security/vboot/vboot_logic.c 2 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/70012/1 diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 2399bf3..490fde2 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -55,6 +55,15 @@ void verstage_mainboard_early_init(void); void verstage_mainboard_init(void); +/* + * Hook for SoC/Platformn to perform operations after phase 1. Returns 0 on success, + * < 0 on error. + * On error the recovery reason and sub-code should also be set appropriately. + * + */ +int vboot_platform_hook_phase1(struct vb2_context *ctx, enum vb2_nv_recovery *rec_reason, + uint8_t *subcode); + /* Check boot modes */ #if CONFIG(VBOOT) && !ENV_SMM int vboot_developer_mode_enabled(void); diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 98a044c..4bb46e7 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -237,6 +237,9 @@ void verstage_main(void) { struct vb2_context *ctx; + enum vb2_nv_recovery plat_rec_reason = VB2_RECOVERY_NOT_REQUESTED; + uint8_t plat_rec_subcode = 0; + vb2_error_t rv; timestamp_add_now(TS_VBOOT_START); @@ -320,6 +323,14 @@ vboot_save_and_reboot(ctx, rv); } + /* Check for trusted boot and make sure SoC firmware is also booting in the right mode */ + if(vboot_platform_hook_phase1(ctx, &plat_rec_reason, &plat_rec_subcode)) { + printk(BIOS_INFO, "Platform hook after Phase 1 Failed\n"); + vb2api_fail(ctx, plat_rec_reason, plat_rec_subcode); + vboot_save_data(ctx); + vboot_reboot(); + } + /* Determine which firmware slot to boot (based on NVRAM) */ printk(BIOS_INFO, "Phase 2\n"); rv = vb2api_fw_phase2(ctx); @@ -391,3 +402,10 @@ verstage_main_exit: timestamp_add_now(TS_VBOOT_END); } + +__weak int vboot_platform_hook_phase1(struct vb2_context *ctx, enum vb2_nv_recovery *rec_reason, + uint8_t *subcode) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/70012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4f5347d1af02650a6ee0b261050556d95be21cb Gerrit-Change-Number: 70012 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: nb/intel/sandybridge: Add a chipset devicetree
by Arthur Heymans (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: Arthur Heymans, Angel Pons, Evgeny Zinoviev, Alexander Couzens, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56912 ) Change subject: nb/intel/sandybridge: Add a chipset devicetree ...................................................................... Patch Set 5: (1 comment) File src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/56912/comment/90c13466_39bf0ba2 PS5, Line 6: device lapic 0xacac off end > I quess you need a device under chip/? Just remember to address these too before sconfig grammar removes keyword lapic. CB:59316 does that. -- To view, visit https://review.coreboot.org/c/coreboot/+/56912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87 Gerrit-Change-Number: 56912 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 25 Nov 2022 16:45:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/xivu: Update DPTF parameters
by Felix Held (Code Review) 25 Nov '22

25 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69960 ) Change subject: mb/google/nissa/var/xivu: Update DPTF parameters ...................................................................... mb/google/nissa/var/xivu: Update DPTF parameters Follow thermal table from thermal team. 1. Modify TS1 passive policy to 68. BUG=b:249446156 TEST=emerge-nissa coreboot chromeos-bootimage Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: I8539a29cab4863034a2b64d38aef4b772473246d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69960 Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/xivu/overridetree.cb 1 file changed, 23 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved Dtrain Hsu: Looks good to me, approved Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb index 0c8ed39..ac23c68 100644 --- a/src/mainboard/google/brya/variants/xivu/overridetree.cb +++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb @@ -107,7 +107,7 @@ register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 77, 5000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 68, 5000), [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 78, 5000), }" -- To view, visit https://review.coreboot.org/c/coreboot/+/69960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8539a29cab4863034a2b64d38aef4b772473246d Gerrit-Change-Number: 69960 Gerrit-PatchSet: 3 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/cezanne: Update XHCI GPE to use constant
by Matt DeVillier (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69917 ) Change subject: soc/amd/cezanne: Update XHCI GPE to use constant ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c2a44f7d2eb47422ae8c585e5e01ea0b420d461 Gerrit-Change-Number: 69917 Gerrit-PatchSet: 3 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 25 Nov 2022 16:28:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: util/amdfwtool: Deal with psp position in flash offset directly
by Matt DeVillier (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Jason Nien, Arthur Heymans, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69852 ) Change subject: util/amdfwtool: Deal with psp position in flash offset directly ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/Makefile.inc: https://review.coreboot.org/c/coreboot/+/69852/comment/6b6d22d6_a206318c PS4, Line 25: $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 1 $(CONFIG_AMD_FWM_POSITION)) > > Earlier the position was in memory map 0xffc20000 and the SPI ROM was in the memory map range [0xf […] would it make sense to add flash offset support to cbfstool? It already knows the flash size from the FMAP, right? -- To view, visit https://review.coreboot.org/c/coreboot/+/69852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89c9e73e7db748379c97e3c0ad69af3faedc8d66 Gerrit-Change-Number: 69852 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 25 Nov 2022 16:26:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Disable GSPI2 controller
by Werner Zeh (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: Paul Menzel, Mario Scheithauer, Felix Held. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69972 ) Change subject: mb/siemens/mc_ehl2: Disable GSPI2 controller ...................................................................... Patch Set 2: (1 comment) File src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb: https://review.coreboot.org/c/coreboot/+/69972/comment/886b1795_e7c035a6 PS2, Line 145: device pci 12.0 on end # GSPI2 > looks like elkhartlake doesn't have a chipset devicetree that disables all non-essential devices by […] It is basically this way: There is a FSP parameter array to let FSP enable or disable the three GSPI controllers. This parameter is processed before PCI enumerator is executed. A 0 in this parameter is equal to disable and because the devicetree does not utilize this parameters, they will be 0 per default. Therefore, FSP-S disable the PCI devices and coreboot can not just enable them. To have a device enabled, in addition the corresponding FSP parameter needs to be set accordingly (via devicetree parameter). So in other words: This device is not needed, it stayed in the devicetree as a 'left-over' from porting (from Intel's CRB) and we would like to remove it. -- To view, visit https://review.coreboot.org/c/coreboot/+/69972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e7462312953d50385ca7bb2f2e0abb8fc3a5886 Gerrit-Change-Number: 69972 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 25 Nov 2022 15:58:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Disable GSPI2 controller
by Felix Held (Code Review) 25 Nov '22

25 Nov '22

Attention is currently required from: Paul Menzel, Mario Scheithauer. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69972 ) Change subject: mb/siemens/mc_ehl2: Disable GSPI2 controller ...................................................................... Patch Set 2: (1 comment) File src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb: https://review.coreboot.org/c/coreboot/+/69972/comment/61d23e5d_523b7778 PS2, Line 145: device pci 12.0 on end # GSPI2 > Why is setting it to `off` not enough, so it’s clear it could theoretically be enabled? looks like elkhartlake doesn't have a chipset devicetree that disables all non-essential devices by default. when coreboot complains that there's a leftover static device that means that the device wasn't discovered when scanning the bus, right? -- To view, visit https://review.coreboot.org/c/coreboot/+/69972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e7462312953d50385ca7bb2f2e0abb8fc3a5886 Gerrit-Change-Number: 69972 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Fri, 25 Nov 2022 15:51:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Disable L1 prefetcher
by Felix Held (Code Review) 25 Nov '22

25 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69966 ) Change subject: mb/siemens/mc_ehl2: Disable L1 prefetcher ...................................................................... mb/siemens/mc_ehl2: Disable L1 prefetcher As for mainboard mc_ehl1, a hard real-time dependency is also required for this mainboard. The L1 prefetcher on Elkhart Lake is too aggressive which in the end leads to an increased number of cache misses. Disabling the L1 prefetcher boosts up the performance (in some cases by more than 10 %) in this specific use case. Change-Id: I07b27dd672533e693a6c2987d16f54333850760e Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69966 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index e1c2972..74d0f26 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -135,6 +135,9 @@ .vcc_low_high_us = 50, }" + # Disable L1 prefetcher for real-time demands + register "L1_prefetcher_disable" = "true" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device -- To view, visit https://review.coreboot.org/c/coreboot/+/69966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07b27dd672533e693a6c2987d16f54333850760e Gerrit-Change-Number: 69966 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: cpu/intel/model_2065x: Don't use a magic APIC
by Felix Held (Code Review) 25 Nov '22

25 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59315 ) Change subject: cpu/intel/model_2065x: Don't use a magic APIC ...................................................................... cpu/intel/model_2065x: Don't use a magic APIC Move the chip configuration to the cpu cluster device. It looks like none of the devicetree were featuring a lapic 0xacac, nor was tcc_offset ever set, so this remains a NOP. Change-Id: I296631511b0e31b0ed43ca8193552483bdab4482 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59315 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/model_2065x/chip.h M src/cpu/intel/model_2065x/model_2065x_init.c M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/x201/devicetree.cb M src/mainboard/packardbell/ms2290/devicetree.cb 5 files changed, 28 insertions(+), 28 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/cpu/intel/model_2065x/chip.h b/src/cpu/intel/model_2065x/chip.h index 4ee91f6..9e89793 100644 --- a/src/cpu/intel/model_2065x/chip.h +++ b/src/cpu/intel/model_2065x/chip.h @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Magic value used to locate this chip in the device tree */ -#define SPEEDSTEP_APIC_MAGIC 0xACAC - struct cpu_intel_model_2065x_config { int tcc_offset; /* TCC Activation Offset */ }; diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index fc86040..389989c 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -20,18 +20,11 @@ #include <smp/node.h> #include <types.h> -static void configure_thermal_target(void) +static void configure_thermal_target(struct device *dev) { - struct cpu_intel_model_2065x_config *conf; - struct device *lapic; + struct cpu_intel_model_2065x_config *conf = dev->bus->dev->chip_info; msr_t msr; - /* Find pointer to CPU configuration */ - lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); - if (!lapic || !lapic->chip_info) - return; - conf = lapic->chip_info; - /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); if ((msr.lo & (1 << 30)) && conf->tcc_offset) { @@ -101,7 +94,7 @@ configure_misc(); /* Thermal throttle activation offset */ - configure_thermal_target(); + configure_thermal_target(cpu); /* Set Max Ratio */ set_max_ratio(); diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 4631b8e..200cabb 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -17,11 +17,8 @@ register "gpu_cpu_backlight" = "0x58d" register "gpu_pch_backlight" = "0x061a061a" - device cpu_cluster 0 on - ops ironlake_cpu_bus_ops - chip cpu/intel/model_2065x - device lapic 0 on end - end + chip cpu/intel/model_2065x + device cpu_cluster 0 on ops ironlake_cpu_bus_ops end end device domain 0 on diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 73b0437..fc7c470 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -18,11 +18,8 @@ register "gpu_cpu_backlight" = "0x58d" register "gpu_pch_backlight" = "0x061a061a" - device cpu_cluster 0 on - ops ironlake_cpu_bus_ops - chip cpu/intel/model_2065x - device lapic 0 on end - end + chip cpu/intel/model_2065x + device cpu_cluster 0 on ops ironlake_cpu_bus_ops end end device domain 0 on diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index b49f4d5..db0725b 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -18,11 +18,8 @@ register "gpu_cpu_backlight" = "0x58d" register "gpu_pch_backlight" = "0x061a061a" - device cpu_cluster 0 on - ops ironlake_cpu_bus_ops - chip cpu/intel/model_2065x - device lapic 0 on end - end + chip cpu/intel/model_2065x + device cpu_cluster 0 on ops ironlake_cpu_bus_ops end end device domain 0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/59315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I296631511b0e31b0ed43ca8193552483bdab4482 Gerrit-Change-Number: 59315 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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