coreboot-gerrit November 2022

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[L] Change in coreboot[master]: security/tpm/: turn tis_{init,open} into tis_probe
by Sergii Dmytruk (Code Review) 27 Nov '22

27 Nov '22

Attention is currently required from: Michał Żygowski, Christian Walter, Julius Werner, Krystian Hebel, Sergii Dmytruk. Hello build bot (Jenkins), Michał Żygowski, Christian Walter, Julius Werner, Krystian Hebel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68991 to look at the new patch set (#3). Change subject: security/tpm/: turn tis_{init,open} into tis_probe ...................................................................... security/tpm/: turn tis_{init,open} into tis_probe Init was always followed by open and after successful initialization we need only send-receive function, which is now returned by tis_probe on success further reducing number of functions to export from drivers. Change-Id: Ib4ce35ada24e3959ea1a518c29d431b4ae123809 Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/drivers/crb/tis.c M src/drivers/i2c/tpm/cr50.c M src/drivers/i2c/tpm/tis.c M src/drivers/i2c/tpm/tis_atmel.c M src/drivers/i2c/tpm/tpm.c M src/drivers/i2c/tpm/tpm.h M src/drivers/pc80/tpm/tis.c M src/drivers/spi/tpm/tis.c M src/security/tpm/tis.h M src/security/tpm/tss/tcg-1.2/tss.c M src/security/tpm/tss/tcg-2.0/tss.c 11 files changed, 139 insertions(+), 180 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/68991/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4ce35ada24e3959ea1a518c29d431b4ae123809 Gerrit-Change-Number: 68991 Gerrit-PatchSet: 3 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel: Improve TCO accessors
by Elyes Haouas (Code Review) 27 Nov '22

27 Nov '22

Attention is currently required from: Tarun Tuli, Sean Rhodes, Subrata Banik, Kapil Porwal, Lean Sheng Tan, Kyösti Mälkki, Werner Zeh. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70052 ) Change subject: soc/intel: Improve TCO accessors ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0090585bf6f30482952af40a985b086cf7bd91e6 Gerrit-Change-Number: 70052 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Sun, 27 Nov 2022 16:44:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/crossgcc: Use GitHub for downloading IASL
by Elyes Haouas (Code Review) 27 Nov '22

27 Nov '22

Attention is currently required from: Felix Singer. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70021 ) Change subject: util/crossgcc: Use GitHub for downloading IASL ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/70021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b10dd1db4299aaef96bc29023bed874b660aba0 Gerrit-Change-Number: 70021 Gerrit-PatchSet: 9 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Sun, 27 Nov 2022 16:41:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/crossgcc: Use GitHub for downloading IASL
by Felix Singer (Code Review) 27 Nov '22

27 Nov '22

Attention is currently required from: Felix Singer, Elyes Haouas. Hello build bot (Jenkins), Angel Pons, Elyes Haouas, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70021 to look at the new patch set (#8). Change subject: util/crossgcc: Use GitHub for downloading IASL ...................................................................... util/crossgcc: Use GitHub for downloading IASL The download links from acpica.org [1] are not stable, and for some reason they named the release tarballs with .tar_0.gz. Thus, use the tarballs from their GitHub repository generated out of the release tags [2]. Tested locally and also IASL patch applies. [1] https://www.acpica.org/downloads [2] https://github.com/acpica/acpica/tags Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I7b10dd1db4299aaef96bc29023bed874b660aba0 --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-R10_20_22_iasl.patch A util/crossgcc/sum/R10_20_22.tar.gz.cksum D util/crossgcc/sum/acpica-unix2-20221020.tar.gz.cksum 4 files changed, 24 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/70021/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/70021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b10dd1db4299aaef96bc29023bed874b660aba0 Gerrit-Change-Number: 70021 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: [NOTFORMERGE] aopen,smm,i82801,e7505,lapic-nmi
by Kyösti Mälkki (Code Review) 27 Nov '22

27 Nov '22

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/69759 ) Change subject: [NOTFORMERGE] aopen,smm,i82801,e7505,lapic-nmi ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/69759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecfea92c032e89dff73d1258e031e9dc0b3ebeec Gerrit-Change-Number: 69759 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: soc/intel: Improve TCO accessors
by Kyösti Mälkki (Code Review) 27 Nov '22

27 Nov '22

Attention is currently required from: Tarun Tuli, Sean Rhodes, Subrata Banik, Kapil Porwal, Lean Sheng Tan, Werner Zeh. Hello Tarun Tuli, Sean Rhodes, Subrata Banik, Kapil Porwal, Lean Sheng Tan, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70052 to look at the new patch set (#3). Change subject: soc/intel: Improve TCO accessors ...................................................................... soc/intel: Improve TCO accessors Renames tco_read_reg() to tco_read16(). Renames tco_write_reg() to tco_write16(). Implement bitwise operations using <arch/io_bitops.h>. Change-Id: I0090585bf6f30482952af40a985b086cf7bd91e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/include/intelblocks/tco.h M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/elkhartlake/bootblock/bootblock.c M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/pmutil.c 12 files changed, 77 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/70052/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/70052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0090585bf6f30482952af40a985b086cf7bd91e6 Gerrit-Change-Number: 70052 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel: Improve TCO accessors
by Kyösti Mälkki (Code Review) 27 Nov '22

27 Nov '22

Attention is currently required from: Tarun Tuli, Sean Rhodes, Subrata Banik, Kapil Porwal, Lean Sheng Tan, Werner Zeh. Hello Tarun Tuli, Sean Rhodes, Subrata Banik, Kapil Porwal, Lean Sheng Tan, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70052 to look at the new patch set (#2). Change subject: soc/intel: Improve TCO accessors ...................................................................... soc/intel: Improve TCO accessors Renames tco_read_reg() to tco_read16(). Renames tco_write_reg() to tco_write16(). Implement bitwise operations using <arch/io_bitops.h>. Change-Id: I0090585bf6f30482952af40a985b086cf7bd91e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M 3rdparty/arm-trusted-firmware M 3rdparty/libgfxinit M 3rdparty/libhwbase M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/include/intelblocks/tco.h M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/elkhartlake/bootblock/bootblock.c M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/pmutil.c 15 files changed, 80 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/70052/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0090585bf6f30482952af40a985b086cf7bd91e6 Gerrit-Change-Number: 70052 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG
by Kyösti Mälkki (Code Review) 27 Nov '22

27 Nov '22

Attention is currently required from: Angel Pons, Patrick Rudolph, Elyes Haouas. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61517 ) Change subject: aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG ...................................................................... Patch Set 8: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61517/comment/09655ff9_e8aedb5c PS7, Line 13: > > 'occuring' may be misspelled - perhaps 'occurring'? […] Done File src/northbridge/intel/e7505/Kconfig: https://review.coreboot.org/c/coreboot/+/61517/comment/484839cf_75e6ae4c PS7, Line 13: #select SMM_ASEG > Should this be selectable? Removed. File src/northbridge/intel/e7505/memmap.c: https://review.coreboot.org/c/coreboot/+/61517/comment/e4ea927d_a7d97a49 PS7, Line 42: return 512 *KiB; > > need consistent spacing around '*' (ctx:WxV) […] Done https://review.coreboot.org/c/coreboot/+/61517/comment/34a169f8_c94c7f0f PS7, Line 54: tolm -= northbridge_get_tseg_size(); > Since most other places also use TSEG size, would it be a good idea to have a function that returns […] If you think of a nicer way, there is about 10 variations under nb/intel to convert. -- To view, visit https://review.coreboot.org/c/coreboot/+/61517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7 Gerrit-Change-Number: 61517 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 27 Nov 2022 13:08:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG
by Kyösti Mälkki (Code Review) 27 Nov '22

27 Nov '22

Attention is currently required from: Kyösti Mälkki, Patrick Rudolph, Elyes Haouas. Hello build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61517 to look at the new patch set (#8). Change subject: aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG ...................................................................... aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG Both SMM_ASEG and SMM_TSEG choices work. There is periodic TCO timeout occurring. At least with DEBUG_SMI kernel reports low memory corruption. Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f2x/model_f2x_init.c A src/cpu/intel/model_f2x/mp_init.c M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/e7505/e7505.h M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/e7505/raminit.c M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c A src/southbridge/intel/i82801dx/smihandler.c 15 files changed, 255 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/61517/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/61517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7 Gerrit-Change-Number: 61517 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel: Improve TCO accessors
by Kyösti Mälkki (Code Review) 27 Nov '22

27 Nov '22

Attention is currently required from: Tarun Tuli, Sean Rhodes, Subrata Banik, Kapil Porwal, Lean Sheng Tan, Werner Zeh. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70052 ) Change subject: soc/intel: Improve TCO accessors ...................................................................... soc/intel: Improve TCO accessors Renames tco_read_reg() to tco_read16(). Renames tco_write_reg() to tco_write16(). Implement bitwise operations using <arch/io_bitops.h>. Change-Id: I0090585bf6f30482952af40a985b086cf7bd91e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/include/intelblocks/tco.h M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/elkhartlake/bootblock/bootblock.c M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/pmutil.c 12 files changed, 75 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/70052/1 diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c index 300ac71..80391ac 100644 --- a/src/soc/intel/alderlake/pmutil.c +++ b/src/soc/intel/alderlake/pmutil.c @@ -229,8 +229,8 @@ { uint8_t *pmc; - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS); printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 1f641de..5c6622c 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -154,8 +154,8 @@ { uintptr_t pmc_bar0 = soc_read_pmc_base(); - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS); ps->prsts = read32((void *)(pmc_bar0 + PRSTS)); ps->gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1)); diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 2219f65..6f471ec 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -222,8 +222,8 @@ { uint8_t *pmc; - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS); printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); diff --git a/src/soc/intel/common/block/include/intelblocks/tco.h b/src/soc/intel/common/block/include/intelblocks/tco.h index 35cbfb1..2012818 100644 --- a/src/soc/intel/common/block/include/intelblocks/tco.h +++ b/src/soc/intel/common/block/include/intelblocks/tco.h @@ -17,7 +17,7 @@ * and returns the status bits set. */ uint32_t tco_reset_status(void); -uint16_t tco_read_reg(uint16_t tco_reg); -void tco_write_reg(uint16_t tco_reg, uint16_t value); +uint16_t tco_read16(uint16_t tco_reg); +void tco_write16(uint16_t tco_reg, uint16_t value); #endif /* SOC_INTEL_COMMON_BLOCK_TCO_H */ diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 12b176c..f678a53 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -29,36 +29,45 @@ return TCO_BASE_ADDRESS; } -uint16_t tco_read_reg(uint16_t tco_reg) +uint16_t tco_read16(uint16_t tco_reg) { - uint16_t tcobase; - - tcobase = tco_get_bar(); - - return inw(tcobase + tco_reg); + return io_read16(tco_get_bar() + tco_reg); } -void tco_write_reg(uint16_t tco_reg, uint16_t value) +void tco_write16(uint16_t tco_reg, uint16_t value) { - uint16_t tcobase; + io_write16(tco_get_bar() + tco_reg, value); +} - tcobase = tco_get_bar(); +uint16_t tco_rwc16(uint16_t tco_reg) +{ + return io_rwc16(tco_get_bar() + tco_reg); +} - outw(value, tcobase + tco_reg); +void tco_setbits16(uint16_t tco_reg, uint16_t mask) +{ + io_setbits16(tco_get_bar() + tco_reg, mask); +} + +void tco_clrbits16(uint16_t tco_reg, uint16_t mask) +{ + io_clrbits16(tco_get_bar() + tco_reg, mask); +} + +void tco_clrsetbits16(uint16_t tco_reg, uint16_t clr, uint16_t set) +{ + io_clrsetbits16(tco_get_bar() + tco_reg, clr, set); } void tco_lockdown(void) { - uint16_t tcocnt; const pci_devfn_t dev = PCH_DEV_SMBUS; /* TCO base address lockdown */ pci_or_config32(dev, TCOCTL, TCO_BASE_LOCK); /* TCO Lock down */ - tcocnt = tco_read_reg(TCO1_CNT); - tcocnt |= TCO_LOCK; - tco_write_reg(TCO1_CNT, tcocnt); + tco_setbits16(TCO1_CNT, TCO_LOCK); } uint32_t tco_reset_status(void) @@ -67,12 +76,12 @@ uint16_t tco2_sts; /* TCO Status 1 register */ - tco1_sts = tco_read_reg(TCO1_STS); - tco_write_reg(TCO1_STS, tco1_sts); + tco1_sts = tco_rwc16(TCO1_STS); + /* First clear only TCO_STS_SECOND_TO here ?? */ /* TCO Status 2 register */ - tco2_sts = tco_read_reg(TCO2_STS); - tco_write_reg(TCO2_STS, tco2_sts | TCO2_STS_SECOND_TO); + tco2_sts = tco_read16(TCO2_STS); + tco_write16(TCO2_STS, tco2_sts | TCO2_STS_SECOND_TO); return (tco2_sts << 16) | tco1_sts; } @@ -80,24 +89,23 @@ /* Stop TCO timer */ static void tco_timer_disable(void) { - uint16_t tcocnt; + tco_setbits16(TCO1_CNT, TCO_TMR_HLT); +} - /* Program TCO timer halt */ - tcocnt = tco_read_reg(TCO1_CNT); - tcocnt |= TCO_TMR_HLT; - tco_write_reg(TCO1_CNT, tcocnt); +/* NO_REBOOT is enabled via bit 0 in TCO1_CNT. */ +#define TCO_NO_REBOOT (1 << 0) + +void tco_set_no_reboot(void) +{ + printk(BIOS_DEBUG, "TCO: Disable reset on second expiration.\n"); + tco_setbits16(TCO1_CNT, TCO_NO_REBOOT); } /* Enable and initialize TCO intruder SMI */ static void tco_intruder_smi_enable(void) { - uint16_t tcocnt; - /* Make TCO issue an SMI on INTRD_DET assertion */ - tcocnt = tco_read_reg(TCO2_CNT); - tcocnt &= ~TCO_INTRD_SEL_MASK; - tcocnt |= TCO_INTRD_SEL_SMI; - tco_write_reg(TCO2_CNT, tcocnt); + tco_clrsetbits16(TCO2_CNT, TCO_INTRD_SEL_MASK, TCO_INTRD_SEL_SMI); } /* Enable TCO BAR using SMBUS TCO base to access TCO related register */ diff --git a/src/soc/intel/elkhartlake/bootblock/bootblock.c b/src/soc/intel/elkhartlake/bootblock/bootblock.c index cc0bb8f..f96e678 100644 --- a/src/soc/intel/elkhartlake/bootblock/bootblock.c +++ b/src/soc/intel/elkhartlake/bootblock/bootblock.c @@ -32,11 +32,7 @@ /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); - if (CONFIG(SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN)) { - uint16_t reg = tco_read_reg(TCO1_CNT); - /* NO_REBOOT is enabled via bit 0 in TCO1_CNT. */ - reg |= 0x01; - tco_write_reg(TCO1_CNT, reg); - printk(BIOS_DEBUG, "TCO: Disable reset on second expiration.\n"); - } + + if (CONFIG(SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN)) + tco_set_no_reboot(); } diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c index 7dee348..bb14070 100644 --- a/src/soc/intel/elkhartlake/pmutil.c +++ b/src/soc/intel/elkhartlake/pmutil.c @@ -238,8 +238,8 @@ { uint8_t *pmc; - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS); printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index f1d4d21..0f5acdd 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -238,8 +238,8 @@ { uint8_t *pmc; - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS); printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index 7e00ca5..34e0f32 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -238,8 +238,8 @@ { uint8_t *pmc; - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS); printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); diff --git a/src/soc/intel/meteorlake/pmutil.c b/src/soc/intel/meteorlake/pmutil.c index 29ef32f..29b9df9 100644 --- a/src/soc/intel/meteorlake/pmutil.c +++ b/src/soc/intel/meteorlake/pmutil.c @@ -220,8 +220,8 @@ { uint8_t *pmc; - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS); printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index c234e30..5e97c97 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -224,8 +224,8 @@ { uint8_t *pmc; - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS); printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 1fb2b07..a308020 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -244,8 +244,8 @@ { uint8_t *pmc; - ps->tco1_sts = tco_read_reg(TCO1_STS); - ps->tco2_sts = tco_read_reg(TCO2_STS); + ps->tco1_sts = tco_read16(TCO1_STS); + ps->tco2_sts = tco_read16(TCO2_STS); printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts); -- To view, visit https://review.coreboot.org/c/coreboot/+/70052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0090585bf6f30482952af40a985b086cf7bd91e6 Gerrit-Change-Number: 70052 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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