coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/intel/meteorlake: Rename method is_eom to is_manufacturing_mode
by Eric Lai (Code Review) 28 Nov '22

28 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Paul Menzel, Rizwan Qureshi, Sridhar Siricilla. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69698 ) Change subject: soc/intel/meteorlake: Rename method is_eom to is_manufacturing_mode ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/meteorlake/me.c: https://review.coreboot.org/c/coreboot/+/69698/comment/7c9a67b8_ce8ec898 PS3, Line 98: manuf manufacture, I think no need to short the variable name. -- To view, visit https://review.coreboot.org/c/coreboot/+/69698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d2de3365126ba618c987c412c4e9784012f9e0b Gerrit-Change-Number: 69698 Gerrit-PatchSet: 3 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Mon, 28 Nov 2022 01:10:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Print vars related to ME mfg mode
by Eric Lai (Code Review) 28 Nov '22

28 Nov '22

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69739 ) Change subject: soc/intel/meteorlake: Print vars related to ME mfg mode ...................................................................... soc/intel/meteorlake: Print vars related to ME mfg mode BUG=none TEST=Build and boot to google/rex. Excerpt from google/rex coreboot log: [DEBUG] ME: FPFs Committed : NO [DEBUG] ME: Manufacturing Vars Locked : NO Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: Iec07c1f951fbbf51541917c8b99d19f2f12980b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69739 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/meteorlake/me.c 1 file changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/me.c b/src/soc/intel/meteorlake/me.c index 743e963..f746fe0 100644 --- a/src/soc/intel/meteorlake/me.c +++ b/src/soc/intel/meteorlake/me.c @@ -123,6 +123,10 @@ */ printk(BIOS_DEBUG, "ME: SPI Protection Mode Enabled : %s\n", hfsts1.fields.mfg_mode ? "NO" : "YES"); + printk(BIOS_DEBUG, "ME: FPFs Committed : %s\n", + hfsts6.fields.fpf_soc_lock ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Manufacturing Vars Locked : %s\n", + hfsts6.fields.manuf_lock ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfsts1.fields.fpt_bad ? "BAD" : "OK"); printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/69739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec07c1f951fbbf51541917c8b99d19f2f12980b2 Gerrit-Change-Number: 69739 Gerrit-PatchSet: 4 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: util/ifdtool/Makefile.inc: Respect LDFLAGS from environment
by Reka Norman (Code Review) 28 Nov '22

28 Nov '22

Reka Norman has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70054 ) Change subject: util/ifdtool/Makefile.inc: Respect LDFLAGS from environment ...................................................................... util/ifdtool/Makefile.inc: Respect LDFLAGS from environment The ChromeOS build system performs ASAN builds by appending -fsanitize=address to CFLAGS and LDFLAGS. Currently, the ASAN build of ifdtool fails with linker errors because the Makefile does not respect LDFLAGS. Modify the Makefile to respect LDFLAGS from the environment. This is consistent with the Makefiles of most other coreboot utils. BUG=b:255462682 TEST=`USE=asan emerge-nissa coreboot-utils` now succeeds with CL:4018976 Change-Id: I1a497562d4d979829edb47c4c4b3f2c64266324e Signed-off-by: Reka Norman <rekanorman(a)chromium.org> --- M util/ifdtool/Makefile.inc 1 file changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/70054/1 diff --git a/util/ifdtool/Makefile.inc b/util/ifdtool/Makefile.inc index eb3a700..2b97bf5 100644 --- a/util/ifdtool/Makefile.inc +++ b/util/ifdtool/Makefile.inc @@ -16,4 +16,4 @@ $(objutil)/ifdtool/ifdtool: $(addprefix $(objutil)/ifdtool/,$(ifdtoolobj)) printf " IFDTOOL\n" - $(HOSTCC) $(addprefix $(objutil)/ifdtool/,$(ifdtoolobj)) -o $@ + $(HOSTCC) ${LDFLAGS} $(addprefix $(objutil)/ifdtool/,$(ifdtoolobj)) -o $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/70054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a497562d4d979829edb47c4c4b3f2c64266324e Gerrit-Change-Number: 70054 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add MTL-P RVP board ids
by Eric Lai (Code Review) 28 Nov '22

28 Nov '22

Attention is currently required from: Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Sridhar Siricilla, Angel Pons, Krishna P Bhat D, Tim Wawrzynczak, Tarun Tuli, Jamie Ryu, Subrata Banik, Harsha B R, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Usha P, Raj Astekar. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66102 ) Change subject: mb/intel/mtlrvp: Add MTL-P RVP board ids ...................................................................... Patch Set 8: (1 comment) File src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h: https://review.coreboot.org/c/coreboot/+/66102/comment/2875cfa4_2390146c PS8, Line 19: /* Functions to configure GPIO as per variant schematics */ : void variant_configure_gpio_pads(void); : void variant_configure_early_gpio_pads(void); : : size_t variant_memory_sku(void); : const struct mb_cfg *variant_memory_params(void); irrelevant to the comment. you can separate or add in comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/66102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90b0543d5db208f696d2c2c2dc3d2581514a845b Gerrit-Change-Number: 66102 Gerrit-PatchSet: 8 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Mon, 28 Nov 2022 00:21:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/quark: Fix out() parameter order
by Eric Lai (Code Review) 28 Nov '22

28 Nov '22

Attention is currently required from: Kyösti Mälkki. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70051 ) Change subject: soc/intel/quark: Fix out() parameter order ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4db09632a41d28b0c8e211e6232db4e6d85bdf5f Gerrit-Change-Number: 70051 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 28 Nov 2022 00:15:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: /: Update and rewrite README.md
by Martin L Roth (Code Review) 28 Nov '22

28 Nov '22

Attention is currently required from: Felix Singer, Matt DeVillier, Angel Pons, Martin Roth. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67119 ) Change subject: /: Update and rewrite README.md ...................................................................... Patch Set 5: (3 comments) File README.md: https://review.coreboot.org/c/coreboot/+/67119/comment/0728134e_768936f5 PS4, Line 27: `git clone https://review.coreboot.org/coreboot.git`. > Maybe point to `https://review.coreboot. […] This has nothing to do with gerrit, this is pure git. Nothing should be changing here without needing a pretty significant update. https://review.coreboot.org/c/coreboot/+/67119/comment/a736ea1d_8a563559 PS4, Line 37: suggest > What does "suggest" mean here? will change to 'accept' https://review.coreboot.org/c/coreboot/+/67119/comment/771bdecf_37a54269 PS4, Line 179: > There's also commonlib/bsd, should it be mentioned? Yes, good point. -- To view, visit https://review.coreboot.org/c/coreboot/+/67119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cd59d75da47b287029a9fc5eeddefaf99198965 Gerrit-Change-Number: 67119 Gerrit-PatchSet: 5 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 28 Nov 2022 00:01:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/nissa/xivu: Add eMMC DLL tuning value
by Kangheui Won (Code Review) 28 Nov '22

28 Nov '22

Attention is currently required from: Tarun Tuli, Henry Sun, Reka Norman, Lawrence Chang, Shou-Chieh Hsu. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69892 ) Change subject: mb/google/nissa/xivu: Add eMMC DLL tuning value ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa8338fd0faa0e01f42ee77dea135c7a241ed3be Gerrit-Change-Number: 69892 Gerrit-PatchSet: 2 Gerrit-Owner: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Lawrence Chang <lawrence.chang(a)intel.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Sun, 27 Nov 2022 23:40:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/crossgcc: Add option to get packages from coreboot's mirror
by Felix Singer (Code Review) 28 Nov '22

28 Nov '22

Attention is currently required from: Martin L Roth, Patrick Georgi, Angel Pons. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70053 ) Change subject: util/crossgcc: Add option to get packages from coreboot's mirror ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Something broke building GMP for the toolchain builder. I don't know what exactly. […] It's not just this patch. Others of mine are also affected. I checked the last submitted patches that changed util/crossgcc and all passed Jenkins. So I don't know. Maybe something on the build node is misconfigured? -- To view, visit https://review.coreboot.org/c/coreboot/+/70053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7df58dca152e7bfe9fde34d290e05b52515b20d9 Gerrit-Change-Number: 70053 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 27 Nov 2022 22:45:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/crossgcc: Add option to get packages from coreboot's mirror
by Felix Singer (Code Review) 28 Nov '22

28 Nov '22

Attention is currently required from: Martin L Roth, Patrick Georgi, Angel Pons. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70053 ) Change subject: util/crossgcc: Add option to get packages from coreboot's mirror ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Something broke building GMP for the toolchain builder. I don't know what exactly. Building locally works for me. -- To view, visit https://review.coreboot.org/c/coreboot/+/70053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7df58dca152e7bfe9fde34d290e05b52515b20d9 Gerrit-Change-Number: 70053 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 27 Nov 2022 22:31:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Revert "sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros"
by Kyösti Mälkki (Code Review) 27 Nov '22

27 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70042 ) Change subject: Revert "sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros" ...................................................................... Revert "sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros" This reverts commit 9f0e21a4dae864809e9651403ab5bad48e784bee. It should be allowed for i82801gx/early_init.c to have #include <southbridge/intel/common/pmutil.h> But there is a conflict: src/southbridge/intel/common/pmutil.h: #define TCO1_CNT 0x68 src/southbridge/intel/common/tco.h: #define TCO1_CNT 0x08 Followup works resolve the difficulties around the offset 0x60 used for TCO register bank, tree-wide. Change-Id: I827558a0e0ef1c4d1f866756df51cd1b2abfc7a0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70042 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/lpc.c 3 files changed, 37 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index dda5c00..deb3deb 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -6,7 +6,6 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/rcba.h> -#include <southbridge/intel/common/tco.h> #include "chip.h" #include "i82801gx.h" @@ -58,6 +57,8 @@ pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN); } +#define TCO_BASE 0x60 + #if ENV_RAMINIT void i82801gx_early_init(void) { @@ -71,9 +72,9 @@ printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, TCO_TMR_HLT); - write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT); - write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS); + write_pmbase16(TCO_BASE + 0x8, (1 << 11)); /* halt timer */ + write_pmbase16(TCO_BASE + 0x4, (1 << 3)); /* clear timeout */ + write_pmbase16(TCO_BASE + 0x6, (1 << 1)); /* clear 2nd timeout */ printk(BIOS_DEBUG, " done.\n"); /* program secondary mlt XXX byte? */ diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 0625db0..ee34f74 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -323,6 +323,7 @@ #define DEVACT_STS 0x44 #define SS_CNT 0x50 #define C3_RES 0x54 +#define TCO1_CNT 0x68 #endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index f8a2dac8..fd0a203 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -20,7 +20,6 @@ #include <southbridge/intel/common/hpet.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/spi.h> -#include <southbridge/intel/common/tco.h> #include "chip.h" #include "i82801gx.h" @@ -428,9 +427,9 @@ pci_or_config16(dev, GEN_PMCON_1, 1 << 4); /* TCO_Lock */ - tco1_cnt = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT); + tco1_cnt = inw(DEFAULT_PMBASE + 0x60 + TCO1_CNT); tco1_cnt |= (1 << 12); /* TCO lock */ - write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, tco1_cnt); + outw(tco1_cnt, DEFAULT_PMBASE + 0x60 + TCO1_CNT); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); -- To view, visit https://review.coreboot.org/c/coreboot/+/70042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I827558a0e0ef1c4d1f866756df51cd1b2abfc7a0 Gerrit-Change-Number: 70042 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2022