coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: arch/x86: Add bitwise operations for IO space
by Kyösti Mälkki (Code Review) 27 Nov '22

27 Nov '22

Attention is currently required from: Angel Pons. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70041 ) Change subject: arch/x86: Add bitwise operations for IO space ...................................................................... Patch Set 1: Code-Review-2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/70041/comment/e469f19a_31bad805 PS1, Line 8: > You could mention that: […] Yeah, let's keep this on hold, improve the message, and only submit once the actual use cases are ready for submission too. I think I will want to add some sort of is_set(PM_REGISTER, bit) style conditional. -- To view, visit https://review.coreboot.org/c/coreboot/+/70041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3e1146f062dced1b75195846ea65a44e2bd4482 Gerrit-Change-Number: 70041 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 27 Nov 2022 20:28:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/crossgcc: Add option to get packages from coreboot's mirror
by Martin L Roth (Code Review) 27 Nov '22

27 Nov '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70053 ) Change subject: util/crossgcc: Add option to get packages from coreboot's mirror ...................................................................... util/crossgcc: Add option to get packages from coreboot's mirror coreboot has been keeping a mirror of all the toolchain packages used for releases for quite a while now. This adds an option to fetch the packages from the coreboot mirror directly to buildgcc. To do this, the url and filename needed to be split apart, which led to quite a few changes in the buildgcc script. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I7df58dca152e7bfe9fde34d290e05b52515b20d9 --- M util/crossgcc/Makefile.inc M util/crossgcc/buildgcc 2 files changed, 80 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/70053/1 diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index a52fbf1..4534aaa 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -3,6 +3,7 @@ TOOLCHAIN_ARCHES := i386 x64 arm aarch64 riscv ppc64 nds32le help_toolchain help:: + @echo @echo '*** Toolchain targets ***' @echo ' crossgcc - Build coreboot cross-compilers for all platforms' @echo ' crossgcc-clean - Remove all built coreboot cross-compilers' @@ -14,6 +15,7 @@ @echo ' ARCH can be "$(subst $(spc),"$(comma) ",$(TOOLCHAIN_ARCHES))"' @echo ' Use "make [target] CPUS=#" to build toolchain using multiple cores' @echo ' Use "make [target] DEST=some/path" to install toolchain there' + @echo ' Use "make [target] BUILDGCC_OPTIONS="-m" to get packages from coreboot mirror" @echo # For the toolchain builds, use CPUS=x to use multiple processors to build diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 0d349f2..4c2cf8a 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -30,6 +30,8 @@ SAVETEMPS=0 BOOTSTRAP=0 THREADS=1 +USE_COREBOOT_MIRROR=0 +COREBOOT_MIRROR_URL="https://www.coreboot.org/releases/crossgcc-sources" # GCC toolchain version numbers GMP_VERSION=6.2.1 @@ -43,29 +45,46 @@ CMAKE_VERSION=3.24.2 NASM_VERSION=2.15.05 -# GCC toolchain archive locations -# These are sanitized by the jenkins toolchain test builder, so if +# Filename for each package +GMP_ARCHIVE="gmp-${GMP_VERSION}.tar.xz" +MPFR_ARCHIVE="mpfr-${MPFR_VERSION}.tar.xz" +MPC_ARCHIVE="mpc-${MPC_VERSION}.tar.gz" +GCC_ARCHIVE="gcc-${GCC_VERSION}.tar.xz" +BINUTILS_ARCHIVE="binutils-${BINUTILS_VERSION}.tar.xz" +IASL_ARCHIVE="acpica-unix2-${IASL_VERSION}.tar.gz" +# CLANG toolchain FILE locations +LLVM_ARCHIVE="llvm-${CLANG_VERSION}.src.tar.xz" +CLANG_ARCHIVE="clang-${CLANG_VERSION}.src.tar.xz" +CRT_ARCHIVE="compiler-rt-${CLANG_VERSION}.src.tar.xz" +CTE_ARCHIVE="clang-tools-extra-${CLANG_VERSION}.src.tar.xz" +LLVMCMAKE_ARCHIVE="cmake-${CLANG_VERSION}.src.tar.xz" +CMAKE_ARCHIVE="cmake-${CMAKE_VERSION}.tar.gz" +NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2" + +# These URLs are sanitized by the jenkins toolchain test builder, so if # a completely new URL is added here, it probably needs to be added # to the jenkins build as well, or the builder won't download it. -GMP_ARCHIVE="https://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.xz" -MPFR_ARCHIVE="https://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.xz" -MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz" -GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz" -BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz" -IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz" -# CLANG toolchain archive locations -LLVM_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERS…" -CLANG_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERS…" -CRT_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERS…" -CTE_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERS…" -LLVMCMAKE_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERS…" -CMAKE_ARCHIVE="https://cmake.org/files/v${CMAKE_VERSION%.*}/cmake-${CMAKE_VERSION}.tar.gz" -NASM_ARCHIVE="https://www.nasm.us/pub/nasm/releasebuilds/${NASM_VERSION}/nasm-${NASM_VERS…" -ALL_ARCHIVES="$GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE \ - $GCC_ARCHIVE $BINUTILS_ARCHIVE $IASL_ARCHIVE \ - $LLVM_ARCHIVE $CLANG_ARCHIVE $LLVMCMAKE_ARCHIVE \ - $CRT_ARCHIVE $CTE_ARCHIVE $CMAKE_ARCHIVE $NASM_ARCHIVE" +# GCC toolchain archive locations +GMP_BASE_URL="https://ftpmirror.gnu.org/gmp" +MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" +MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" +GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" +BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" +IASL_BASE_URL="https://acpica.org/sites/acpica/files" +# CLANG toolchain archive locations +LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERS…" +CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERS…" +CRT_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERS…" +CTE_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERS…" +LLVMCMAKE_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERS…" +CMAKE_BASE_URL="https://cmake.org/files/v${CMAKE_VERSION%.*}" +NASM_BASE_URL="https://www.nasm.us/pub/nasm/releasebuilds/${NASM_VERSION}" + +ALL_ARCHIVES="$GMP_BASE_URL/$GMP_ARCHIVE $MPFR_BASE_URL/$MPFR_ARCHIVE $MPC_BASE_URL/$MPC_ARCHIVE \ + $GCC_BASE_URL/$GCC_ARCHIVE $BINUTILS_BASE_URL/$BINUTILS_ARCHIVE $IASL_BASE_URL/$IASL_ARCHIVE \ + $LLVM_BASE_URL/$LLVM_ARCHIVE $CLANG_BASE_URL/$CLANG_ARCHIVE $LLVMCMAKE_BASE_URL/$LLVMCMAKE_ARCHIVE \ + $CRT_BASE_URL/$CRT_ARCHIVE $CTE_BASE_URL/$CTE_ARCHIVE $CMAKE_BASE_URL/$CMAKE_ARCHIVE $NASM_BASE_URL/$NASM_ARCHIVE" # GCC toolchain directories GMP_DIR="gmp-${GMP_VERSION}" @@ -300,23 +319,27 @@ download() { package=$1 # shellcheck disable=SC2086 - archive="$(eval echo \$$package"_ARCHIVE")" + if [ "${USE_COREBOOT_MIRROR}" -eq 0 ]; then + url="$(eval echo \$$package"_BASE_URL")" + else + url="${COREBOOT_MIRROR_URL}" + fi - FILE=$(basename "$archive") - printf " * $FILE " + file="$(eval echo \$$package"_ARCHIVE")" + printf " * ${file} " - if test -f "tarballs/$FILE"; then + if test -f "tarballs/${file}"; then printf "(cached)... " else - printf "(downloading from $archive)" - rm -f "tarballs/$FILE" + printf "(downloading from ${url}/${file})" + rm -f "tarballs/${file}" cd tarballs || exit 1 - download_showing_percentage "$archive" + download_showing_percentage "${url}/${file}" cd .. fi - if [ ! -f "tarballs/$FILE" ]; then - printf "${RED}Failed to download $FILE.${NC}\n" + if [ ! -f "tarballs/${file}" ]; then + printf "${RED}Failed to download ${file}.${NC}\n" exit 1 fi } @@ -326,8 +349,7 @@ compute_hash() { package=$1 # shellcheck disable=SC2086 - archive="$(eval echo \$$package"_ARCHIVE")" - file="$(basename "$archive")" + file="$(eval echo \$$package"_ARCHIVE")" if test -z "$CHECKSUM"; then echo "${RED}\$CHECKSUM program missing. This is bad.${NC}" 1>&2 @@ -340,8 +362,7 @@ error_hash_missing() { package="$1" # shellcheck disable=SC2086 - archive="$(eval echo \$$package"_ARCHIVE")" - file="$(basename "$archive")" + file="$(eval echo \$$package"_ARCHIVE")" fullhashfile="util/crossgcc/sum/$file.cksum" printf "${RED}hash file missing:${NC}\n\n" 1>&2 @@ -357,8 +378,7 @@ get_known_hash() { package=$1 # shellcheck disable=SC2086 - archive="$(eval echo \$$package"_ARCHIVE")" - file="$(basename "$archive")" + file="$(eval echo \$$package"_ARCHIVE")" hashfile="sum/$file.cksum" if [ ! -f "$hashfile" ]; then @@ -377,8 +397,7 @@ known_hash="$2" computed_hash="$3" # shellcheck disable=SC2086 - archive="$(eval echo \$$package"_ARCHIVE")" - file="$(basename "$archive")" + file="$(eval echo \$$package"_ARCHIVE")" printf "${RED}hash mismatch:${NC}\n\n" printf " expected (known) hash: $known_hash\n" @@ -397,8 +416,6 @@ # hash; Bail out on mismatch or missing hash file. verify_hash() { package=$1 - # shellcheck disable=SC2086 - archive="$(eval echo \$$package"_ARCHIVE")" known_hash="$(get_known_hash "$package")" || exit "$?" computed_hash="$(compute_hash "$package")" || exit "$?" @@ -418,7 +435,7 @@ # shellcheck disable=SC2086 dir="$(eval echo \$$package"_DIR")" test -d "${dir}" && test -f "${dir}/.unpack_success" || ( - printf " * $(basename "$archive")\n" + printf " * "$archive"\n" FLAGS=zxf suffix=$(echo "$archive" | sed 's,.*\.,,') if [ "$suffix" = "gz" ] && [ -n "$PIGZ" ]; then FLAGS="-I pigz -xf" @@ -429,7 +446,7 @@ elif [ "$suffix" = "lzma" ]; then FLAGS="--lzma -xf" fi # shellcheck disable=SC2086 - $TAR $FLAGS "tarballs/$(basename "$archive")" + $TAR $FLAGS "tarballs/$archive" for patch in patches/${dir}_*.patch; do test -r "$patch" || continue printf " o $(basename "$patch")\n" @@ -876,12 +893,12 @@ getoptbrand="$(getopt -V 2>/dev/null | sed -e '1!d' -e 's,^$......$.*,\1,')" if [ "${getoptbrand}" = "getopt" ]; then # Detected GNU getopt that supports long options. - args=$(getopt -l print-version,version,help,clean,directory:,bootstrap,bootstrap-only,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported:,urls,nocolor -o WVhcd:bBp:l:P:j:D:tSys:un -- "$@") + args=$(getopt -l print-version,version,help,clean,directory:,bootstrap,bootstrap-only,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported:,urls,nocolor,mirror -o WVhcd:bBp:l:P:j:D:tSys:unm -- "$@") getopt_ret=$? eval set -- "$args" else # Detected non-GNU getopt - args=$(getopt WVhcd:bBp:l:P:j:D:tSys:un $*) + args=$(getopt WVhcd:bBp:l:P:j:D:tSys:unm $*) getopt_ret=$? # shellcheck disable=SC2086 set -- $args @@ -904,6 +921,7 @@ -B|--bootstrap-only) shift; BOOTSTRAPONLY=1; BOOTSTRAP=1;; -p|--platform) shift; TARGETARCH="$1"; shift;; -l|--languages) shift; LANGUAGES="$1"; shift;; + -m|--mirror) shift; USE_COREBOOT_MIRROR=1;; -D|--destdir) shift; DESTDIR="$1"; shift;; -j|--jobs) shift; THREADS="$1"; JOBS="-j $1"; shift;; -P|--package) shift; PACKAGE="$1"; shift;; -- To view, visit https://review.coreboot.org/c/coreboot/+/70053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7df58dca152e7bfe9fde34d290e05b52515b20d9 Gerrit-Change-Number: 70053 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/tigerlake: Fix setting `HyperThreading`
by Felix Singer (Code Review) 27 Nov '22

27 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Angel Pons. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69534 ) Change subject: soc/intel/tigerlake: Fix setting `HyperThreading` ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea60b89f6f970eb9aee8c7bec026ab5c2df30205 Gerrit-Change-Number: 69534 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 27 Nov 2022 18:27:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: security/tpm/: turn tis_{init,open} into tis_probe
by Sergii Dmytruk (Code Review) 27 Nov '22

27 Nov '22

Attention is currently required from: Michał Żygowski, Christian Walter, Julius Werner, Krystian Hebel, Yu-Ping Wu. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68991 ) Change subject: security/tpm/: turn tis_{init,open} into tis_probe ...................................................................... Patch Set 3: (1 comment) File src/security/tpm/tss/tcg-1.2/tss.c: https://review.coreboot.org/c/coreboot/+/68991/comment/57f2172e_731f3a6a PS2, Line 35: tis_sendrecv > Done. […] The change seems to have caused https://qa.coreboot.org/job/coreboot-gerrit/223415/ failures. -- To view, visit https://review.coreboot.org/c/coreboot/+/68991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4ce35ada24e3959ea1a518c29d431b4ae123809 Gerrit-Change-Number: 68991 Gerrit-PatchSet: 3 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sun, 27 Nov 2022 18:19:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: nb/intel/sandybridge: Add a chipset devicetree
by Martin L Roth (Code Review) 27 Nov '22

27 Nov '22

Attention is currently required from: Arthur Heymans, Angel Pons, Evgeny Zinoviev, Alexander Couzens, Patrick Rudolph. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56912 ) Change subject: nb/intel/sandybridge: Add a chipset devicetree ...................................................................... Patch Set 5: (1 comment) File src/northbridge/intel/sandybridge/chipset.cb: https://review.coreboot.org/c/coreboot/+/56912/comment/1609dc09_87ae9bee PS5, Line 19: device pci 00.0 alias hb on end # host bridge : device pci 01.0 alias peg10 off end # PEG10 : device pci 01.1 alias peg11 off end # PEG11 : device pci 01.2 alias peg12 off end # PEG12 : device pci 02.0 alias igd off end # vga controller : device pci 04.0 alias dev4 off end # Device 4 : device pci 06.0 alias peg60 off end # PEG60 : : chip southbridge/intel/bd82x6x # Intel Series 6/7 PCH : device pci 14.0 alias xhci off end # USB 3.0 Controller (only on 7 series) : device pci 16.0 alias mei1 off end # Management Engine Interface 1 : device pci 16.1 alias mei2 off end # Management Engine Interface 2 : device pci 16.2 alias me_ide_r off end # Management Engine IDE-R : device pci 16.3 alias me_kt off end # Management Engine KT : device pci 19.0 alias gbe off end # Intel Gigabit Ethernet : device pci 1a.0 alias ehci2 off end # USB2 EHCI #2 : device pci 1b.0 alias hda off end # High Definition Audio : device pci 1c.0 alias rp1 off end # PCIe Port #1 : device pci 1c.1 alias rp2 off end # PCIe Port #2 : device pci 1c.2 alias rp3 off end # PCIe Port #3 : device pci 1c.3 alias rp4 off end # PCIe Port #4 : device pci 1c.4 alias rp5 off end # PCIe Port #5 : device pci 1c.5 alias rp6 off end # PCIe Port #6 : device pci 1c.6 alias rp7 off end # PCIe Port #7 : device pci 1c.7 alias rp8 off end # PCIe Port #8 : device pci 1d.0 alias ehci1 off end # USB2 EHCI #1 : device pci 1e.0 alias pci_b off end # PCI bridge : device pci 1f.0 alias lpc on end # LPC bridge : device pci 1f.2 alias sata1 off end # SATA Controller 1 : device pci 1f.3 alias smbus on end # SMBus : device pci 1f.5 alias sata2 off end # SATA Controller 2 : device pci 1f.6 alias thermal off end # Thermal : end > Do you *need* to define the PCI devices in the chipset devicetree in this patch? It would seem that […] Sorry, what do you mean? why would the aliases break things? -- To view, visit https://review.coreboot.org/c/coreboot/+/56912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87 Gerrit-Change-Number: 56912 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 27 Nov 2022 17:21:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Create baseboard structure for mtlrvp
by Martin L Roth (Code Review) 27 Nov '22

27 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69971 ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/intel/mtlrvp: Create baseboard structure for mtlrvp ...................................................................... mb/intel/mtlrvp: Create baseboard structure for mtlrvp This patch will create the baseboard structure for mtlrvp. Changes include, 1. Adding Baseboard config for mtlrvp in Kconfig 2. Move gpio.h to corresponding baseboard directory 3. Append header reference to CPPFLAGS_common in Makefile.inc BUG=none TEST=FW_NAME=mtlrvp_p emerge-rex coreboot chromeos-bootimage Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I82acb6879fecb242014258f2c358804d5abbbd48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69971 Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/Makefile.inc R src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/include/baseboard/gpio.h 3 files changed, 32 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved Ronak Kanabar: Looks good to me, approved diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index e73d26a..db7c161 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -13,6 +13,10 @@ config MAINBOARD_DIR default "intel/mtlrvp" +config BASEBOARD_DIR + string + default "mtlrvp" + config MAINBOARD_PART_NUMBER string default "mtlrvp" diff --git a/src/mainboard/intel/mtlrvp/Makefile.inc b/src/mainboard/intel/mtlrvp/Makefile.inc index 830a6d3..71ca021 100644 --- a/src/mainboard/intel/mtlrvp/Makefile.inc +++ b/src/mainboard/intel/mtlrvp/Makefile.inc @@ -1,5 +1,9 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) +BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR)) +subdirs-y += variants/baseboard/$(BASEBOARD_DIR) subdirs-y += variants/$(VARIANT_DIR) + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include diff --git a/src/mainboard/intel/mtlrvp/include/baseboard/gpio.h b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/include/baseboard/gpio.h similarity index 100% rename from src/mainboard/intel/mtlrvp/include/baseboard/gpio.h rename to src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/include/baseboard/gpio.h -- To view, visit https://review.coreboot.org/c/coreboot/+/69971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82acb6879fecb242014258f2c358804d5abbbd48 Gerrit-Change-Number: 69971 Gerrit-PatchSet: 8 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: mb/amd/mayan: Add framework for morgana crb mayan
by Martin L Roth (Code Review) 27 Nov '22

27 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70010 ) Change subject: mb/amd/mayan: Add framework for morgana crb mayan ...................................................................... mb/amd/mayan: Add framework for morgana crb mayan mayan is the reference board for the morgana SoC. It needs to be updated to match the actual board design as well. amd/mayan is started as a copy of amd/birman. Change-Id: Id6801e6c6e706ae3878ce9e2c3d6452964235148 Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70010 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/mainboard/amd/mayan/Kconfig A src/mainboard/amd/mayan/Kconfig.name A src/mainboard/amd/mayan/Makefile.inc A src/mainboard/amd/mayan/board.fmd A src/mainboard/amd/mayan/board_info.txt A src/mainboard/amd/mayan/bootblock.c A src/mainboard/amd/mayan/chromeos.c A src/mainboard/amd/mayan/chromeos.fmd A src/mainboard/amd/mayan/devicetree_morgana.cb A src/mainboard/amd/mayan/dsdt.asl A src/mainboard/amd/mayan/early_gpio.c A src/mainboard/amd/mayan/ec.c A src/mainboard/amd/mayan/ec.h A src/mainboard/amd/mayan/gpio.c A src/mainboard/amd/mayan/gpio.h A src/mainboard/amd/mayan/mainboard.c A src/mainboard/amd/mayan/port_descriptors.c 17 files changed, 815 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/mayan/Kconfig b/src/mainboard/amd/mayan/Kconfig new file mode 100644 index 0000000..8a54481 --- /dev/null +++ b/src/mainboard/amd/mayan/Kconfig @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_AMD_MAYAN_MORGANA + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 # Mayan actually has a 32MiB ROM + select EC_ACPI + select SOC_AMD_COMMON_BLOCK_USE_ESPI + select AMD_SOC_CONSOLE_UART + select MAINBOARD_HAS_CHROMEOS + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE + select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN + +config FMDFILE + default "src/mainboard/amd/mayan/chromeos.fmd" if CHROMEOS + default "src/mainboard/amd/mayan/board.fmd" + +config MAINBOARD_DIR + default "amd/mayan" + +config MAINBOARD_PART_NUMBER + default "Mayan_Morgana" + +config DEVICETREE + default "devicetree_morgana.cb" + +config AMD_FWM_POSITION_INDEX + int + default 3 if CHROMEOS + help + TODO: might need to be adapted for better placement of files in cbfs + +config MAYAN_HAVE_MCHP_FW + bool "Have Microchip EC firmware?" + default n + +config MAYAN_MCHP_SIG_FILE + string "Microchip EC signature file" + depends on MAYAN_HAVE_MCHP_FW + default "3rdparty/blobs/mainboard/amd/mayan/EC_mayan_sig.bin" + help + The EC sig blob is the first 4kBytes of the firmware image. + The first 4 bytes form a pointer (with CRC) to where the EC firmware + is located + +config MAYAN_MCHP_FW_FILE + string "Microchip EC firmware file" + depends on MAYAN_HAVE_MCHP_FW + default "3rdparty/blobs/mainboard/amd/mayan/EC_mayan.bin" + help + The EC firmware blob is at the MAYAN_MCHP_FW_OFFSET offset of the + firmware image. + +config MAYAN_MCHP_FW_OFFSET + hex + depends on MAYAN_HAVE_MCHP_FW + default 0xB80000 + help + The EC firmware blob defaults to the 4MByte offset of the firmware + image. If this offset needs to change, a new signature block must be + generated with the updated offset. + +config VBOOT + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_STARTS_IN_BOOTBLOCK + +config VBOOT_VBNV_OFFSET + hex + default 0x2A + +config RO_REGION_ONLY + string + depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A + # Add the EFS and EC to the RO region only + # This is a mayan-specific override of soc/amd/morgana/Kconfig + default "apu/amdfw apu/ecfw" + +config CHROMEOS + # Use default libpayload config + select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE + # We don't have recovery buttons, so we can't manually enable devmode. + select GBB_FLAG_FORCE_DEV_SWITCH_ON + +if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig +config EFS_SPI_READ_MODE + default 3 # Quad IO (1-1-4) + +config EFS_SPI_SPEED + default 0 # 66MHz + +config EFS_SPI_MICRON_FLAG + default 0 + +config NORMAL_READ_SPI_SPEED + default 1 # 33MHz + +config ALT_SPI_SPEED + default 1 # 33MHz + +config TPM_SPI_SPEED + default 1 # 33MHz + +endif # !EM100 + +endif # BOARD_AMD_MAYAN_MORGANA diff --git a/src/mainboard/amd/mayan/Kconfig.name b/src/mainboard/amd/mayan/Kconfig.name new file mode 100644 index 0000000..1d60d67 --- /dev/null +++ b/src/mainboard/amd/mayan/Kconfig.name @@ -0,0 +1,5 @@ +comment "Mayan" + +config BOARD_AMD_MAYAN_MORGANA + bool "-> Mayan for Morgana SoC" + select SOC_AMD_MORGANA diff --git a/src/mainboard/amd/mayan/Makefile.inc b/src/mainboard/amd/mayan/Makefile.inc new file mode 100644 index 0000000..fdf00ea --- /dev/null +++ b/src/mainboard/amd/mayan/Makefile.inc @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += early_gpio.c +bootblock-y += ec.c + +romstage-y += port_descriptors.c + +ramstage-y += chromeos.c +ramstage-y += gpio.c + +ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_Updatable.bin),) +APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_Updatable.bin +APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_DefaultRecovery.bin +else +$(info APCB sources not found. Skipping APCB. The resulting image won't boot.) +endif + +ifeq ($(CONFIG_MAYAN_HAVE_MCHP_FW),y) +$(call add_intermediate, add_mchp_fw) + $(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_MAYAN_MCHP_SIG_FILE) --fill-upward + +# calculate the absolute position from the config offset +MAYAN_EC_POSITION=$(call int-add, \ + $(call int-subtract, 0xffffffff \ + $(CONFIG_ROM_SIZE)) $(CONFIG_MAYAN_MCHP_FW_OFFSET) 1) + +cbfs-files-y += apu/ecfw +apu/ecfw-file := $(CONFIG_MAYAN_MCHP_FW_FILE) +apu/ecfw-position := $(MAYAN_EC_POSITION) +apu/ecfw-type := raw + +else +files_added:: warn_no_mchp +endif # CONFIG_MAYAN_HAVE_MCHP_FW + +PHONY+=warn_no_mchp +warn_no_mchp: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without the EC FW.\n" + printf "Do not flash this image. Your Mayan's power button\n" + printf "will not respond when you press it.\n\n" diff --git a/src/mainboard/amd/mayan/board.fmd b/src/mainboard/amd/mayan/board.fmd new file mode 100644 index 0000000..6c6ad92 --- /dev/null +++ b/src/mainboard/amd/mayan/board.fmd @@ -0,0 +1,8 @@ +FLASH@0xFF000000 16M { + BIOS { + EC 4K + RW_MRC_CACHE 120K + FMAP 4K + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/amd/mayan/board_info.txt b/src/mainboard/amd/mayan/board_info.txt new file mode 100644 index 0000000..b351b8e --- /dev/null +++ b/src/mainboard/amd/mayan/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/amd/mayan/bootblock.c b/src/mainboard/amd/mayan/bootblock.c new file mode 100644 index 0000000..4c01cc1 --- /dev/null +++ b/src/mainboard/amd/mayan/bootblock.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/espi.h> +#include "ec.h" +#include "gpio.h" + +void bootblock_mainboard_early_init(void) +{ + mainboard_program_early_gpios(); + + espi_switch_to_spi1_pads(); +} + +void bootblock_mainboard_init(void) +{ + mayan_ec_init(); +} diff --git a/src/mainboard/amd/mayan/chromeos.c b/src/mainboard/amd/mayan/chromeos.c new file mode 100644 index 0000000..3119303 --- /dev/null +++ b/src/mainboard/amd/mayan/chromeos.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootmode.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <types.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = {}; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + /* Mayan doesn't have a write protect pin */ + return 0; +} + +DECLARE_NO_CROS_GPIOS(); diff --git a/src/mainboard/amd/mayan/chromeos.fmd b/src/mainboard/amd/mayan/chromeos.fmd new file mode 100644 index 0000000..c28070a --- /dev/null +++ b/src/mainboard/amd/mayan/chromeos.fmd @@ -0,0 +1,34 @@ +FLASH@0xFF000000 16M { + SI_BIOS { + EC 4K + RW_MRC_CACHE(PRESERVE) 120K + RW_SECTION_A 4M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + RW_SECTION_B 4M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 20K + SMMSTORE(PRESERVE) 64K + RW_LEGACY(CBFS) + WP_RO@10M 6M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 448K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/amd/mayan/devicetree_morgana.cb b/src/mainboard/amd/mayan/devicetree_morgana.cb new file mode 100644 index 0000000..cfcacfa --- /dev/null +++ b/src/mainboard/amd/mayan/devicetree_morgana.cb @@ -0,0 +1,226 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# TODO: Update for mayan + +chip soc/amd/morgana + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x3f8, + .size = 8, + }, + .generic_io_range[1] = { + .base = 0x600, + .size = 256, + }, + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_16_MHZ, + .crc_check_enable = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 1, + .flash_ch_en = 0, + }" + + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | + GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + register "i2c[0].early_init" = "1" + register "i2c[1].early_init" = "1" + register "i2c[2].early_init" = "1" + register "i2c[3].early_init" = "1" + + # I2C Pad Control RX Select Configuration + register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" + register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" + + register "s0ix_enable" = "true" + + register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works + + register "usb_phy_custom" = "1" + register "usb_phy" = "{ + .Usb2PhyPort[0] = { + .compdistune = 0x3, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xe, + .sqrxtune = 0x3, + .txfslstune = 0x3, + .txpreempamptune = 0x2, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[1] = { + .compdistune = 0x3, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xe, + .sqrxtune = 0x3, + .txfslstune = 0x3, + .txpreempamptune = 0x2, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[2] = { + .compdistune = 0x3, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xe, + .sqrxtune = 0x3, + .txfslstune = 0x3, + .txpreempamptune = 0x2, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[3] = { + .compdistune = 0x3, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xe, + .sqrxtune = 0x3, + .txfslstune = 0x3, + .txpreempamptune = 0x2, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[4] = { + .compdistune = 0x3, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xe, + .sqrxtune = 0x3, + .txfslstune = 0x3, + .txpreempamptune = 0x2, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[5] = { + .compdistune = 0x3, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xe, + .sqrxtune = 0x3, + .txfslstune = 0x3, + .txpreempamptune = 0x2, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb3PhyPort[0] = { + .tx_term_ctrl = 0x2, + .rx_term_ctrl = 0x2, + .tx_vboost_lvl_en = 0x0, + .tx_vboost_lvl = 0x5, + }, + .Usb3PhyPort[1] = { + .tx_term_ctrl = 0x2, + .rx_term_ctrl = 0x2, + .tx_vboost_lvl_en = 0x0, + .tx_vboost_lvl = 0x5, + }, + .Usb3PhyPort[2] = { + .tx_term_ctrl = 0x2, + .rx_term_ctrl = 0x2, + .tx_vboost_lvl_en = 0x0, + .tx_vboost_lvl = 0x5, + }, + .ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C, + .ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C, + .BatteryChargerEnable = 0, + .PhyP3CpmP4Support = 0, + }" + + register "gpp_clk_config[0]" = "GPP_CLK_REQ" + register "gpp_clk_config[1]" = "GPP_CLK_REQ" + register "gpp_clk_config[2]" = "GPP_CLK_OFF" + register "gpp_clk_config[3]" = "GPP_CLK_REQ" + + device domain 0 on + device ref iommu on end + device ref gpp_bridge_0 on end # GBE + device ref gpp_bridge_1 on end # WIFI + device ref gpp_bridge_2 on end # NVMe SSD + device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A + device ref gfx on end # Internal GPU (GFX) + device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) + device ref crypto on end # Crypto Coprocessor + device ref xhci_0 on # USB 3.1 (USB0) + chip drivers/usb/acpi + device ref xhci_0_root_hub on + chip drivers/usb/acpi + device ref usb3_port0 on end + end + chip drivers/usb/acpi + device ref usb2_port0 on end + end + chip drivers/usb/acpi + device ref usb2_port1 on end + end + end + end + end + device ref xhci_1 on # USB 3.1 (USB1) + chip drivers/usb/acpi + device ref xhci_1_root_hub on + chip drivers/usb/acpi + device ref usb3_port2 on end + end + chip drivers/usb/acpi + device ref usb3_port3 on end + end + chip drivers/usb/acpi + device ref usb2_port2 on end + end + chip drivers/usb/acpi + device ref usb2_port3 on end + end + chip drivers/usb/acpi + device ref usb2_port4 on end + end + end + end + end + device ref acp on end # Audio Processor (ACP) + end + device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C + device ref xhci_2 on + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias xhci_2_root_hub on + chip drivers/usb/acpi + device usb 2.0 alias usb2_port5 on end + end + end + end + end + end + end + + device ref i2c_0 on end + device ref i2c_1 on end + device ref i2c_2 on end + device ref i2c_3 on end + device ref uart_0 on end # UART0 + +end diff --git a/src/mainboard/amd/mayan/dsdt.asl b/src/mainboard/amd/mayan/dsdt.asl new file mode 100644 index 0000000..7b8982a --- /dev/null +++ b/src/mainboard/amd/mayan/dsdt.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ + #include <acpi/dsdt_top.asl> + + #include <soc.asl> +} diff --git a/src/mainboard/amd/mayan/early_gpio.c b/src/mainboard/amd/mayan/early_gpio.c new file mode 100644 index 0000000..cf7166c --- /dev/null +++ b/src/mainboard/amd/mayan/early_gpio.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include "gpio.h" + +/* TODO: Update for mayan */ + +/* GPIO pins used by coreboot should be initialized in bootblock */ + +static const struct soc_amd_gpio gpio_set_stage_reset[] = { +}; + +void mainboard_program_early_gpios(void) +{ + gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset)); +} diff --git a/src/mainboard/amd/mayan/ec.c b/src/mainboard/amd/mayan/ec.c new file mode 100644 index 0000000..1b1d09b --- /dev/null +++ b/src/mainboard/amd/mayan/ec.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* TODO: Update for mayan */ + +#include <ec/acpi/ec.h> +#include "ec.h" + +#define MAYAN_EC_CMD 0x666 +#define MAYAN_EC_DATA 0x662 + +#define EC_GPIO_3_ADDR 0xA3 +#define EC_GPIO_LOM_RESET_AUX BIT(1) + +#define EC_GPIO_7_ADDR 0xA7 +#define EC_GPIO_DT_PWREN BIT(2) +#define EC_GPIO_WWAN_MODULE_RST BIT(5) + +#define EC_GPIO_8_ADDR 0xA8 +#define EC_GPIO_SMBUS0_EN BIT(0) + +#define EC_GPIO_A_ADDR 0xAA +#define EC_GPIO_WWAN_PWREN BIT(3) +#define EC_GPIO_M2_SSD0_PWREN BIT(6) +#define EC_GPIO_LOM_PWREN BIT(7) + +#define EC_GPIO_C_ADDR 0xAC +#define EC_GPIO_DT_N_WLAN_SW BIT(1) +#define EC_GPIO_MP2_SEL BIT(2) +#define EC_GPIO_WWAN_N_LOM_SW BIT(3) + +#define EC_SW02_ADDR 0xB7 +#define EC_SW02_MS BIT(7) + +static void configure_ec_gpio(void) +{ + uint8_t tmp; + + tmp = ec_read(EC_GPIO_3_ADDR); + tmp |= EC_GPIO_LOM_RESET_AUX; + ec_write(EC_GPIO_3_ADDR, tmp); + + tmp = ec_read(EC_GPIO_7_ADDR); + tmp |= EC_GPIO_WWAN_MODULE_RST | EC_GPIO_DT_PWREN; + ec_write(EC_GPIO_7_ADDR, tmp); + + tmp = ec_read(EC_GPIO_8_ADDR); + tmp |= EC_GPIO_SMBUS0_EN; + ec_write(EC_GPIO_8_ADDR, tmp); + + tmp = ec_read(EC_GPIO_A_ADDR); + tmp |= EC_GPIO_M2_SSD0_PWREN | EC_GPIO_LOM_PWREN | EC_GPIO_WWAN_PWREN; + ec_write(EC_GPIO_A_ADDR, tmp); + + tmp = ec_read(EC_GPIO_C_ADDR); + tmp |= EC_GPIO_WWAN_N_LOM_SW | EC_GPIO_MP2_SEL | EC_GPIO_DT_N_WLAN_SW; + ec_write(EC_GPIO_C_ADDR, tmp); + + tmp = ec_read(EC_SW02_ADDR); + tmp |= EC_SW02_MS; + ec_write(EC_SW02_ADDR, tmp); +} + +void mayan_ec_init(void) +{ + ec_set_ports(MAYAN_EC_CMD, MAYAN_EC_DATA); + configure_ec_gpio(); +} diff --git a/src/mainboard/amd/mayan/ec.h b/src/mainboard/amd/mayan/ec.h new file mode 100644 index 0000000..b74b236 --- /dev/null +++ b/src/mainboard/amd/mayan/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAYAN_EC_H +#define MAYAN_EC_H + +void mayan_ec_init(void); + +#endif /* MAYAN_EC_H */ diff --git a/src/mainboard/amd/mayan/gpio.c b/src/mainboard/amd/mayan/gpio.c new file mode 100644 index 0000000..62f6447 --- /dev/null +++ b/src/mainboard/amd/mayan/gpio.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include "gpio.h" + +/* TODO: Update for mayan */ + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + +}; + +void mainboard_program_gpios(void) +{ + gpio_configure_pads(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram)); +} diff --git a/src/mainboard/amd/mayan/gpio.h b/src/mainboard/amd/mayan/gpio.h new file mode 100644 index 0000000..04c98c5 --- /dev/null +++ b/src/mainboard/amd/mayan/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_program_early_gpios(void); /* bootblock GPIO configuration */ +void mainboard_program_gpios(void); /* ramstage GPIO configuration */ + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/amd/mayan/mainboard.c b/src/mainboard/amd/mayan/mainboard.c new file mode 100644 index 0000000..0f42fc9 --- /dev/null +++ b/src/mainboard/amd/mayan/mainboard.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/amd_pci_util.h> +#include <commonlib/helpers.h> +#include <device/device.h> +#include <soc/acpi.h> +#include <types.h> +#include "gpio.h" + +/* TODO: Update for mayan */ + +/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is + accessed via I/O ports 0xc00/0xc01. */ + +/* + * This controls the device -> IRQ routing. + * + * Hardcoded IRQs: + * 0: timer < soc/amd/common/acpi/lpc.asl + * 1: i8042 - Keyboard + * 2: cascade + * 8: rtc0 <- soc/amd/common/acpi/lpc.asl + * 9: acpi <- soc/amd/common/acpi/lpc.asl + */ +static const struct fch_irq_routing fch_irq_map[] = { + { PIRQ_A, 12, PIRQ_NC }, + { PIRQ_B, 14, PIRQ_NC }, + { PIRQ_C, 15, PIRQ_NC }, + { PIRQ_D, 12, PIRQ_NC }, + { PIRQ_E, 14, PIRQ_NC }, + { PIRQ_F, 15, PIRQ_NC }, + { PIRQ_G, 12, PIRQ_NC }, + { PIRQ_H, 14, PIRQ_NC }, + + { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, + { PIRQ_SD, PIRQ_NC, PIRQ_NC }, + { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, + { PIRQ_EMMC, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIO, 11, 11 }, + { PIRQ_I2C0, 10, 10 }, + { PIRQ_I2C1, 7, 7 }, + { PIRQ_I2C2, 6, 6 }, + { PIRQ_I2C3, 5, 5 }, + { PIRQ_UART0, 4, 4 }, + { PIRQ_UART1, 3, 3 }, + + /* The MISC registers are not interrupt numbers */ + { PIRQ_MISC, 0xfa, 0x00 }, + { PIRQ_MISC0, 0x91, 0x00 }, + { PIRQ_HPET_L, 0x00, 0x00 }, + { PIRQ_HPET_H, 0x00, 0x00 }, +}; + +const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +{ + *length = ARRAY_SIZE(fch_irq_map); + return fch_irq_map; +} + +static void mainboard_init(void *chip_info) +{ + mainboard_program_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/amd/mayan/port_descriptors.c b/src/mainboard/amd/mayan/port_descriptors.c new file mode 100644 index 0000000..151ad14 --- /dev/null +++ b/src/mainboard/amd/mayan/port_descriptors.c @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/i2c_simple.h> +#include <soc/gpio.h> +#include <soc/platform_descriptors.h> +#include <types.h> + +/* TODO: Update for mayan */ + +static const fsp_dxio_descriptor mayan_dxio_descriptors[] = { + { + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = 2, + .function_number = 1, + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = 2, + .link_hotplug = 3, + .clk_req = CLK_REQ3, + }, + { + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 1, + .end_logical_lane = 1, + .device_number = 2, + .function_number = 2, + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = 2, + .link_hotplug = 3, + .clk_req = CLK_REQ1, + }, + { + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 2, + .end_logical_lane = 3, + .device_number = 2, + .function_number = 3, + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = 2, + .link_hotplug = 3, + .gpio_group_id = GPIO_27, + .clk_req = CLK_REQ0, + }, +}; + +static fsp_ddi_descriptor mayan_ddi_descriptors[] = { + { /* DDI0 - eDP */ + .connector_type = DDI_EDP, + .aux_index = DDI_AUX1, + .hdp_index = DDI_HDP1 + }, + { /* DDI1 - HDMI/DP */ + .connector_type = DDI_HDMI, + .aux_index = DDI_AUX2, + .hdp_index = DDI_HDP2 + }, + { /* DDI2 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI3 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX4, + .hdp_index = DDI_HDP4, + }, + { /* DDI4 - unused */ + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX5, + .hdp_index = DDI_HDP5, + } +}; + +static uint8_t get_ddi1_type(void) +{ + const uint8_t eeprom_i2c_bus = 2; + const uint8_t eeprom_i2c_address = 0x55; + const uint16_t eeprom_connector_type_offset = 2; + uint8_t eeprom_connector_type_data[2]; + uint16_t connector_type; + + if (i2c_2ba_read_bytes(eeprom_i2c_bus, eeprom_i2c_address, + eeprom_connector_type_offset, eeprom_connector_type_data, + sizeof(eeprom_connector_type_data))) { + printk(BIOS_NOTICE, + "Display connector type couldn't be determined. Disabling DDI1.\n"); + return DDI_UNUSED_TYPE; + } + + connector_type = eeprom_connector_type_data[1] | eeprom_connector_type_data[0] << 8; + + switch (connector_type) { + case 0xc: + printk(BIOS_DEBUG, "Configuring DDI1 as HDMI.\n"); + return DDI_HDMI; + break; + case 0x13: + printk(BIOS_DEBUG, "Configuring DDI1 as DP.\n"); + return DDI_DP; + break; + case 0x14: + printk(BIOS_DEBUG, "Configuring DDI1 as eDP.\n"); + return DDI_EDP; + break; + default: + printk(BIOS_WARNING, "Unexpected display connector type %x. Disabling DDI1.\n", + connector_type); + return DDI_UNUSED_TYPE; + } +} + +void mainboard_get_dxio_ddi_descriptors( + const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + mayan_ddi_descriptors[1].connector_type = get_ddi1_type(); + + *dxio_descs = mayan_dxio_descriptors; + *dxio_num = ARRAY_SIZE(mayan_dxio_descriptors); + *ddi_descs = mayan_ddi_descriptors; + *ddi_num = ARRAY_SIZE(mayan_ddi_descriptors); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/70010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6801e6c6e706ae3878ce9e2c3d6452964235148 Gerrit-Change-Number: 70010 Gerrit-PatchSet: 4 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: security/tpm: support compiling in multiple TPM drivers
by build bot (Jenkins) (Code Review) 27 Nov '22

27 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Michał Żygowski, Matt DeVillier, Christian Walter, Julius Werner, Krystian Hebel, Fred Reitberger, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69162 ) Change subject: security/tpm: support compiling in multiple TPM drivers ...................................................................... Patch Set 11: Verified+1 (2 comments) File src/security/tpm/tis.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164636): https://review.coreboot.org/c/coreboot/+/69162/comment/42e46b2e_cb9ed60e PS11, Line 110: #define __tis_driver __attribute__((used, section(".rodata.tis_driver"))) Prefer __used over __attribute__((used)) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164636): https://review.coreboot.org/c/coreboot/+/69162/comment/ae1a696f_ff8229bd PS11, Line 110: #define __tis_driver __attribute__((used, section(".rodata.tis_driver"))) Prefer __section(".rodata.tis_driver") over __attribute__((section(".rodata.tis_driver"))) -- To view, visit https://review.coreboot.org/c/coreboot/+/69162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44c5a1d825afe414c2f5c2c90f4cfe41ba9bef5f Gerrit-Change-Number: 69162 Gerrit-PatchSet: 11 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 27 Nov 2022 17:09:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: security/tpm/: turn tis_{init,open} into tis_probe
by Sergii Dmytruk (Code Review) 27 Nov '22

27 Nov '22

Attention is currently required from: Michał Żygowski, Christian Walter, Julius Werner, Krystian Hebel, Yu-Ping Wu. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68991 ) Change subject: security/tpm/: turn tis_{init,open} into tis_probe ...................................................................... Patch Set 2: (1 comment) File src/security/tpm/tss/tcg-1.2/tss.c: https://review.coreboot.org/c/coreboot/+/68991/comment/2d897661_cefe85d7 PS2, Line 35: tis_sendrecv > Before this patch, `tis_sendrecv` was defined in each tis implementation, so it wouldn't possibly be […] Done. I meant that skipping initialization could result in failure in multiple ways with this deference being only one of them. -- To view, visit https://review.coreboot.org/c/coreboot/+/68991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4ce35ada24e3959ea1a518c29d431b4ae123809 Gerrit-Change-Number: 68991 Gerrit-PatchSet: 2 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sun, 27 Nov 2022 17:09:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: security/tpm: resolve conflicts in TSS implementations
by Sergii Dmytruk (Code Review) 27 Nov '22

27 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Michał Żygowski, Frans Hendriks, Matt DeVillier, Christian Walter, Julius Werner, Krystian Hebel, Fred Reitberger, Sergii Dmytruk, Felix Held. Hello build bot (Jenkins), Raul Rangel, Frans Hendriks, Matt DeVillier, Julius Werner, Krystian Hebel, Erik van den Bogaert, Jason Glenesk, Michał Żygowski, Christian Walter, Fred Reitberger, Yu-Ping Wu, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69160 to look at the new patch set (#11). Change subject: security/tpm: resolve conflicts in TSS implementations ...................................................................... security/tpm: resolve conflicts in TSS implementations No functional changes. Refactor code such that there won't be any compiler or linker errors if TSS 1.2 and TSS 2.0 were both compiled in. One might want to support both TPM families for example if TPM is pluggable, in which case currently one has to update both TPM device and firmware. Change-Id: Ia0ea5a917c46ada9fc3274f17240e12bca98db6a Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/drivers/crb/tis.c M src/security/tpm/Makefile.inc M src/security/tpm/tspi/tspi.c M src/security/tpm/tss.h M src/security/tpm/tss/tcg-1.2/tss.c M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c A src/security/tpm/tss/tss.c M src/security/tpm/tss/vendor/cr50/cr50.c A src/security/tpm/tss1.h A src/security/tpm/tss2.h M src/security/vboot/secdata_tpm.c M src/soc/amd/common/psp_verstage/psp_verstage.c M src/vendorcode/eltan/security/mboot/mboot.c M src/vendorcode/google/chromeos/tpm2.c 15 files changed, 416 insertions(+), 281 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/69160/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/69160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0ea5a917c46ada9fc3274f17240e12bca98db6a Gerrit-Change-Number: 69160 Gerrit-PatchSet: 11 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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